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verilog: strip leading and trailing spaces in macro args
[yosys.git]
/
tests
/
techmap
/
.gitignore
2020-01-29
Claire Wolf
Merge branch 'vector_fix' of https://github.com/Kmanfi...
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2019-09-27
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-09-04
Pepijn de Vos
Merge remote-tracking branch 'diego/gowin'
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2019-08-30
Eddie Hung
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into...
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2019-08-30
David Shah
Merge branch 'master' into xc7dsp
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2019-08-29
Sergey
Merge pull request #3 from YosysHQ/Sergey/tests_ice40
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2019-08-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into xaig_...
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2019-08-28
Eddie Hung
Merge remote-tracking branch 'origin/clifford/async2syn...
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2019-08-28
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-28
David Shah
Merge pull request #1332 from YosysHQ/dave/ecp5gsr
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2019-08-27
Clifford Wolf
Merge pull request #1325 from YosysHQ/eddie/sat_init
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2019-08-27
Eddie Hung
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
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2019-08-26
Eddie Hung
Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23
Eddie Hung
Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23
Eddie Hung
Merge branch 'master' into mwk/xilinx_bufgmap
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2019-08-23
Eddie Hung
tests/techmap/run-test.sh to cope with *.ys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-02-21
Clifford Wolf
Added tests/techmap/mem_simple_4x1
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