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Merge remote-tracking branch 'origin/master' into xc7srl
[yosys.git]
/
tests
/
tools
/
autotest.sh
2019-04-22
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
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2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
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2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
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2019-04-22
Clifford Wolf
Merge pull request #916 from YosysHQ/map_cells_before_m...
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2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
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2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
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2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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2019-04-22
Clifford Wolf
Merge pull request #945 from YosysHQ/clifford/libwb
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2019-04-21
Clifford Wolf
Fix tests
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-19
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-19
Eddie Hung
Merge pull request #808 from eddiehung/read_aiger
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2019-03-19
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-03-14
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-03-09
Clifford Wolf
Merge pull request #859 from smunaut/ice40_braminit
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2019-03-01
Clifford Wolf
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
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2019-03-01
Clifford Wolf
Hotfix for "make test"
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2019-02-28
Clifford Wolf
Merge pull request #834 from YosysHQ/clifford/siminit
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2019-02-28
Clifford Wolf
Add "write_verilog -siminit"
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2019-02-28
Clifford Wolf
Merge pull request #794 from daveshah1/ecp5improve
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2019-02-28
Clifford Wolf
Merge pull request #827 from ucb-bar/firrtlfixes
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2019-02-26
Jim Lawson
Fix FIRRTL to Verilog process instance subfield assignment.
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2019-02-24
Clifford Wolf
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
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2019-02-22
Clifford Wolf
Merge pull request #819 from YosysHQ/clifford/optd
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2019-02-22
Clifford Wolf
Merge pull request #820 from YosysHQ/clifford/fix810
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2019-02-22
Clifford Wolf
Merge pull request #740 from daveshah1/improve_dress
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2019-02-21
Clifford Wolf
Merge pull request #818 from YosysHQ/clifford/dffsrfix
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2019-02-21
Clifford Wolf
Merge pull request #821 from eddiehung/dff_init
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2019-02-21
Eddie Hung
Revert "Add -B option to autotest.sh to append to backe...
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2019-02-19
Eddie Hung
Merge branch 'master' into read_aiger
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2019-02-19
Eddie Hung
Merge pull request #805 from eddiehung/dff_init
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2019-02-18
Eddie Hung
Merge branch 'dff_init' into read_aiger
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2019-02-17
Eddie Hung
One more merge conflict
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2019-02-17
Eddie Hung
Merge branch 'dff_init' into read_aiger
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into dff_init
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2019-02-17
Eddie Hung
Merge https://github.com/YosysHQ/yosys into read_aiger
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2019-02-17
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-02-17
Clifford Wolf
Merge pull request #811 from ucb-bar/firrtlfixes
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2019-02-15
Jim Lawson
Update cells supported for verilog to FIRRTL conversion.
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2019-02-08
Eddie Hung
Merge remote-tracking branch 'origin/dff_init' into...
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2019-02-08
Eddie Hung
Support and differentiate between ASCII and binary...
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2019-02-06
Eddie Hung
Merge branch 'dff_init' of https://github.com/eddiehung...
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2019-02-06
Eddie Hung
Revert most of autotest.sh; for non *.v use Yosys to...
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2019-02-06
Eddie Hung
Add -B option to autotest.sh to append to backend_opts
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2019-02-05
Eddie Hung
Add tests
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-15
Clifford Wolf
Merge pull request #513 from udif/pr_reg_wire_error
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2018-07-04
Aman Goel
Merge branch 'YosysHQ-master'
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2018-07-04
Aman Goel
Merging with official repo
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2018-06-06
Clifford Wolf
Merge pull request #561 from udif/pr_skip_typo
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2018-06-05
Udi Finkelstein
Fixed typo (sikp -> skip)
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2018-05-13
Clifford Wolf
Merge pull request #505 from thefallenidealist/FreeBSD_...
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2018-05-06
Johnny Sorocil
autotest.sh: Change from /bin/bash to /usr/bin/env...
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2016-09-23
Clifford Wolf
Merge branch 'master' of https://github.com/brouhaha...
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2016-09-20
Clifford Wolf
Added autotest.sh -I
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2016-08-06
Clifford Wolf
Added "test_autotb -seed" (and "autotest.sh -S")
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-07-02
Clifford Wolf
Fixed autotest.sh handling of `timescale
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2016-05-20
Clifford Wolf
Improvements and fixes in autotest.sh script and test_a...
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2016-05-20
Clifford Wolf
Merge branch 'master' of https://github.com/Kmanfi...
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2016-05-19
Kaj Tuomi
Fix for Modelsim transcript line warp issue #164
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2016-03-25
Clifford Wolf
Merge pull request #136 from ravenexp/master
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2016-03-25
Sergey Kvachonok
Optionally use ${CC} when compiling test utils.
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2015-08-14
Larry Doolittle
Another block of spelling fixes
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-12
Clifford Wolf
Some test related fixes
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-14
Clifford Wolf
Added "synth" command
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2014-09-06
Clifford Wolf
Fixed autotest for non-basename arguments
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2014-08-30
Clifford Wolf
Added autotest -e (do not use -noexpr on write_verilog)
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2014-08-03
Clifford Wolf
Added "wreduce" to some of the standard test benches
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2014-08-01
Clifford Wolf
Added "test_autotb -n <num_iter>" option
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2014-07-30
Clifford Wolf
Added "make -j{N}" support to "make test"
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2014-07-29
Clifford Wolf
Renamed "write_autotest" to "test_autotb" and moved...
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2014-07-21
Clifford Wolf
Added "opt_const -fine" and "opt_reduce -fine"
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2014-07-17
Clifford Wolf
Also simulate unmapped memories in "make test"
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2014-07-16
Clifford Wolf
Added note to "make test": use git checkout of iverilog
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2014-03-17
Clifford Wolf
Progress in Verific bindings
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2014-03-14
Clifford Wolf
Progress in Verific bindings
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2014-02-15
Clifford Wolf
Added frontend (-f) option to autotest.sh
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2014-02-13
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-13
Clifford Wolf
Updated ABC and some related changes
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2014-02-12
Clifford Wolf
Merge pull request #26 from ahmedirfan1983/btor
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2014-02-12
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2014-02-12
Clifford Wolf
Disabled "abc -dff" in "make test" for now (waiting...
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2014-02-03
Clifford Wolf
Replaced isim with xsim in tests/tools/autotest.sh...
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-02
Clifford Wolf
Added autotest.sh -p option
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2013-12-31
Clifford Wolf
Use "abc -dff" in "make test"
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2013-12-31
Clifford Wolf
Fixed commented out techmap call in tests/tools/autotest.sh
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2013-11-24
Clifford Wolf
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
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2013-11-24
Clifford Wolf
Added modelsim support to autotest
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2013-09-15
Clifford Wolf
Moved common techlib files to techlibs/common
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2013-08-09
Clifford Wolf
Added $div and $mod technology mapping
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2013-07-09
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-07-09
Clifford Wolf
Major redesign of expr width/sign detecion (verilog...
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2013-01-05
Clifford Wolf
initial import
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