git.libre-soc.org Git - yosys.git/history

2014-02-03	Clifford Wolf	Replaced isim with xsim in tests/tools/autotest.sh...	blob \| commitdiff \| raw
2014-01-03	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-01-02	Clifford Wolf	Added autotest.sh -p option	blob \| commitdiff \| raw \| diff to current
2013-12-31	Clifford Wolf	Use "abc -dff" in "make test"	blob \| commitdiff \| raw \| diff to current
2013-12-31	Clifford Wolf	Fixed commented out techmap call in tests/tools/autotest.sh	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	blob \| commitdiff \| raw \| diff to current
2013-11-24	Clifford Wolf	Added modelsim support to autotest	blob \| commitdiff \| raw \| diff to current
2013-09-15	Clifford Wolf	Moved common techlib files to techlibs/common	blob \| commitdiff \| raw \| diff to current
2013-08-09	Clifford Wolf	Added $div and $mod technology mapping	blob \| commitdiff \| raw \| diff to current
2013-07-09	Clifford Wolf	Merge branch 'master' of github.com:cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2013-07-09	Clifford Wolf	Major redesign of expr width/sign detecion (verilog...	blob \| commitdiff \| raw \| diff to current
2013-01-05	Clifford Wolf	initial import	blob \| commitdiff \| raw \| diff to current