Merge remote-tracking branch 'origin/master' into eddie/muxpack
[yosys.git] / tests / tools /
2019-06-08 Clifford WolfMerge pull request #1078 from YosysHQ/eddie/muxcover_costs
2019-06-07 Eddie HungMerge branch 'master' into eddie/muxpack
2019-06-07 Clifford WolfMerge pull request #1079 from YosysHQ/eddie/fix_read_aiger
2019-06-07 Eddie HungUse ABC to convert from AIGER to Verilog
2019-06-07 Clifford WolfMerge branch 'pr_elab_sys_tasks' of https://github...
2019-06-07 Clifford WolfMerge branch 'tux3-implicit_named_connection'
2019-06-07 Clifford WolfMerge branch 'implicit_named_connection' of https:...
2019-06-06 tux3SystemVerilog support for implicit named port connections
2019-05-21 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-05-06 Clifford WolfMerge pull request #871 from YosysHQ/verific_import
2019-05-06 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-05-03 Eddie HungMerge remote-tracking branch 'origin/master' into cliff...
2019-05-03 Eddie Hungiverilog with simcells.v as well
2019-04-30 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-04-30 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-04-22 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-22 Clifford WolfMerge pull request #905 from christian-krieg/feature...
2019-04-22 Clifford WolfMerge pull request #941 from Wren6991/sim_lib_io_clke
2019-04-22 Clifford WolfMerge branch 'master' of https://github.com/dh73/yosys_...
2019-04-22 Clifford WolfMerge pull request #916 from YosysHQ/map_cells_before_m...
2019-04-22 Clifford WolfMerge pull request #911 from mmicko/gowin-nobram
2019-04-22 Clifford WolfMerge pull request #909 from zachjs/master
2019-04-22 Clifford WolfMerge pull request #944 from YosysHQ/clifford/pmux2shiftx
2019-04-22 Clifford WolfMerge pull request #945 from YosysHQ/clifford/libwb
2019-04-21 Clifford WolfFix tests
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-19 Eddie HungMerge pull request #808 from eddiehung/read_aiger
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-03-01 Clifford WolfHotfix for "make test"
2019-02-28 Clifford WolfMerge pull request #834 from YosysHQ/clifford/siminit
2019-02-28 Clifford WolfAdd "write_verilog -siminit"
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes
2019-02-26 Jim LawsonFix FIRRTL to Verilog process instance subfield assignment.
2019-02-26 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-22 Clifford WolfMerge pull request #819 from YosysHQ/clifford/optd
2019-02-22 Clifford WolfMerge pull request #820 from YosysHQ/clifford/fix810
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-21 Clifford WolfMerge pull request #818 from YosysHQ/clifford/dffsrfix
2019-02-21 Clifford WolfMerge pull request #821 from eddiehung/dff_init
2019-02-21 Eddie HungRevert "Add -B option to autotest.sh to append to backe...
2019-02-19 Eddie HungMerge branch 'master' into read_aiger
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init
2019-02-18 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungOne more merge conflict
2019-02-17 Eddie HungMerge branch 'dff_init' into read_aiger
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion.
2019-02-08 Eddie HungMerge remote-tracking branch 'origin/dff_init' into...
2019-02-08 Eddie HungSupport and differentiate between ASCII and binary...
2019-02-06 Eddie HungMerge branch 'dff_init' of https://github.com/eddiehung...
2019-02-06 Eddie HungRevert most of autotest.sh; for non *.v use Yosys to...
2019-02-06 Eddie HungAdd -B option to autotest.sh to append to backend_opts
2019-02-05 Eddie HungAdd tests
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-07-04 Aman GoelMerge branch 'YosysHQ-master'
2018-07-04 Aman GoelMerging with official repo
2018-06-06 Clifford WolfMerge pull request #561 from udif/pr_skip_typo
2018-06-05 Udi FinkelsteinFixed typo (sikp -> skip)
2018-05-13 Clifford WolfMerge pull request #505 from thefallenidealist/FreeBSD_...
2018-05-06 Johnny Sorocilautotest.sh: Change from /bin/bash to /usr/bin/env...
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
2016-09-22 Eric SmithAdd optional SEED=n command line option to Makefile...
2016-09-20 Clifford WolfAdded autotest.sh -I
2016-09-13 Clifford WolfMerge pull request #228 from Kmanfi/test
2016-09-13 Kaj TuomiFix for modules with big interfaces.
2016-08-06 Clifford WolfAdded "test_autotb -seed" (and "autotest.sh -S")
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-07-02 Clifford WolfFixed autotest.sh handling of `timescale
2016-05-20 Clifford WolfImprovements and fixes in autotest.sh script and test_a...
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi...
2016-05-19 Kaj TuomiFix for Modelsim transcript line warp issue #164
2016-03-25 Clifford WolfMerge pull request #136 from ravenexp/master
2016-03-25 Sergey KvachonokOptionally use ${CC} when compiling test utils.
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-08-22 Clifford WolfSwitched to Python 3
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-12 Clifford WolfSome test related fixes
2015-01-18 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-01-18 Clifford WolfRefactoring of memory_bram and xilinx brams
2015-01-13 Clifford WolfTiny fix in vcdcd.pl
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-14 Clifford WolfAdded "synth" command
2014-09-06 Clifford WolfFixed autotest for non-basename arguments
2014-08-30 Clifford WolfAdded autotest -e (do not use -noexpr on write_verilog)
2014-08-03 Clifford WolfAdded "wreduce" to some of the standard test benches
2014-08-01 Clifford WolfAdded "test_autotb -n <num_iter>" option
next