Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
[yosys.git] / tests / tools /
2014-02-19 Clifford WolfAdded vcd2txt.pl and txt2tikztiming.py (tests/tools...
2014-02-15 Clifford WolfAdded frontend (-f) option to autotest.sh
2014-02-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-13 Clifford WolfUpdated ABC and some related changes
2014-02-12 Clifford WolfMerge pull request #26 from ahmedirfan1983/btor
2014-02-12 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-02-12 Clifford WolfDisabled "abc -dff" in "make test" for now (waiting...
2014-02-05 Clifford WolfRemoved old unused files from tests/
2014-02-03 Clifford WolfReplaced isim with xsim in tests/tools/autotest.sh...
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-02 Clifford WolfAdded autotest.sh -p option
2013-12-31 Clifford WolfUse "abc -dff" in "make test"
2013-12-31 Clifford WolfFixed commented out techmap call in tests/tools/autotest.sh
2013-11-24 Clifford WolfRenamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 Clifford WolfAdded modelsim support to autotest
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common
2013-08-09 Clifford WolfAdded $div and $mod technology mapping
2013-07-09 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-07-09 Clifford WolfMajor redesign of expr width/sign detecion (verilog...
2013-05-16 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-05-16 Clifford WolfMerge branch 'bugfix'
2013-05-14 Clifford WolfImproved vcdcd.pl (added -d option)
2013-05-14 Clifford WolfSome improvements in vcdcd.pl
2013-01-05 Clifford Wolfadded more .gitignore files (make test)
2013-01-05 Clifford Wolfinitial import