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synth_gatemate: Add block RAM cascade support
[yosys.git]
/
tests
/
2021-11-13
Patrick Urban
synth_gatemate: Update pass
tree
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commitdiff
2021-11-13
Patrick Urban
synth_gatemate: Apply new test practice with assert-max
tree
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commitdiff
2021-11-13
Patrick Urban
synth_gatemate: Fix fsm test
tree
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commitdiff
2021-11-13
Patrick Urban
Allow initial blocks to be disabled during tests
tree
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commitdiff
2021-11-13
Patrick Urban
synth_gatemate: Initial implementation
tree
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commitdiff
2021-11-10
Claire Xen
Merge pull request #3077 from YosysHQ/claire/genlib
tree
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commitdiff
2021-11-09
Marcelina Kościelnicka
iopadmap: Add native support for negative-polarity...
tree
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commitdiff
2021-10-27
Marcelina Kościelnicka
dfflegalize: Add tests for aldff lowering.
tree
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commitdiff
2021-10-27
Marcelina Kościelnicka
dfflegalize: Add tests targetting aldff.
tree
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commitdiff
2021-10-27
Marcelina Kościelnicka
dfflegalize: Refactor, add aldff support.
tree
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commitdiff
2021-10-26
Zachary Snow
verilog: use derived module info to elaborate cell...
tree
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commitdiff
2021-10-21
Marcelina Kościelnicka
extract_reduce: Refactor and fix input signal construction.
tree
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commitdiff
2021-10-19
Miodrag Milanović
Merge pull request #3045 from galibert/master
tree
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commitdiff
2021-10-19
Claire Xenia Wolf
Fixes in vcdcd.pl for newer Perl versions
tree
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commitdiff
2021-10-11
Claire Xen
Merge pull request #3039 from YosysHQ/claire/verific_aldff
tree
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commitdiff
2021-10-08
Marcelina Kościelnicka
Fix a regression from #3035.
tree
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commitdiff
2021-10-07
Marcelina Kościelnicka
FfData: some refactoring.
tree
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commitdiff
2021-09-24
Claire Xen
Merge pull request #3014 from YosysHQ/claire/fix-vgtest
tree
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commitdiff
2021-09-23
Claire Xenia Wolf
Fix "make vgtest" so it runs to the end (but now it...
tree
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commitdiff
2021-09-21
Zachary Snow
sv: support wand and wor of data types
tree
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commitdiff
2021-09-21
Zachary Snow
verilog: fix multiple AST_PREFIX scope resolution issues
tree
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commitdiff
2021-09-09
Eddie Hung
abc9: make re-entrant (#2993)
tree
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commitdiff
2021-09-09
Eddie Hung
abc9: holes module to instantiate cells with NEW_ID...
tree
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commitdiff
2021-09-09
Eddie Hung
abc9: replace cell type/parameters if derived type...
tree
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commitdiff
2021-08-31
Zachary Snow
sv: support declaration in generate for initialization
tree
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commitdiff
2021-08-30
Zachary Snow
sv: support declaration in procedural for initialization
tree
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commitdiff
2021-08-22
Marcelina Kościelnicka
opt_clean: Make the init attribute follow the FF's Q.
tree
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commitdiff
2021-08-20
Pepijn de Vos
Gowin: deal with active-low tristate (#2971)
tree
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commitdiff
2021-08-14
Marcelina Kościelnicka
proc_prune: Make assign removal and promotion per-bit...
tree
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commitdiff
2021-08-13
Marcelina Kościelnicka
Add opt_mem_widen pass.
tree
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commitdiff
2021-08-13
Marcelina Kościelnicka
memory_share: Add -nosat and -nowiden options.
tree
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commitdiff
2021-08-13
Marcelina Kościelnicka
memory_dff: Recognize soft transparency logic.
tree
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commitdiff
2021-08-13
Marcelina Kościelnicka
Add new opt_mem_priority pass.
tree
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commitdiff
2021-08-13
Miodrag Milanović
Merge pull request #2932 from YosysHQ/mwk/logger-check...
tree
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commitdiff
2021-08-13
Brett Witherspoon
sv: improve support for wire and var with user-defined...
tree
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commitdiff
2021-08-11
Marcelina Kościelnicka
test/arch/{ecp5,ice40}/memories.ys: Use read_verilog...
tree
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commitdiff
2021-08-11
Marcelina Kościelnicka
memory_dff: Recognize read ports with reset / initial...
tree
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commitdiff
2021-08-11
Marcelina Kościelnicka
proc_memwr: Use the v2 memwr cell.
tree
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commitdiff
2021-08-11
Marcelina Kościelnicka
Add v2 memory cells.
tree
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commitdiff
2021-08-07
Marcelina Kościelnicka
opt_merge: Use FfInitVals.
tree
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commitdiff
2021-07-30
Zachary Snow
proc_rmdead: use explicit pattern set when there are...
tree
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commitdiff
2021-07-30
Zachary Snow
genrtlil: add width detection for AST_PREFIX nodes
tree
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commitdiff
2021-07-29
Marcelina Kościelnicka
opt_lut: Allow more than one -dlogic per cell type.
tree
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commitdiff
2021-07-29
Zachary Snow
verilog: save and restore overwritten macro arguments
tree
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commitdiff
2021-07-28
Marcelina Kościelnicka
verilog: Emit $meminit_v2 cell.
tree
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commitdiff
2021-07-27
Marcelina Kościelnicka
opt_expr: Propagate constants to port connections.
tree
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commitdiff
2021-07-17
whitequark
Merge pull request #2879 from whitequark/cxxrtl-fix...
tree
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commitdiff
2021-07-16
Rupert Swarbrick
Add support for parsing the SystemVerilog 'bind' construct
tree
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commitdiff
2021-07-16
whitequark
Merge pull request #2870 from whitequark/cxxrtl-fix...
tree
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commitdiff
2021-07-15
Zachary Snow
sv: fix two struct access bugs
tree
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commitdiff
2021-07-15
Rupert Swarbrick
Add a test for interfaces on modules loaded on-demand
tree
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commitdiff
2021-07-05
Claire Xen
Merge pull request #2835 from YosysHQ/verific_command
tree
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commitdiff
2021-06-18
Miodrag Milanović
Merge pull request #2836 from YosysHQ/gatecat/pyosys...
tree
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commitdiff
2021-06-17
Zachary Snow
sv: fix up end label checking
tree
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commitdiff
2021-06-11
Marcelina Kościelnicka
Add regression test for #2824.
tree
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commitdiff
2021-06-09
Claire Xen
Merge pull request #2817 from YosysHQ/claire/fixemails
tree
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commitdiff
2021-06-09
Claire Xenia Wolf
More deadname stuff
tree
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commitdiff
2021-06-09
Claire Xenia Wolf
More deadname stuff
tree
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commitdiff
2021-06-09
Claire Xenia Wolf
Use HTTPS for website links, gatecat email
tree
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commitdiff
2021-06-09
Claire Xenia Wolf
Fix files with CRLF line endings
tree
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commitdiff
2021-06-08
Zachary Snow
verilog: check for module scope identifiers during...
tree
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commitdiff
2021-06-08
Zachary Snow
mem2reg: tolerate out of bounds constant accesses
tree
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commitdiff
2021-06-07
Claire Xenia Wolf
Fixing old e-mail addresses and deadnames
tree
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commitdiff
2021-06-01
Zachary Snow
sv: support tasks and functions within packages
tree
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commitdiff
2021-05-31
Marcelina Kościelnicka
memory_map: Improve start_offset handling.
tree
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commitdiff
2021-05-25
Marcelina Kościelnicka
memory_bram: Reuse extract_rdff helper for make_outreg.
tree
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commitdiff
2021-05-25
Zachary Snow
verilog: fix case expression sign and width handling
tree
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commitdiff
2021-05-25
Zachary Snow
sv: support remaining assignment operators
tree
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commitdiff
2021-05-25
Marcelina Kościelnicka
opt_mem_feedback: Respect write port priority.
tree
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commitdiff
2021-05-24
Marcelina Kościelnicka
opt_mem_feedback: Rewrite feedback path finding logic.
tree
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commitdiff
2021-05-23
Marcelina Kościelnicka
Add new helper class for merging FFs into cells, use...
tree
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commitdiff
2021-05-23
Marcelina Kościelnicka
opt_mem: Remove write ports with const-0 EN.
tree
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commitdiff
2021-05-20
Marcelina Kościelnicka
tests/blif: Add missing gitignore
tree
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commitdiff
2021-05-15
gatecat
intel_alm: Fix illegal carry chains
tree
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commitdiff
2021-05-15
gatecat
intel_alm: Add global buffer insertion
tree
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commitdiff
2021-05-15
gatecat
intel_alm: Add IO buffer insertion
tree
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commitdiff
2021-05-10
Zachary Snow
sv: check validity of package end label
tree
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commitdiff
2021-05-08
Marcelina Kościelnicka
blif: Use library cells' start_offset and upto for...
tree
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commitdiff
2021-05-04
Marcelina Kościelnicka
opt_dff: Fix NOT gates wired in reverse.
tree
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commitdiff
2021-04-21
Claire Xen
Merge pull request #2669 from YosysHQ/claire/ice40defaults
tree
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commitdiff
2021-04-20
Claire Xenia Wolf
Add default assignments to SB_LUT4
tree
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commitdiff
2021-04-17
Lofty
quicklogic: ABC9 synthesis
tree
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commitdiff
2021-03-30
Zachary Snow
preproc: test coverage for #2712
tree
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commitdiff
2021-03-30
Eddie Hung
abc9: uniquify blackboxes like whiteboxes (#2695)
tree
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commitdiff
2021-03-30
Eddie Hung
abc9: fix SCC issues (#2694)
tree
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commitdiff
2021-03-23
N. Engelhardt
Merge pull request #2696 from nakengelhardt/guidelines
tree
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commitdiff
2021-03-23
Marcelina Kościelnicka
quicklogic: Add .gitignore file for test outputs.
tree
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commitdiff
2021-03-21
Xiretza
verilog: check entire user type stack for type definition
tree
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commitdiff
2021-03-19
Zachary Snow
sv: allow typenames as function return types
tree
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commitdiff
2021-03-19
Miodrag Milanović
Merge pull request #2681 from msinger/fix-issue2606
tree
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commitdiff
2021-03-18
Lofty
quicklogic: PolarPro 3 support
tree
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commitdiff
2021-03-17
Marcelina Kościelnicka
ast: Use better parameter serialization for paramod...
tree
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commitdiff
2021-03-17
gatecat
Blackbox all whiteboxes after synthesis
tree
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commitdiff
2021-03-17
Zachary Snow
sv: carry over global typedefs from previous files
tree
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commitdiff
2021-03-17
Xiretza
verilog: fix buf/not primitives with multiple outputs
tree
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commitdiff
2021-03-17
gatecat
blackbox: Include whiteboxed modules
tree
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commitdiff
2021-03-16
Zachary Snow
verilog: support module scope identifiers in parametric...
tree
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commitdiff
2021-03-15
Marcelina Kościelnicka
proc_arst: Add special-casing of clock signal in condit...
tree
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commitdiff
2021-03-15
Marcelina Kościelnicka
opt_clean: Remove init attribute bits together with...
tree
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commitdiff
2021-03-15
Marcelina Kościelnicka
rtlil: Disallow 0-width chunks in SigSpec.
tree
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commitdiff
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