Merge pull request #768 from whitequark/opt_lut_elim
[yosys.git] / tests /
2019-01-01 Clifford WolfMerge pull request #768 from whitequark/opt_lut_elim
2018-12-31 whitequarkopt_lut: eliminate LUTs evaluating to constants or...
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches
2018-12-29 Larry DoolittleSquelch a little more trailing whitespace
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt
2018-12-16 Clifford WolfMerge pull request #725 from olofk/ram4k-init
2018-12-16 Clifford WolfMerge pull request #714 from daveshah1/abc_preserve_naming
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map...
2018-12-16 Clifford WolfMerge pull request #722 from whitequark/rename_src
2018-12-16 Clifford WolfMerge pull request #720 from whitequark/master
2018-12-07 whitequarkequiv_opt: pass -D EQUIV when techmapping.
2018-12-07 whitequarkequiv_opt: new command, for verifying optimization...
2018-12-07 David ShahMerge pull request #727 from whitequark/opt_lut
2018-12-07 whitequarkopt_lut: leave intact LUTs with cascade feeding module...
2018-12-06 Clifford WolfAdd missing .gitignore
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708
2018-12-05 Clifford WolfMerge pull request #718 from whitequark/gate2lut
2018-12-05 whitequarkgate2lut: new techlib, for converting Yosys gates to...
2018-12-05 Clifford WolfMerge pull request #713 from Diego-HR/master
2018-12-05 Clifford WolfMerge pull request #712 from mmicko/anlogic-support
2018-12-05 Clifford WolfMerge pull request #717 from whitequark/opt_lut
2018-12-05 whitequarkopt_lut: add -dlogic, to avoid disturbing logic such...
2018-12-05 whitequarkopt_lut: new pass, to combine LUTs for tighter packing.
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the...
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface...
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the...
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram
2018-10-19 Clifford WolfMerge pull request #671 from rafaeltp/master
2018-10-19 Clifford WolfMerge pull request #670 from rubund/feature/basic_svint...
2018-10-18 Ruben UndheimBasic test for checking correct synthesis of SystemVeri...
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-07-04 Aman GoelMerge branch 'YosysHQ-master'
2018-07-04 Aman GoelMerging with official repo
2018-06-06 Clifford WolfMerge pull request #561 from udif/pr_skip_typo
2018-06-05 Udi FinkelsteinFixed typo (sikp -> skip)
2018-06-05 Udi FinkelsteinModified errors into warnings
2018-06-05 Udi Finkelsteinreg_wire_error test needs the -sv flag so it is run...
2018-05-13 Clifford WolfMerge pull request #505 from thefallenidealist/FreeBSD_...
2018-05-06 Johnny Sorocilautotest.sh: Change from /bin/bash to /usr/bin/env...
2018-03-27 Clifford WolfFix tests/simple/specify.v
2018-03-27 Udi FinkelsteinFirst draft of Verilog parser support for specify block...
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge...
2018-02-28 Clifford WolfMerge branch 'verificsva-ng'
2018-02-27 Clifford WolfMajor redesign of Verific SVA importer
2018-02-21 Clifford WolfAdd support for SVA throughout via Verific
2018-02-18 Clifford WolfAdd support for SVA sequence concatenation ranges via...
2018-02-18 Clifford WolfAdd support for SVA until statements via Verific
2018-02-16 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2018-02-15 Clifford WolfFix verific PRIM_SVA_AT handling in properties with...
2017-11-09 dh73Merge https://github.com/cliffordwolf/yosys
2017-10-20 Clifford WolfRemove PSL example from tests/sva/
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2017-09-29 Clifford WolfMerge pull request #425 from udif/udif_dollar_bits
2017-09-26 Udi Finkelstein$size() now works correctly for all cases!
2017-09-26 Udi Finkelstein$size() seems to work now with or without the optional...
2017-09-26 Udi FinkelsteinAdded $bits() for memories as well.
2017-09-26 Udi Finkelstein$size() now works with memories as well!
2017-09-26 Udi FinkelsteinAdd $size() function. At the moment it works only on...
2017-07-28 Clifford WolfAdd simple VHDL+PSL example
2017-07-27 Clifford WolfImprove Verific SVA importer
2017-07-27 Clifford WolfAdd counter.sv SVA test
2017-07-27 Clifford WolfImprove SVA tests, add Makefile and scripts
2017-07-22 Clifford WolfAdd more SVA test cases for future Verific work
2017-07-22 Clifford WolfAdd some simple SVA test cases for future Verific work
2017-04-12 Larry DoolittleSquelch trailing whitespace
2017-01-05 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-01-04 Clifford WolfFixed typo in tests/simple/arraycells.v
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-11 Clifford WolfMerge branch 'LSS-USP-unit-test-structure'
2016-12-11 Clifford WolfBuild hotfix in tests/unit/Makefile
2016-12-10 rodrigosiqueiraImproved unit test structure
2016-12-04 rodrigosiqueiraAdded required structure to implement unit tests
2016-11-15 Clifford WolfAdded support for hierarchical defparams
2016-11-01 Clifford WolfAdded support for (single-clock) transparent memories...
2016-10-11 Clifford WolfFixed "make test" for git head of iverilog
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
2016-09-22 Eric SmithAdd optional SEED=n command line option to Makefile...
2016-09-20 Clifford WolfAdded autotest.sh -I
2016-09-13 Clifford WolfMerge pull request #228 from Kmanfi/test
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