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Use mem2reg on memories that only have constant-index write ports
[yosys.git] / tests /
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode tree | commitdiff
2019-03-01 Clifford WolfHotfix for "make test" tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #834 from YosysHQ/clifford/siminit tree | commitdiff
2019-02-28 Clifford WolfAdd "write_verilog -siminit" tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve tree | commitdiff
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes tree | commitdiff
2019-02-26 Jim LawsonFix FIRRTL to Verilog process instance subfield assignment. tree | commitdiff
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes tree | commitdiff
2019-02-24 Clifford WolfMerge pull request #824 from litghost/fix_reduce_on_ff tree | commitdiff
2019-02-24 Clifford WolfFix handling of defparam for when default_nettype is... tree | commitdiff
2019-02-23 Jim LawsonAddress requested changes - don't require non-$ name. tree | commitdiff
2019-02-22 Keith RothmanFix WREDUCE on FF not fixing ARST_VALUE parameter. tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #819 from YosysHQ/clifford/optd tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #820 from YosysHQ/clifford/fix810 tree | commitdiff
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress tree | commitdiff
2019-02-21 Clifford WolfMerge pull request #818 from YosysHQ/clifford/dffsrfix tree | commitdiff
2019-02-21 Clifford WolfMerge pull request #786 from YosysHQ/pmgen tree | commitdiff
2019-02-21 Clifford WolfMerge pull request #821 from eddiehung/dff_init tree | commitdiff
2019-02-21 Eddie HungRevert "Add -B option to autotest.sh to append to backe... tree | commitdiff
2019-02-21 Eddie HungMerge pull request #817 from eddiehung/dff_init tree | commitdiff
2019-02-20 Eddie HungRemove simple_defparam tests tree | commitdiff
2019-02-19 Jim LawsonFix normal (non-array) hierarchy -auto-top. tree | commitdiff
2019-02-19 Eddie HungMerge pull request #805 from eddiehung/dff_init tree | commitdiff
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init tree | commitdiff
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into... tree | commitdiff
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes tree | commitdiff
2019-02-15 Jim LawsonAppend (instead of over-writing) EXTRA_FLAGS tree | commitdiff
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion. tree | commitdiff
2019-02-06 Eddie HungAdd tests for simple cases using defparam tree | commitdiff
2019-02-06 Eddie HungAdd -B option to autotest.sh to append to backend_opts tree | commitdiff
2019-02-06 Eddie HungExtend testcase tree | commitdiff
2019-02-06 Eddie HungAdd testcase tree | commitdiff
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master tree | commitdiff
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t... tree | commitdiff
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword' tree | commitdiff
2019-01-27 Clifford WolfRemove asicworld tests for (unsupported) switch-level... tree | commitdiff
2019-01-03 Clifford WolfMerge pull request #775 from whitequark/opt_flowmap tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #770 from whitequark/opt_expr_cmp tree | commitdiff
2019-01-02 whitequarkopt_expr: improve simplification of comparisons with... tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #755 from Icenowy/anlogic-dram-init tree | commitdiff
2019-01-02 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #750 from Icenowy/anlogic-ff-init tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #773 from whitequark/opt_lut_elim_fixes tree | commitdiff
2019-01-02 Clifford WolfMerge pull request #771 from whitequark/techmap_cmp2lut tree | commitdiff
2019-01-02 whitequarkcmp2lut: new techmap pass. tree | commitdiff
2019-01-02 whitequarkopt_expr: refactor simplification of unsigned X<onehot... tree | commitdiff
2019-01-02 whitequarkopt_expr: refactor simplification of signed X>=0 and... tree | commitdiff
2019-01-02 whitequarkopt_expr: simplify any unsigned comparisons with all... tree | commitdiff
2019-01-01 Clifford WolfMerge pull request #768 from whitequark/opt_lut_elim tree | commitdiff
2018-12-31 whitequarkopt_lut: eliminate LUTs evaluating to constants or... tree | commitdiff
2018-12-31 Clifford WolfMerge pull request #766 from Icenowy/anlogic-latches tree | commitdiff
2018-12-29 Larry DoolittleSquelch a little more trailing whitespace tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737 tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #725 from olofk/ram4k-init tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #714 from daveshah1/abc_preserve_naming tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map... tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #722 from whitequark/rename_src tree | commitdiff
2018-12-16 Clifford WolfMerge pull request #720 from whitequark/master tree | commitdiff
2018-12-07 whitequarkequiv_opt: pass -D EQUIV when techmapping. tree | commitdiff
2018-12-07 whitequarkequiv_opt: new command, for verifying optimization... tree | commitdiff
2018-12-07 David ShahMerge pull request #727 from whitequark/opt_lut tree | commitdiff
2018-12-07 whitequarkopt_lut: leave intact LUTs with cascade feeding module... tree | commitdiff
2018-12-06 Clifford WolfAdd missing .gitignore tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #709 from smunaut/issue_708 tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #718 from whitequark/gate2lut tree | commitdiff
2018-12-05 whitequarkgate2lut: new techlib, for converting Yosys gates to... tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #713 from Diego-HR/master tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #712 from mmicko/anlogic-support tree | commitdiff
2018-12-05 Clifford WolfMerge pull request #717 from whitequark/opt_lut tree | commitdiff
2018-12-05 whitequarkopt_lut: add -dlogic, to avoid disturbing logic such... tree | commitdiff
2018-12-05 whitequarkopt_lut: new pass, to combine LUTs for tighter packing. tree | commitdiff
2018-12-01 Clifford WolfMerge pull request #676 from rafaeltp/master tree | commitdiff
2018-10-25 Clifford WolfMerge pull request #678 from whentze/master tree | commitdiff
2018-10-25 Clifford WolfMerge pull request #679 from udif/pr_syntax_error tree | commitdiff
2018-10-24 Udi FinkelsteinRename the generic "Syntax error" message from the... tree | commitdiff
2018-10-23 Clifford WolfMerge pull request #677 from daveshah1/ecp5_dsp tree | commitdiff
2018-10-21 rafaeltpMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-10-20 Clifford WolfMerge pull request #674 from rubund/feature/svinterface... tree | commitdiff
2018-10-20 Ruben UndheimSupport for SystemVerilog interfaces as a port in the... tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #672 from daveshah1/fix_bram tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #671 from rafaeltp/master tree | commitdiff
2018-10-19 Clifford WolfMerge pull request #670 from rubund/feature/basic_svint... tree | commitdiff
2018-10-18 Ruben UndheimBasic test for checking correct synthesis of SystemVeri... tree | commitdiff
2018-10-18 Clifford WolfMerge pull request #659 from rubund/sv_interfaces tree | commitdiff
2018-10-12 Ruben UndheimSupport for 'modports' for System Verilog interfaces tree | commitdiff
2018-10-12 Ruben UndheimSynthesis support for SystemVerilog interfaces tree | commitdiff
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error tree | commitdiff
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master tree | commitdiff
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file... tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master tree | commitdiff
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error tree | commitdiff
2018-07-04 Aman GoelMerge branch 'YosysHQ-master' tree | commitdiff
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