Add abc9_ops -check, -prep_times, -write_box for required times
[yosys.git] / tests /
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell...
2019-12-05 Eddie HungAdd WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 Eddie Hungabc9_map.v to transform INIT=1 to INIT=0
2019-12-04 Marcin Kościelnickiiopadmap: Refactor and fix tristate buffer mapping...
2019-12-03 Eddie HungCheck SB_CARRY name also preserved
2019-12-03 Eddie HungAdd testcase
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-12-03 Pepijn de Vosupdate test
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values
2019-12-02 David ShahMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix
2019-12-01 David Shahabc9: Fix breaking of SCCs
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
2019-11-28 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungAdd multiple driver testcase
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Clifford WolfMerge pull request #1534 from YosysHQ/mwk/opt_share-fix
2019-11-27 Eddie HungMerge pull request #1535 from YosysHQ/eddie/write_xaige...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/write_xaiger...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-27 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-27 Eddie HungRevert "submod to bitty rather bussy, for bussy wires...
2019-11-27 Eddie HungFix wire width
2019-11-27 Eddie HungNo need for -abc9
2019-11-27 Marcin Kościelnickiopt_share: Fix handling of fine cells.
2019-11-27 Eddie HungMerge branch 'master' into xaig_dff
2019-11-27 Eddie HungAdd citation
2019-11-27 Eddie HungRemove notes
2019-11-27 Eddie HungAdd testcase derived from fastfir_dynamictaps benchmark
2019-11-26 Eddie HungAdd testcase where \init is copied
2019-11-25 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-25 Pepijn de Vosattempt to fix formatting
2019-11-25 Pepijn de Vosgowin: add and test dff init values
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge branch 'xaig_dff' of github.com:YosysHQ/yosys...
2019-11-23 Eddie HungMerge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungRemove redundant flatten
2019-11-23 Eddie HungStray dump
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungAdd another test with constant driver
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/clkpart...
2019-11-23 Eddie HungAdd testcase for signal used as part input part output
2019-11-23 Eddie HungMerge remote-tracking branch 'origin/eddie/submod_po...
2019-11-23 Eddie HungCleanup spacing
2019-11-23 Eddie HungAdd testcase
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungMerge branch 'eddie/clkpart' into xaig_dff
2019-11-22 Eddie HungMerge branch 'master' of github.com:YosysHQ/yosys
2019-11-22 Eddie HungMissing endmodule
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests.
2019-11-22 Eddie HungAnother sloppy mistake!
2019-11-22 Eddie HungMerge remote-tracking branch 'origin/xaig_dff' into...
2019-11-22 Eddie Hungasync2sync -> clk2fflogic
2019-11-22 Eddie HungMerge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-22 Eddie HungAdd test
2019-11-21 David Shahsv: Add tests for SV always types
2019-11-20 Eddie HungAdd multi clock test
2019-11-20 Eddie HungAdd a equiv test too
2019-11-20 Eddie HungAdd two tests
2019-11-19 Eddie HungMerge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Marcin KościelnickiFix #1462, #1480.
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix
2019-11-18 Marcin KościelnickiFix #1496.
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-11 Miodrag MilanovicFixed tests
2019-11-06 Pepijn de Vosfix wide luts
2019-10-30 Pepijn de Vosdon't cound exact luts in big muxes; futile and fragile
2019-10-28 Pepijn de Vosadd tristate buffer and test
2019-10-28 Pepijn de Vosdo not use wide luts in testcase
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 Pepijn de VosALU sim tweaks
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de VosAdd some tests
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-18 Miodrag MilanovićMerge pull request #1454 from YosysHQ/mmicko/common_tests
2019-10-18 Miodrag Milanovicfixed error
2019-10-18 Miodrag MilanovicUnify verilog style
2019-10-18 Miodrag MilanovicCommon memory test now shared
2019-10-18 Miodrag MilanovicRemove not needed tests
2019-10-18 Miodrag MilanovicShare common tests
2019-10-18 Miodrag Milanovicfix yosys path
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