Merge pull request #1515 from YosysHQ/clifford/svastuff
[yosys.git] / tests /
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests.
2019-11-21 David Shahsv: Add tests for SV always types
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Marcin KościelnickiFix #1462, #1480.
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix
2019-11-18 Marcin KościelnickiFix #1496.
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-11 Miodrag MilanovicFixed tests
2019-11-06 Pepijn de Vosfix wide luts
2019-10-30 Pepijn de Vosdon't cound exact luts in big muxes; futile and fragile
2019-10-28 Pepijn de Vosadd tristate buffer and test
2019-10-28 Pepijn de Vosdo not use wide luts in testcase
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 Pepijn de VosALU sim tweaks
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de VosAdd some tests
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-18 Miodrag MilanovićMerge pull request #1454 from YosysHQ/mmicko/common_tests
2019-10-18 Miodrag Milanovicfixed error
2019-10-18 Miodrag MilanovicUnify verilog style
2019-10-18 Miodrag MilanovicCommon memory test now shared
2019-10-18 Miodrag MilanovicRemove not needed tests
2019-10-18 Miodrag MilanovicShare common tests
2019-10-18 Miodrag Milanovicfix yosys path
2019-10-18 Miodrag MilanovicFix path to yosys
2019-10-18 Miodrag MilanovicMoved all tests in arch sub directory
2019-10-18 Miodrag MilanovicAdd async2sync
2019-10-18 Miodrag MilanovićMerge pull request #1435 from YosysHQ/mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge pull request #1434 from YosysHQ/mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge pull request #1421 from YosysHQ/eddie/pr1352
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-18 Miodrag MilanovićMerge pull request #1420 from YosysHQ/eddie/pr1363
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-17 Miodrag MilanovicMake equivalence work with latest master
2019-10-17 Miodrag Milanovicremove not needed top module
2019-10-17 Miodrag Milanovicremove not needed top module
2019-10-17 Miodrag Milanovicsplit muxes synth per type
2019-10-17 Miodrag MilanovicTest dffs separetely
2019-10-17 Miodrag MilanovicSplit latches into separete tests
2019-10-17 Miodrag MilanovicFix formatting
2019-10-17 Miodrag MilanovicClean verilog code from not used define block
2019-10-17 Miodrag MilanovicRemoved alu and div_mod test as agreed, ignore generate...
2019-10-17 Miodrag MilanovicTest per flip-flop type
2019-10-17 Eddie HungAdd -assert
2019-10-17 Eddie HungUse built-in async2sync call as per #1417
2019-10-17 Eddie HungUpdate mul test to DSP48E1
2019-10-17 Eddie HungUpdate area for div_mod
2019-10-17 Eddie HungAdd comment for lack of tristate logic pointing to...
2019-10-17 Eddie HungMove $x to end as 7f0eec8
2019-10-17 SergeyDegtyaradffs test update (equiv_opt -multiclock)
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyDegtyarAdd comment with expected behavior for latches,tribuf...
2019-10-17 SergeyDegtyarFix latches.ys test
2019-10-17 SergeyDegtyarRemove xilinx_ug901 tests (will be moved to yosys-tests)
2019-10-17 SergeyDegtyarAdd smoke tests to tests/xilinx
2019-10-17 SergeyDegtyarAdd comments for unproven cells.
2019-10-17 SergeyDegtyarAdd tests for Xilinx UG901 examples
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-10-14 Clifford WolfMerge pull request #1448 from YosysHQ/daveshah1-sv...
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-08 Eddie HungRevert "Add test that is expecting to fail"
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-06 Clifford WolfMerge pull request #1439 from YosysHQ/eddie/fix_ice40_w...
2019-10-05 Eddie HungMissing 'accept' at end of ice40_wrapcarry, spotted...
2019-10-04 Miodrag MilanovicSplit mux tests per type
2019-10-04 Miodrag MilanovicSplit latch check
2019-10-04 Miodrag Milanovicsplit rest od ff's
2019-10-04 Miodrag MilanovicSeparate check for ff's types
2019-10-04 Miodrag MilanovicCleaned tests
2019-10-04 Miodrag MilanovicRemove not needed tests
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/efinix' of https://github...
2019-10-04 Miodrag MilanovicCleanup and formating
2019-10-04 Miodrag Milanovicsplit latches into separate checks
2019-10-04 Miodrag Milanoviccheck muxes per type
2019-10-04 Miodrag Milanoviccheck ff's separately
2019-10-04 Miodrag MilanovicCleanup top modules and not used defines
2019-10-04 Miodrag Milanovicremove alu test
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/anlogic' of https://github...
2019-10-04 Miodrag MilanovicCheck latches type one by one
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