Add "make coverage"
[yosys.git] / tests /
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-08-15 Clifford WolfMerge pull request #590 from hzeller/remaining-file...
2018-08-15 Clifford WolfMerge pull request #576 from cr1901/no-resource
2018-08-15 Clifford WolfMerge pull request #592 from japm48/master
2018-08-15 Clifford WolfMerge pull request #513 from udif/pr_reg_wire_error
2018-07-04 Aman GoelMerge branch 'YosysHQ-master'
2018-07-04 Aman GoelMerging with official repo
2018-06-06 Clifford WolfMerge pull request #561 from udif/pr_skip_typo
2018-06-05 Udi FinkelsteinFixed typo (sikp -> skip)
2018-06-05 Udi FinkelsteinModified errors into warnings
2018-06-05 Udi Finkelsteinreg_wire_error test needs the -sv flag so it is run...
2018-05-13 Clifford WolfMerge pull request #505 from thefallenidealist/FreeBSD_...
2018-05-06 Johnny Sorocilautotest.sh: Change from /bin/bash to /usr/bin/env...
2018-03-27 Clifford WolfFix tests/simple/specify.v
2018-03-27 Udi FinkelsteinFirst draft of Verilog parser support for specify block...
2018-03-11 Udi FinkelsteinThis PR should be the base for discussion, do not merge...
2018-02-28 Clifford WolfMerge branch 'verificsva-ng'
2018-02-27 Clifford WolfMajor redesign of Verific SVA importer
2018-02-21 Clifford WolfAdd support for SVA throughout via Verific
2018-02-18 Clifford WolfAdd support for SVA sequence concatenation ranges via...
2018-02-18 Clifford WolfAdd support for SVA until statements via Verific
2018-02-16 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2018-02-15 Clifford WolfFix verific PRIM_SVA_AT handling in properties with...
2017-11-09 dh73Merge https://github.com/cliffordwolf/yosys
2017-10-20 Clifford WolfRemove PSL example from tests/sva/
2017-09-29 Clifford WolfAllow $size and $bits in verilog mode, actually check...
2017-09-29 Clifford WolfMerge pull request #425 from udif/udif_dollar_bits
2017-09-26 Udi Finkelstein$size() now works correctly for all cases!
2017-09-26 Udi Finkelstein$size() seems to work now with or without the optional...
2017-09-26 Udi FinkelsteinAdded $bits() for memories as well.
2017-09-26 Udi Finkelstein$size() now works with memories as well!
2017-09-26 Udi FinkelsteinAdd $size() function. At the moment it works only on...
2017-07-28 Clifford WolfAdd simple VHDL+PSL example
2017-07-27 Clifford WolfImprove Verific SVA importer
2017-07-27 Clifford WolfAdd counter.sv SVA test
2017-07-27 Clifford WolfImprove SVA tests, add Makefile and scripts
2017-07-22 Clifford WolfAdd more SVA test cases for future Verific work
2017-07-22 Clifford WolfAdd some simple SVA test cases for future Verific work
2017-04-12 Larry DoolittleSquelch trailing whitespace
2017-01-05 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-01-04 Clifford WolfFixed typo in tests/simple/arraycells.v
2016-12-23 Andrew ZonenbergMerge pull request #1 from azonenberg-hk/master
2016-12-12 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-12-11 Clifford WolfMerge branch 'LSS-USP-unit-test-structure'
2016-12-11 Clifford WolfBuild hotfix in tests/unit/Makefile
2016-12-10 rodrigosiqueiraImproved unit test structure
2016-12-04 rodrigosiqueiraAdded required structure to implement unit tests
2016-11-15 Clifford WolfAdded support for hierarchical defparams
2016-11-01 Clifford WolfAdded support for (single-clock) transparent memories...
2016-10-11 Clifford WolfFixed "make test" for git head of iverilog
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
2016-09-22 Eric SmithAdd optional SEED=n command line option to Makefile...
2016-09-20 Clifford WolfAdded autotest.sh -I
2016-09-13 Clifford WolfMerge pull request #228 from Kmanfi/test
2016-09-13 Kaj TuomiFix for modules with big interfaces.
2016-08-22 Clifford WolfFixed bug with memories that do not have a down-to...
2016-08-21 Clifford WolfAdded another mem2reg test case
2016-08-21 Clifford WolfAnother bugfix in mem2reg code
2016-08-06 Clifford WolfAdded "test_autotb -seed" (and "autotest.sh -S")
2016-07-08 Clifford WolfFixed mem assignment in left-hand-side concatenation
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-07-02 Clifford WolfFixed autotest.sh handling of `timescale
2016-06-17 Clifford WolfFixed init issue in mem2reg_test2 test case
2016-05-29 Clifford WolfAdded opt_expr support for div/mod by power-of-two
2016-05-20 Clifford WolfSome fixes in tests/asicworld/*_tb.v
2016-05-20 Clifford WolfImprovements and fixes in autotest.sh script and test_a...
2016-05-20 Clifford WolfMerge branch 'master' of https://github.com/Kmanfi...
2016-05-19 Kaj TuomiFix for Modelsim transcript line warp issue #164
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfBugfix and improvements in memory_share
2016-03-25 Clifford WolfMerge pull request #136 from ravenexp/master
2016-03-25 Sergey KvachonokOptionally use ${CC} when compiling test utils.
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-11-30 Clifford WolfAdded tests/simple/graphtest.v
2015-11-12 Clifford WolfMore bugfixes in handling of parameters in tasks and...
2015-11-11 Clifford WolfFixed handling of parameters and localparams in functions
2015-10-31 Clifford WolfBugfix in memory_dff
2015-10-31 Clifford WolfImprovements in wreduce
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-08-22 Clifford WolfSwitched to Python 3
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-13 Clifford WolfFixed CRLF line endings
2015-08-13 Clifford WolfSome ASCII encoding fixes (comments and docs) by Larry...
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-19 Clifford WolfProgress in SMV back-end
2015-06-18 Clifford WolfProgress in SMV back-end
2015-06-08 luke whittlesey$mem cell in verilog backend : grouped writes by clock
2015-06-04 luke whittleseyBug fix in $mem verilog backend + changed tests/bram...
2015-05-18 Clifford Wolfbugfix in blif front-end
2015-05-17 Clifford Wolfadded vloghtb test_febe.sh
2015-05-11 Clifford Wolfchanged file() to open() in python scripts
2015-04-07 Clifford WolfAdded "pmuxtree" command
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-03-20 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-03-20 Clifford Wolffix for python 2.6.6
2015-02-14 Clifford WolfVarious fixes for memories with offsets
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