Adding a note (TODO) in the memory_params.ys check file
[yosys.git] / tests /
2019-12-12 Diego HAdding a note (TODO) in the memory_params.ys check...
2019-12-12 Diego HUpdating RAMB36E1 thresholds. Adding test for both...
2019-12-12 Diego HMerge https://github.com/YosysHQ/yosys into bram_xilinx
2019-12-11 David ShahMerge pull request #1564 from ZirconiumX/intel_housekeeping
2019-12-10 Eddie HungMerge pull request #1545 from YosysHQ/eddie/ice40_wrapc...
2019-12-09 Eddie Hungunmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 Eddie Hungice40_wrapcarry to really preserve attributes via ...
2019-12-07 Eddie HungMerge pull request #1555 from antmicro/fix-macc-xilinx...
2019-12-07 Eddie HungDrop keep=0 attributes on SB_CARRY
2019-12-06 Jan Kowalewskitests: arch: xilinx: Change order of arguments in macc.sh
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell...
2019-12-05 Eddie HungAdd WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-04 Marcin Kościelnickiiopadmap: Refactor and fix tristate buffer mapping...
2019-12-03 Eddie HungCheck SB_CARRY name also preserved
2019-12-03 Eddie HungAdd testcase
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit
2019-12-03 Pepijn de Vosupdate test
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values
2019-12-02 David ShahMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix
2019-12-01 David Shahabc9: Fix breaking of SCCs
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_...
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
2019-11-27 Clifford WolfMerge pull request #1534 from YosysHQ/mwk/opt_share-fix
2019-11-27 Eddie HungMerge pull request #1535 from YosysHQ/eddie/write_xaige...
2019-11-27 Eddie HungNo need for -abc9
2019-11-27 Marcin Kościelnickiopt_share: Fix handling of fine cells.
2019-11-27 Eddie HungAdd citation
2019-11-27 Eddie HungRemove notes
2019-11-27 Eddie HungAdd testcase derived from fastfir_dynamictaps benchmark
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path.
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable
2019-11-25 Pepijn de Vosattempt to fix formatting
2019-11-25 Pepijn de Vosgowin: add and test dff init values
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests.
2019-11-21 David Shahsv: Add tests for SV always types
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin
2019-11-19 Marcin KościelnickiFix #1462, #1480.
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix
2019-11-18 Marcin KościelnickiFix #1496.
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp...
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com...
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-11-11 Miodrag MilanovicFixed tests
2019-11-06 Pepijn de Vosfix wide luts
2019-10-30 Pepijn de Vosdon't cound exact luts in big muxes; futile and fragile
2019-10-28 Pepijn de Vosadd tristate buffer and test
2019-10-28 Pepijn de Vosdo not use wide luts in testcase
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog...
2019-10-24 Pepijn de VosALU sim tweaks
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
2019-10-21 Pepijn de VosAdd some tests
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ...
2019-10-18 Miodrag MilanovićMerge pull request #1454 from YosysHQ/mmicko/common_tests
2019-10-18 Miodrag Milanovicfixed error
2019-10-18 Miodrag MilanovicUnify verilog style
2019-10-18 Miodrag MilanovicCommon memory test now shared
2019-10-18 Miodrag MilanovicRemove not needed tests
2019-10-18 Miodrag MilanovicShare common tests
2019-10-18 Miodrag Milanovicfix yosys path
2019-10-18 Miodrag MilanovicFix path to yosys
2019-10-18 Miodrag MilanovicMoved all tests in arch sub directory
2019-10-18 Miodrag MilanovicAdd async2sync
2019-10-18 Miodrag MilanovićMerge pull request #1435 from YosysHQ/mmicko/efinix
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix
2019-10-18 Miodrag MilanovićMerge pull request #1434 from YosysHQ/mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge pull request #1421 from YosysHQ/eddie/pr1352
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-18 Miodrag MilanovićMerge pull request #1420 from YosysHQ/eddie/pr1363
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-17 Miodrag MilanovicMake equivalence work with latest master
2019-10-17 Miodrag Milanovicremove not needed top module
2019-10-17 Miodrag Milanovicremove not needed top module
2019-10-17 Miodrag Milanovicsplit muxes synth per type
2019-10-17 Miodrag MilanovicTest dffs separetely
2019-10-17 Miodrag MilanovicSplit latches into separete tests
2019-10-17 Miodrag MilanovicFix formatting
2019-10-17 Miodrag MilanovicClean verilog code from not used define block
2019-10-17 Miodrag MilanovicRemoved alu and div_mod test as agreed, ignore generate...
2019-10-17 Miodrag MilanovicTest per flip-flop type
2019-10-17 Eddie HungAdd -assert
2019-10-17 Eddie HungUse built-in async2sync call as per #1417
2019-10-17 Eddie HungUpdate mul test to DSP48E1
2019-10-17 Eddie HungUpdate area for div_mod
2019-10-17 Eddie HungAdd comment for lack of tristate logic pointing to...
2019-10-17 Eddie HungMove $x to end as 7f0eec8
2019-10-17 SergeyDegtyaradffs test update (equiv_opt -multiclock)
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
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