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write_xaiger to inst each cell type once, do not call techmap/aigmap
[yosys.git] / tests /
2019-12-05 Clifford WolfMerge pull request #1551 from whitequark/manual-cell... tree | commitdiff
2019-12-04 Marcin Kościelnickiiopadmap: Refactor and fix tristate buffer mapping... tree | commitdiff
2019-12-03 Clifford WolfMerge pull request #1524 from pepijndevos/gowindffinit tree | commitdiff
2019-12-03 Pepijn de Vosupdate test tree | commitdiff
2019-12-03 Pepijn de VosUse -match-init to not synth contradicting init values tree | commitdiff
2019-12-02 David ShahMerge pull request #1542 from YosysHQ/dave/abc9-loop-fix tree | commitdiff
2019-12-01 David Shahabc9: Fix breaking of SCCs tree | commitdiff
2019-11-29 Miodrag MilanovićMerge pull request #1540 from YosysHQ/mwk/xilinx-bufpll tree | commitdiff
2019-11-27 Eddie HungMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_... tree | commitdiff
2019-11-27 Clifford WolfMerge pull request #1501 from YosysHQ/dave/mem_copy_attr tree | commitdiff
2019-11-27 Clifford WolfMerge pull request #1534 from YosysHQ/mwk/opt_share-fix tree | commitdiff
2019-11-27 Eddie HungMerge pull request #1535 from YosysHQ/eddie/write_xaige... tree | commitdiff
2019-11-27 Eddie HungNo need for -abc9 tree | commitdiff
2019-11-27 Marcin Kościelnickiopt_share: Fix handling of fine cells. tree | commitdiff
2019-11-27 Eddie HungAdd citation tree | commitdiff
2019-11-27 Eddie HungRemove notes tree | commitdiff
2019-11-27 Eddie HungAdd testcase derived from fastfir_dynamictaps benchmark tree | commitdiff
2019-11-25 Marcin Kościelnickiclkbufmap: Add support for inverters in clock path. tree | commitdiff
2019-11-25 Marcin Kościelnickixilinx: Use INV instead of LUT1 when applicable tree | commitdiff
2019-11-25 Pepijn de Vosattempt to fix formatting tree | commitdiff
2019-11-25 Pepijn de Vosgowin: add and test dff init values tree | commitdiff
2019-11-22 Clifford WolfMerge pull request #1511 from YosysHQ/dave/always tree | commitdiff
2019-11-22 Marcin Kościelnickigowin: Remove show command from tests. tree | commitdiff
2019-11-21 David Shahsv: Add tests for SV always types tree | commitdiff
2019-11-19 Clifford WolfMerge pull request #1449 from pepijndevos/gowin tree | commitdiff
2019-11-19 Marcin KościelnickiFix #1462, #1480. tree | commitdiff
2019-11-18 Clifford WolfMerge pull request #1497 from YosysHQ/mwk/extract-fa-fix tree | commitdiff
2019-11-18 Marcin KościelnickiFix #1496. tree | commitdiff
2019-11-16 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-11-14 Clifford WolfMerge pull request #1444 from btut/feature/python_wrapp... tree | commitdiff
2019-11-14 Clifford WolfMerge pull request #1465 from YosysHQ/dave/ice40_timing_sim tree | commitdiff
2019-11-14 Clifford WolfMerge branch 'label-bads-btor' of https://github.com... tree | commitdiff
2019-11-13 whitequarkMerge pull request #1488 from whitequark/flowmap-fixes tree | commitdiff
2019-11-12 Clifford WolfMerge pull request #1484 from YosysHQ/clifford/cmp2luteqne tree | commitdiff
2019-11-11 Pepijn de Vosfix fsm test with proper clock enable polarity tree | commitdiff
2019-11-11 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-11-11 Miodrag MilanovicFixed tests tree | commitdiff
2019-11-06 Pepijn de Vosfix wide luts tree | commitdiff
2019-10-30 Pepijn de Vosdon't cound exact luts in big muxes; futile and fragile tree | commitdiff
2019-10-28 Pepijn de Vosadd tristate buffer and test tree | commitdiff
2019-10-28 Pepijn de Vosdo not use wide luts in testcase tree | commitdiff
2019-10-27 Clifford WolfMerge pull request #1393 from whitequark/write_verilog... tree | commitdiff
2019-10-24 Pepijn de VosALU sim tweaks tree | commitdiff
2019-10-22 Clifford WolfMerge pull request #1452 from nakengelhardt/fix_dsp_mem_reg tree | commitdiff
2019-10-21 Pepijn de VosAdd some tests tree | commitdiff
2019-10-21 Pepijn de VosMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-10-18 Miodrag MilanovićMerge pull request #1454 from YosysHQ/mmicko/common_tests tree | commitdiff
2019-10-18 Miodrag Milanovicfixed error tree | commitdiff
2019-10-18 Miodrag MilanovicUnify verilog style tree | commitdiff
2019-10-18 Miodrag MilanovicCommon memory test now shared tree | commitdiff
2019-10-18 Miodrag MilanovicRemove not needed tests tree | commitdiff
2019-10-18 Miodrag MilanovicShare common tests tree | commitdiff
2019-10-18 Miodrag Milanovicfix yosys path tree | commitdiff
2019-10-18 Miodrag MilanovicFix path to yosys tree | commitdiff
2019-10-18 Miodrag MilanovicMoved all tests in arch sub directory tree | commitdiff
2019-10-18 Miodrag MilanovicAdd async2sync tree | commitdiff
2019-10-18 Miodrag MilanovićMerge pull request #1435 from YosysHQ/mmicko/efinix tree | commitdiff
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/efinix tree | commitdiff
2019-10-18 Miodrag MilanovićMerge pull request #1434 from YosysHQ/mmicko/anlogic tree | commitdiff
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic tree | commitdiff
2019-10-18 Miodrag MilanovićMerge pull request #1421 from YosysHQ/eddie/pr1352 tree | commitdiff
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352 tree | commitdiff
2019-10-18 Miodrag MilanovićMerge pull request #1420 from YosysHQ/eddie/pr1363 tree | commitdiff
2019-10-18 Miodrag Milanovichierarchy - proc reorder tree | commitdiff
2019-10-18 Miodrag Milanovichierarchy - proc reorder tree | commitdiff
2019-10-18 Miodrag Milanovichierarchy - proc reorder tree | commitdiff
2019-10-18 Miodrag Milanovichierarchy - proc reorder tree | commitdiff
2019-10-17 Miodrag MilanovicMake equivalence work with latest master tree | commitdiff
2019-10-17 Miodrag Milanovicremove not needed top module tree | commitdiff
2019-10-17 Miodrag Milanovicremove not needed top module tree | commitdiff
2019-10-17 Miodrag Milanovicsplit muxes synth per type tree | commitdiff
2019-10-17 Miodrag MilanovicTest dffs separetely tree | commitdiff
2019-10-17 Miodrag MilanovicSplit latches into separete tests tree | commitdiff
2019-10-17 Miodrag MilanovicFix formatting tree | commitdiff
2019-10-17 Miodrag MilanovicClean verilog code from not used define block tree | commitdiff
2019-10-17 Miodrag MilanovicRemoved alu and div_mod test as agreed, ignore generate... tree | commitdiff
2019-10-17 Miodrag MilanovicTest per flip-flop type tree | commitdiff
2019-10-17 Eddie HungAdd -assert tree | commitdiff
2019-10-17 Eddie HungUse built-in async2sync call as per #1417 tree | commitdiff
2019-10-17 Eddie HungUpdate mul test to DSP48E1 tree | commitdiff
2019-10-17 Eddie HungUpdate area for div_mod tree | commitdiff
2019-10-17 Eddie HungAdd comment for lack of tristate logic pointing to... tree | commitdiff
2019-10-17 Eddie HungMove $x to end as 7f0eec8 tree | commitdiff
2019-10-17 SergeyDegtyaradffs test update (equiv_opt -multiclock) tree | commitdiff
2019-10-17 SergeyFix div_mod test tree | commitdiff
2019-10-17 SergeyFix div_mod test tree | commitdiff
2019-10-17 SergeyFix div_mod test tree | commitdiff
2019-10-17 SergeyFix div_mod test tree | commitdiff
2019-10-17 SergeyFix div_mod test tree | commitdiff
2019-10-17 SergeyFix div_mod test tree | commitdiff
2019-10-17 SergeyDegtyarAdd comment with expected behavior for latches,tribuf... tree | commitdiff
2019-10-17 SergeyDegtyarFix latches.ys test tree | commitdiff
2019-10-17 SergeyDegtyarRemove xilinx_ug901 tests (will be moved to yosys-tests) tree | commitdiff
2019-10-17 SergeyDegtyarAdd smoke tests to tests/xilinx tree | commitdiff
2019-10-17 SergeyDegtyarAdd comments for unproven cells. tree | commitdiff
2019-10-17 SergeyDegtyarAdd tests for Xilinx UG901 examples tree | commitdiff
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ... tree | commitdiff
2019-10-14 Clifford WolfMerge pull request #1448 from YosysHQ/daveshah1-sv... tree | commitdiff
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack tree | commitdiff
2019-10-08 Eddie HungRevert "Add test that is expecting to fail" tree | commitdiff
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