Add "scratchpad" to CHANGELOG
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2019-10-18 Miodrag MilanovićMerge pull request #1434 from YosysHQ/mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge branch 'master' into mmicko/anlogic
2019-10-18 Miodrag MilanovićMerge pull request #1421 from YosysHQ/eddie/pr1352
2019-10-18 Miodrag MilanovićMerge branch 'master' into eddie/pr1352
2019-10-18 Miodrag MilanovićMerge pull request #1420 from YosysHQ/eddie/pr1363
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-18 Miodrag Milanovichierarchy - proc reorder
2019-10-17 Miodrag MilanovicMake equivalence work with latest master
2019-10-17 Miodrag Milanovicremove not needed top module
2019-10-17 Miodrag Milanovicremove not needed top module
2019-10-17 Miodrag Milanovicsplit muxes synth per type
2019-10-17 Miodrag MilanovicTest dffs separetely
2019-10-17 Miodrag MilanovicSplit latches into separete tests
2019-10-17 Miodrag MilanovicFix formatting
2019-10-17 Miodrag MilanovicClean verilog code from not used define block
2019-10-17 Miodrag MilanovicRemoved alu and div_mod test as agreed, ignore generate...
2019-10-17 Miodrag MilanovicTest per flip-flop type
2019-10-17 Eddie HungAdd -assert
2019-10-17 Eddie HungUse built-in async2sync call as per #1417
2019-10-17 Eddie HungUpdate mul test to DSP48E1
2019-10-17 Eddie HungUpdate area for div_mod
2019-10-17 Eddie HungAdd comment for lack of tristate logic pointing to...
2019-10-17 Eddie HungMove $x to end as 7f0eec8
2019-10-17 SergeyDegtyaradffs test update (equiv_opt -multiclock)
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyFix div_mod test
2019-10-17 SergeyDegtyarAdd comment with expected behavior for latches,tribuf...
2019-10-17 SergeyDegtyarFix latches.ys test
2019-10-17 SergeyDegtyarRemove xilinx_ug901 tests (will be moved to yosys-tests)
2019-10-17 SergeyDegtyarAdd smoke tests to tests/xilinx
2019-10-17 SergeyDegtyarAdd comments for unproven cells.
2019-10-17 SergeyDegtyarAdd tests for Xilinx UG901 examples
2019-10-15 Benedikt TutzerMerge branch 'master' of https://github.com/YosysHQ...
2019-10-14 Clifford WolfMerge pull request #1448 from YosysHQ/daveshah1-sv...
2019-10-14 Clifford WolfUse "(id)" instead of "id" for types as temporary hack
2019-10-08 Eddie HungRevert "Add test that is expecting to fail"
2019-10-08 Eddie HungMerge pull request #1432 from YosysHQ/eddie/fix1427
2019-10-08 Eddie HungMerge pull request #1433 from YosysHQ/eddie/equiv_opt_a...
2019-10-08 Eddie HungMerge pull request #1437 from YosysHQ/eddie/abc_to_abc9
2019-10-08 Eddie HungMerge pull request #1438 from YosysHQ/eddie/xilinx_dsp_...
2019-10-06 Clifford WolfMerge pull request #1439 from YosysHQ/eddie/fix_ice40_w...
2019-10-05 Eddie HungMissing 'accept' at end of ice40_wrapcarry, spotted...
2019-10-04 Miodrag MilanovicSplit mux tests per type
2019-10-04 Miodrag MilanovicSplit latch check
2019-10-04 Miodrag Milanovicsplit rest od ff's
2019-10-04 Miodrag MilanovicSeparate check for ff's types
2019-10-04 Miodrag MilanovicCleaned tests
2019-10-04 Miodrag MilanovicRemove not needed tests
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/efinix' of https://github...
2019-10-04 Miodrag MilanovicCleanup and formating
2019-10-04 Miodrag Milanovicsplit latches into separate checks
2019-10-04 Miodrag Milanoviccheck muxes per type
2019-10-04 Miodrag Milanoviccheck ff's separately
2019-10-04 Miodrag MilanovicCleanup top modules and not used defines
2019-10-04 Miodrag Milanovicremove alu test
2019-10-04 Miodrag MilanovicMerge branch 'SergeyDegtyar/anlogic' of https://github...
2019-10-04 Miodrag MilanovicCheck latches type one by one
2019-10-04 Miodrag MilanovicRemoved top module where not needed
2019-10-04 Miodrag MilanovicTest muxes synth one by one
2019-10-04 Miodrag MilanovicCleaned verilog code from not used defines
2019-10-04 Miodrag MilanovicCheck for MULT18X18D, since that is working now
2019-10-04 Miodrag MilanovicCheck flops one by one
2019-10-04 Miodrag MilanovicRemoved alu and div_mod tests as agreed
2019-10-03 Eddie HungUse `sat -tempinduct` and comments for why equiv_opt...
2019-10-03 Eddie HungDisable equiv check for ice40 latches
2019-10-03 Eddie HungUse equiv_opt -async2sync for xilinx
2019-10-03 Clifford WolfMerge pull request #1419 from YosysHQ/eddie/lazy_derive
2019-10-03 Clifford WolfMerge pull request #1422 from YosysHQ/eddie/aigmap_select
2019-10-03 Clifford WolfMerge pull request #1429 from YosysHQ/clifford/checkmapped
2019-10-03 David Shahsv: Improve tests
2019-10-03 David Shahsv: Add test scripts for typedefs
2019-10-03 David Shahsv: Add support for memories of a typedef
2019-10-03 David Shahsv: Add support for memory typedefs
2019-10-03 David Shahsv: Fix typedefs in packages
2019-10-03 David Shahsv: Fix typedef parameters
2019-10-03 David Shahsv: Switch parser to glr, prep for typedef
2019-10-03 David ShahMerge pull request #1425 from YosysHQ/dave/ecp5_pdp16
2019-10-03 Eddie HungFix broken CI, check reset even for constants, trim...
2019-10-03 Eddie HungMerge pull request #1423 from YosysHQ/eddie/techmap_rep...
2019-10-03 Eddie HungFix test
2019-10-03 Eddie HungMerge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-03 Eddie HungUpdate test
2019-10-03 Eddie HungAdd test
2019-10-02 Eddie HungAdd test that is expecting to fail
2019-10-02 Eddie HungExtend test with renaming cells with prefix too
2019-10-01 Sergeyrun-test.sh Move $x at end of line.
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/efinix
2019-10-01 SergeyMerge branch 'master' into SergeyDegtyar/anlogic
2019-10-01 Sergeyrun-test.sh Move $x at end of line.
2019-10-01 Eddie Hungequiv_opt with -assert
2019-10-01 Eddie HungUpdate resource count for alu.ys
2019-10-01 Eddie HungAdd test
2019-09-30 Eddie HungAdd quick test
2019-09-30 Eddie HungMove $x to end as per 7f0eec8
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