Tim Ansell [Thu, 23 Aug 2018 03:17:40 +0000 (13:17 +1000)]
Merge pull request #91 from cr1901/ignore-fix
.gitignore: litex/build contains valid source, so exclude from .gitig…
Tim Ansell [Thu, 23 Aug 2018 03:15:49 +0000 (13:15 +1000)]
Merge pull request #92 from cr1901/l2-gate
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
William D. Jones [Thu, 23 Aug 2018 03:04:20 +0000 (23:04 -0400)]
.gitignore: litex/build contains valid source, so exclude from .gitignore.
William D. Jones [Thu, 23 Aug 2018 03:03:08 +0000 (23:03 -0400)]
software/bios: Gate flush_l2_cache() if L2 Cache isn't present.
Florent Kermarrec [Wed, 22 Aug 2018 21:15:32 +0000 (23:15 +0200)]
bios/sdram: improve/simplify read window selection
Compute a score for each window and select the best
Florent Kermarrec [Wed, 22 Aug 2018 13:20:28 +0000 (15:20 +0200)]
sim: run as root only when needed (ethernet module present)
Florent Kermarrec [Wed, 22 Aug 2018 12:28:37 +0000 (14:28 +0200)]
builder: change call to get_sdram_phy_c_header and also pass timing_settings
Florent Kermarrec [Wed, 22 Aug 2018 11:40:22 +0000 (13:40 +0200)]
soc_sdram: cosmetic
Florent Kermarrec [Wed, 22 Aug 2018 11:28:23 +0000 (13:28 +0200)]
soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >)
Florent Kermarrec [Tue, 21 Aug 2018 17:10:22 +0000 (19:10 +0200)]
soc_core: add cpu_endianness
Florent Kermarrec [Tue, 21 Aug 2018 16:15:57 +0000 (18:15 +0200)]
builder: get_sdram_phy_header renamed to get_sdram_phy_c_header
Florent Kermarrec [Tue, 21 Aug 2018 12:52:28 +0000 (14:52 +0200)]
soc_sdram: use new LiteDRAMWishbone2Native and port.data_width
Florent Kermarrec [Tue, 21 Aug 2018 09:04:15 +0000 (11:04 +0200)]
vexriscv: update
Florent Kermarrec [Mon, 20 Aug 2018 13:36:51 +0000 (15:36 +0200)]
soc/integration: move sdram_init to litedram
Florent Kermarrec [Sat, 18 Aug 2018 12:15:43 +0000 (14:15 +0200)]
Vexriscv: update csr-defs.h
Florent Kermarrec [Sat, 18 Aug 2018 12:14:00 +0000 (14:14 +0200)]
update Vexriscv
Florent Kermarrec [Sat, 18 Aug 2018 11:45:22 +0000 (13:45 +0200)]
bios/sdram: changes to ease manual read window selection
Florent Kermarrec [Fri, 17 Aug 2018 14:08:32 +0000 (16:08 +0200)]
litex_server: allow multiple clients to connect to the same server
Florent Kermarrec [Fri, 17 Aug 2018 06:32:32 +0000 (08:32 +0200)]
cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40)
Florent Kermarrec [Thu, 16 Aug 2018 17:47:43 +0000 (19:47 +0200)]
bios/boot: flush all caches before running from ram
Florent Kermarrec [Thu, 16 Aug 2018 13:13:27 +0000 (15:13 +0200)]
sim/verilator: catch ctrl-c on exit and revert default termios settings
Florent Kermarrec [Thu, 16 Aug 2018 08:03:43 +0000 (10:03 +0200)]
cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf
Florent Kermarrec [Tue, 14 Aug 2018 16:33:28 +0000 (18:33 +0200)]
bios/sdram: fix read_level_scan result
enjoy-digital [Sun, 12 Aug 2018 17:34:52 +0000 (19:34 +0200)]
Merge pull request #86 from pgielda/patch-1
Fix generating csr.csv file
Peter Gielda [Sun, 12 Aug 2018 11:37:39 +0000 (13:37 +0200)]
Fix generating csr.csv file
Fix generating csr.csv file when no absolute path is given.
Florent Kermarrec [Wed, 8 Aug 2018 06:53:54 +0000 (08:53 +0200)]
soc/intergration/cpu_interface: typo
Florent Kermarrec [Tue, 7 Aug 2018 07:02:09 +0000 (09:02 +0200)]
bios/main: use edata instead of erodata
Florent Kermarrec [Tue, 7 Aug 2018 06:59:34 +0000 (08:59 +0200)]
picorv32: add reset signal
Florent Kermarrec [Mon, 6 Aug 2018 10:23:50 +0000 (12:23 +0200)]
soc/software/bios: add reboot command
Florent Kermarrec [Mon, 6 Aug 2018 10:23:16 +0000 (12:23 +0200)]
soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers
Florent Kermarrec [Mon, 6 Aug 2018 10:21:18 +0000 (12:21 +0200)]
soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.
Florent Kermarrec [Mon, 6 Aug 2018 10:19:23 +0000 (12:19 +0200)]
soc/cores/cpu: add reset signal
enjoy-digital [Fri, 27 Jul 2018 09:59:28 +0000 (11:59 +0200)]
Merge pull request #81 from xobs/vexriscv-to-wishbone
Push Vexriscv debug directly on the Wishbone bus
Sean Cross [Fri, 27 Jul 2018 07:21:19 +0000 (15:21 +0800)]
tools: remove vexriscv_debug
This program is no longer needed.
The `openocd_vexriscv` package natively supports `etherbone`, and now
that the vexriscv debug module is available on Wishbone instead of as a
CSR, this module no longer works.
This change simplifies both tooling (because there is one fewer program
to run) and integration (because you don't need to modify your CSRs
anymore, just `register_mem()`.)
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Fri, 27 Jul 2018 07:02:31 +0000 (15:02 +0800)]
vexriscv: reset wishbone bus on CPU reset
If the CPU is resetting during a Wishbone transfer, assert the ERR line.
Because the resetOut line is likely multiple cycles long, this should
give Wishbone enough time to finish its transfer, which will cause d.stb
and i.stb to go to 0, which will return d_err and i_err to 0.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Thu, 19 Jul 2018 09:47:28 +0000 (17:47 +0800)]
vexriscv: put debug bus directly on wishbone bus
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone
core can access 32-bit values directly from the core. Additionally,
both reading and writing are supported without the need to do a SYNC
register as before.
Additionally, the address of the Wishbone bus won't move around anymore,
as it's fixed when doing `self.register_mem()`.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Fri, 20 Jul 2018 08:11:41 +0000 (10:11 +0200)]
add litex_setup script to clone and install Migen, LiteX and LiteX's cores
Florent Kermarrec [Fri, 20 Jul 2018 08:01:33 +0000 (10:01 +0200)]
build/generic_platform: use list for sources instead of set
Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
Florent Kermarrec [Thu, 19 Jul 2018 10:52:00 +0000 (12:52 +0200)]
bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup
Florent Kermarrec [Thu, 19 Jul 2018 10:51:16 +0000 (12:51 +0200)]
soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8
Florent Kermarrec [Thu, 19 Jul 2018 09:35:50 +0000 (11:35 +0200)]
setup.pu: fix exclude
Florent Kermarrec [Wed, 18 Jul 2018 10:48:44 +0000 (12:48 +0200)]
boards/plarforms/genesys2: replace user_dip_sw with user_sw
Florent Kermarrec [Wed, 18 Jul 2018 09:51:58 +0000 (11:51 +0200)]
boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter
Florent Kermarrec [Wed, 18 Jul 2018 07:37:38 +0000 (09:37 +0200)]
setup.py: exclude test, sim, doc directories
Florent Kermarrec [Wed, 18 Jul 2018 07:30:14 +0000 (09:30 +0200)]
software/bios/linker: revert data section since required by RISC-V compiler
enjoy-digital [Tue, 17 Jul 2018 15:31:48 +0000 (17:31 +0200)]
Merge pull request #80 from xobs/fix-vexriscv-csr-read
vexriscv_debug: use csr read()/write() accessors
Sean Cross [Tue, 17 Jul 2018 10:03:58 +0000 (18:03 +0800)]
vexriscv_debug: use csr read()/write() accessors
CSR access widths can be different from register widths. 8-bit
registers are common.
The runtime-generated `read()` and `write()` functions handle this
mapping correctly. When direct register accesses are handled, this
mapping is lost.
Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Mon, 16 Jul 2018 16:40:36 +0000 (18:40 +0200)]
soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient)
Florent Kermarrec [Mon, 16 Jul 2018 07:44:15 +0000 (09:44 +0200)]
targets/nexys_video: remove read leveling constants (now automatic)
Florent Kermarrec [Mon, 16 Jul 2018 07:43:09 +0000 (09:43 +0200)]
targets/nexys4ddr: s7ddrphy now supports ddr2, working
Florent Kermarrec [Mon, 16 Jul 2018 07:42:09 +0000 (09:42 +0200)]
bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window)
Florent Kermarrec [Tue, 10 Jul 2018 20:32:51 +0000 (22:32 +0200)]
soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx)
Florent Kermarrec [Tue, 10 Jul 2018 11:29:32 +0000 (13:29 +0200)]
soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another)
Florent Kermarrec [Fri, 6 Jul 2018 17:21:17 +0000 (19:21 +0200)]
bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup)
Florent Kermarrec [Fri, 6 Jul 2018 14:22:49 +0000 (16:22 +0200)]
bios/sdram: fix compilation with no write leveling
enjoy-digital [Fri, 6 Jul 2018 11:23:08 +0000 (13:23 +0200)]
Merge pull request #79 from xobs/fix-vexriscv-data-read
vexriscv: debug: fix reading DATA register
Sean Cross [Fri, 6 Jul 2018 10:22:32 +0000 (18:22 +0800)]
vexriscv: debug: fix reading DATA register
The REFRESH register accepts an 8-bit address and determines which
register to refresh. Since there are only two addresses currently in
use, this register can be either 0x00 or 0x04.
A refactor replaced the compare with one that checked for any 0 bits.
Since both 0x00 and 0x04 have 0 bits, this check always evaluated as
true, causing the logic to always refresh the CORE register.
Replace this check with an explicit check for 0x00.
Signed-off-by: Sean Cross <sean@xobs.io>
enjoy-digital [Fri, 6 Jul 2018 09:12:22 +0000 (11:12 +0200)]
Merge pull request #78 from xobs/vexriscv_debug_bridge
Add Vexriscv debug bridge
Sean Cross [Fri, 6 Jul 2018 08:09:38 +0000 (16:09 +0800)]
setup: add vexriscv_debug to list of entrypoints
Add the vexriscv_debug program to the list of scripts created when
installing this module. This program is a simple bridge that allows
openocd to talk to the vexriscv core so it can be debugged.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Fri, 6 Jul 2018 08:08:06 +0000 (16:08 +0800)]
tools: vexriscv_debug: add debug bridge
Add a bridge that uses litex_server to go from openocd to wishbone.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Thu, 5 Jul 2018 15:31:23 +0000 (17:31 +0200)]
cores/cpu/vexriscv: create variants: None and "debug", some cleanup
Florent Kermarrec [Thu, 5 Jul 2018 14:51:40 +0000 (16:51 +0200)]
core/cpu/vexriscv/core: improve indentation
enjoy-digital [Thu, 5 Jul 2018 14:46:24 +0000 (16:46 +0200)]
Merge pull request #77 from xobs/debug-vexriscv-enjoy
Enable support for vexriscv debugging
Florent Kermarrec [Thu, 5 Jul 2018 10:02:14 +0000 (12:02 +0200)]
platforms/arty_s7: keep up to date with Migen
Sean Cross [Thu, 5 Jul 2018 08:56:13 +0000 (16:56 +0800)]
soc_core: uart: add a reset line to the UART
Enable resetting the UART by adding a ResetInserter to the UART.
The UART must be reset when resetting the softcore.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Thu, 28 Jun 2018 01:18:42 +0000 (09:18 +0800)]
soc: integration: use the new cpu_debugging flag for vexriscv
Allow a new cpu_debugging flag to be passed to the constructor to
enable in-circuit live debugging of the softcore under gdb.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Thu, 28 Jun 2018 01:17:48 +0000 (09:17 +0800)]
soc: vexriscv: add cpu debug support
Add support for debugging the CPU, and gate it behind a new cpu_debug
parameter. With this enabled, a simple Wishbone interface is provided.
The debug version of the core adds two 32-bit registers to the CPU.
The register at address 0 indicates status, and is used to halt
and reset the core.
The debug register at address 4 is used to inject opcodes into the
core, and read back the result.
A patched version of OpenOCD can be used to attach to this bus via
the Litex Ethernet or UART bridges.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Thu, 28 Jun 2018 01:24:34 +0000 (09:24 +0800)]
vexriscv: verilog: pull debug-enabled verilog
The upstream vexriscv repo now generates both the current VexRiscv.v
softcore, as well as VexRiscv-Debug.v. This -Debug varient exposes
their specialized debug bus that allows for attaching a modified version
of openocd.
Sync the litex repo with the upstream version to take advantage of debug
support.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Thu, 5 Jul 2018 09:18:49 +0000 (11:18 +0200)]
platforms/arty: merge with Migen
Florent Kermarrec [Thu, 5 Jul 2018 08:43:26 +0000 (10:43 +0200)]
platforms/kc705: keep up to date with Migen
Florent Kermarrec [Thu, 5 Jul 2018 08:42:45 +0000 (10:42 +0200)]
platforms/de0nano: keep up to date with Migen
Florent Kermarrec [Thu, 5 Jul 2018 08:09:22 +0000 (10:09 +0200)]
README/boards: add precision on Migen's platforms
Florent Kermarrec [Mon, 2 Jul 2018 12:12:27 +0000 (14:12 +0200)]
bios/sdram: also check for last read of scan to choose optimal window
Florent Kermarrec [Mon, 2 Jul 2018 11:47:18 +0000 (13:47 +0200)]
bios/main: add cpu frequency to banner
Florent Kermarrec [Mon, 2 Jul 2018 11:46:48 +0000 (13:46 +0200)]
bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal.
Florent Kermarrec [Fri, 29 Jun 2018 12:24:44 +0000 (14:24 +0200)]
soc/cores/code_8b10b: update (from misoc)
Florent Kermarrec [Thu, 28 Jun 2018 16:43:48 +0000 (18:43 +0200)]
bios/sdram: use new phy, improve scan, allow disabling high skew
Florent Kermarrec [Thu, 28 Jun 2018 09:42:43 +0000 (11:42 +0200)]
software/bios: fix picorv32 boot_helper
Florent Kermarrec [Wed, 27 Jun 2018 13:31:54 +0000 (15:31 +0200)]
bios/sdram: add write/read leveling scans
Florent Kermarrec [Wed, 27 Jun 2018 09:27:05 +0000 (11:27 +0200)]
boards: add genesys2 (platform with clk/serial/dram/ethernet + target)
Florent Kermarrec [Tue, 19 Jun 2018 09:15:29 +0000 (11:15 +0200)]
soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases)
Florent Kermarrec [Mon, 18 Jun 2018 16:01:47 +0000 (18:01 +0200)]
soc/integration/cpu_interface: add shadow_base parameter
enjoy-digital [Mon, 18 Jun 2018 09:21:06 +0000 (11:21 +0200)]
Merge pull request #75 from xobs/bios-windows-build
soc: bios: fix windows build
Sean Cross [Mon, 18 Jun 2018 09:13:54 +0000 (17:13 +0800)]
soc: bios: fix windows build
The BIOS builds just fine on Windows, but afterwards tries to run
`chmod`. This command does not exist on Windows, and is unnecessary.
Add a conditional guard to prevent this command from running on Windows.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Tue, 12 Jun 2018 13:39:22 +0000 (15:39 +0200)]
targets: change a7/k7ddrphy imports to s7ddrphy
Florent Kermarrec [Tue, 12 Jun 2018 08:54:20 +0000 (10:54 +0200)]
soc/cores/cpu: add add_sources static method
When creating SoC with multiple sub-SoC already generated, we need an
easy way to add cpu sources.
enjoy-digital [Wed, 30 May 2018 17:35:04 +0000 (19:35 +0200)]
Merge pull request #72 from bunnie/fix_riscv_boothelper
fix the vexriscv boot helper
bunnie [Wed, 30 May 2018 17:24:22 +0000 (01:24 +0800)]
fix the vexriscv boot helper
enjoy-digital [Mon, 28 May 2018 22:13:59 +0000 (00:13 +0200)]
Merge pull request #71 from DeanoC/master
Fix for missing connectors for arty boards
Deano Calver [Thu, 24 May 2018 18:55:52 +0000 (21:55 +0300)]
Fix for missing connectors for arty boards
Florent Kermarrec [Thu, 24 May 2018 06:10:05 +0000 (08:10 +0200)]
litex_term: cleanup getkey and revert default settings on KeyboardInterrupt
Florent Kermarrec [Wed, 9 May 2018 14:28:28 +0000 (16:28 +0200)]
README: add list of supported CPUs/Cores and add link to tutorials
Florent Kermarrec [Wed, 9 May 2018 13:39:25 +0000 (15:39 +0200)]
soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at gnutoolchains.com/)
Dolu1990 [Wed, 9 May 2018 12:31:05 +0000 (14:31 +0200)]
add VexRiscv support (imported/adapted from misoc)
Florent Kermarrec [Wed, 9 May 2018 12:39:31 +0000 (14:39 +0200)]
add VexRiscv submodule
Florent Kermarrec [Wed, 9 May 2018 11:25:38 +0000 (13:25 +0200)]
allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)
Florent Kermarrec [Tue, 1 May 2018 10:02:54 +0000 (12:02 +0200)]
build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
Florent Kermarrec [Mon, 30 Apr 2018 22:46:26 +0000 (00:46 +0200)]
soc/intergration/soc_core: don't delete uart/timer0 interrupts
Florent Kermarrec [Mon, 30 Apr 2018 22:44:13 +0000 (00:44 +0200)]
xilinx/programmer: fix programmer
Florent Kermarrec [Thu, 12 Apr 2018 15:55:46 +0000 (17:55 +0200)]
build/xilinx/vivado: add vivado ip support