nv50,nvc0: disable the TGSI merge registers pass

shader-db results on GK106 (Thanks Karol):

total instructions in shared programs : 3931608 -> 3929463 (-0.05%)
total gprs used in shared programs    : 481255 -> 479014 (-0.47%)
total local used in shared programs   : 27481 -> 27381 (-0.36%)
total bytes used in shared programs   : 36031256 -> 36011120 (-0.06%)

                local        gpr       inst      bytes
    helped          14        1471        1309        1309
      hurt           1          88         384         384

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

radeonsi: disable the TGSI merge registers pass

47109 shaders in 29632 tests
Totals:
SGPRS: 1917364 -> 1916620 (-0.04 %)
VGPRS: 1165802 -> 1165202 (-0.05 %)
Spilled SGPRs: 1880 -> 1843 (-1.97 %)
Spilled VGPRs: 70 -> 65 (-7.14 %)
Private memory VGPRs: 1184 -> 1184 (0.00 %)
Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread
Code Size: 60211356 -> 60192268 (-0.03 %) bytes
LDS: 1077 -> 1077 (0.00 %) blocks
Max Waves: 428597 -> 428674 (0.02 %)
Wait states: 0 -> 0 (0.00 %)

Totals from affected shaders:
SGPRS: 238173 -> 237429 (-0.31 %)
VGPRS: 149556 -> 148956 (-0.40 %)
Spilled SGPRs: 1263 -> 1226 (-2.93 %)
Spilled VGPRs: 25 -> 20 (-20.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 20 -> 16 (-20.00 %) dwords per thread
Code Size: 10457904 -> 10438816 (-0.18 %) bytes
LDS: 50 -> 50 (0.00 %) blocks
Max Waves: 41283 -> 41360 (0.19 %)
Wait states: 0 -> 0 (0.00 %)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_tgsi: disable the merge registers pass conditionally

The main goal of this pass to merge temporary registers in order
to reduce the total number of registers and also to produce
optimal TGSI code.

In fact, compilers seem to be confused when temporary variables
are already merged, maybe because it's done too early in the
process.

Skipping the pass, reduce both the register pressure and the code
size, at least for Nouveau and RadeonSI because they have a real
backend compiler.

Found by luck while fixing an issue in the TGSI dead code elimination
pass which affects tex instructions with bindless samplers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: use unsynchronized transfers for shader binary uploads

Because the buffer is new, it can't be referenced by any CS.

This can save few CPU cycles by skipping the whole
PIPE_TRANSFER_UNSYNCHRONIZED if in amdgpu_bo_map().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: turn si_shader_key::mono into a non-union

A merged LS-HS shader needs both fix_fetch and inputs_to_copy
for compilation.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: adjust ESGS ring buffer size computation on VI

Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ON

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct register

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add a workaround for viewing a slice of 3D as a 2D image

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix 1D array shader images

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix most things wrong with shader images

There are 2 major hw changes:
- The address must always point to the address of level 0. GFX9 tiling
  modes don't allow binding to a non-0 level.
- 3D must always be bound as 3D, because 2D and 3D use entirely different
  tiling modes, and the texture target determines which set of modes is
  used.

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix texture buffer objects and image buffers with IDXEN==0

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

configure: print LDFLAGS alongside CFLAGS & co.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: tidy up left over APPLE_vertex_array_object semantics

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: inline bind_vertex_array() helper

The previous commit removed the only other user of this function.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: drop APPLE_vertex_array_object support

Shared context support for VAOs was dropped in 0b2750620b65.

From the ARB_vertex_array_object spec:

   "This extension differs from GL_APPLE_vertex_array_object
   in that client memory cannot be accessed through a
   non-zero vertex array object.  It also differs in that
   vertex array objects are explicitly not sharable between
   contexts."

Nobody should be using this extension over
ARB_vertex_array_object anymore so just drop it rather than
adding locking back just for VAOs created from these
functions.

For reference the Nvidia blob doesn't expose this extension.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: Enable userspace fence checking.

v2: - Added some error handling.
    - memset the buffer to 0.

v3: Added assert for buffer size.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

i965: Remove unused variable 'options'

Should have been removed in commit ad55b1a7701a

glsl: Initialize current_var

CID: 1324644 (Uninitialized pointer field)

radv/ac: setup mrt exports then export them in one go. (v2)

Noticed while looking at Sascha Willems deferred shaders.

This is a bit of an llvm workaround, llvm was producing this:
        v_cvt_pkrtz_f16_f32_e64 v4, v7, v8                       ; D2960004 00021107
        v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0                      ; D2960006 0001E509
        s_waitcnt vmcnt(0)                                       ; BF8C0F70
        exp mrt0 v4, v4, v6, v6 compr                            ; C400040F 00000604
        s_waitcnt expcnt(0)                                      ; BF8C0F0F
        v_cvt_pkrtz_f16_f32_e64 v4, v12, v5                      ; D2960004 00020B0C
        v_cvt_pkrtz_f16_f32_e64 v5, v14, 1.0                     ; D2960005 0001E50E
        exp mrt1 v4, v4, v5, v5 compr                            ; C400041F 00000504
        s_waitcnt expcnt(0)                                      ; BF8C0F0F
        v_cvt_pkrtz_f16_f32_e64 v0, v0, v1                       ; D2960000 00020300
        v_cvt_pkrtz_f16_f32_e64 v1, v2, v3                       ; D2960001 00020702
        exp mrt2 v0, v0, v1, v1 done compr vm                    ; C4001C2F 00000100

After this change:
        v_cvt_pkrtz_f16_f32_e64 v4, v7, v8                       ; D2960004 00021107
        s_waitcnt vmcnt(0)                                       ; BF8C0F70
        v_cvt_pkrtz_f16_f32_e64 v0, v0, v1                       ; D2960000 00020300
        v_cvt_pkrtz_f16_f32_e64 v6, v9, 1.0                      ; D2960006 0001E509
        v_cvt_pkrtz_f16_f32_e64 v5, v12, v5                      ; D2960005 00020B0C
        v_cvt_pkrtz_f16_f32_e64 v7, v14, 1.0                     ; D2960007 0001E50E
        exp mrt0 v4, v4, v6, v6 compr                            ; C400040F 00000604
        v_cvt_pkrtz_f16_f32_e64 v1, v2, v3                       ; D2960001 00020702
        exp mrt1 v5, v5, v7, v7 compr                            ; C400041F 00000705
        exp mrt2 v0, v0, v1, v1 done compr vm                    ; C4001C2F 00000100

No waitcnt for exports are emitted.

v2: fixup index->mrt mapping (Bas).

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/ac: overhaul vs output/ps input routing

In order to cleanly eliminate exports rewrite the
code first to mirror how radeonsi works for now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/ac: move point coord after layer/viewport.

These need to be ordered as per shader enum ordering, I'll
rewrite this soon, but this is a bug fix.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium: remove u_caps.c/h interface

No longer used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ddebug: implement get_query_result_resource

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

trace: don't trace resource_destroy

due to the lack of pipe_resource wrapping, we can get this call from inside
of driver calls, which would try to lock an already-locked mutex.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/util: add debugging helpers printing pipeline statistics

typically useful for hw bring-up

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Android: fix r300g only build

If r300g is the only radeon driver built, the Android build fails to
build:

ninja: error:
'out/target/product/linaro_x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_radeon_intermediates/export_includes',
needed by
'out/target/product/linaro_x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/import_includes',
missing and no known rule to make it

This is because the path to build libmesa_pipe_radeon was only getting
added for r600g and radeonsi, but the library dependency was added for
all radeon drivers. As libmesa_pipe_radeon is not needed for r300g, drop
the library dependency.

Cc: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Emil Velikov <emil.velikov@collabora.com>

mesa: use locked version of HashWalk for xfb objects

From Chapter 5 'Shared Objects and Multiple Contexts' of
the OpenGL 4.5 spec:

   "Objects which contain references to other objects include
   framebuffer, program pipeline, query, transform feedback,
   and vertex array objects.   Such objects are called container
   objects and are not shared"

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: create locked version of HashWalk

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

genxml: Fix gen_pack_header.py crash when field type is invalid.

Just return earlier in that case. Also set prefix to an empty string, so
we don't get to use it undefined.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Make BLEND_STATE command support variable length array.

We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers
dwords (on gen8+), but the BLEND_STATE struct length is always 17. By
marking it size 1, which is actually the size of the struct minus the
BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of
entries.

For gen6 and gen7 we set length to 0, since it only contains
BLEND_STATE_ENTRY's, and no other data.

With this change, we also change the code for blorp and anv to emit only
the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on
gen6-7 and 17 dwords on gen8+.

v2:
   - Use designated initializers on blorp and remove 0 from
   initialization (Jason)
   - Default entries to disabled on Vulkan (Jason)
   - Rebase code.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Fix python crash when no dwords are found.

If the 'dwords' dict is empty, max(dwords.keys()) throws an exception.
This case could happen when we have an instruction that is only an array
of other structs, with variable length.

v2:
   - Add another clause for empty dwords and make it work with python 3
   (Dylan)
   - Set the length to 0 if dwords is empty, and do not declare dw

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Remove unused parameter.

'start' parameter from Group.emit_pack_function() is useless.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/aubinator: Correctly read variable length structs.

Before this commit, when a group with count="0" is found, only one field
is added to the struct representing the instruction. This causes only
one entry to be printed by aubinator, for variable length groups.

With this commit we "detect" that there's a variable length group
(count="0") and store the offset of the last entry added to the struct
when reading the xml. When finally reading the aubdump file, we check
the size of the group and whether we have variable number of elements,
and in that case, reuse the last field to add the remaining elements.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

isl/format: Update the R16G16B16X16_FLOAT entry

The section of the PRM mentioned in the code comment above this table
says that this format supports the render target write message. Internal
documentation says that this format also supports alpha blending. As a
side effect, this allows CCS_D buffers to be created for images with
this format.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>

anv/pass: Delete anv_pass::subpass_attachments

This field has no users.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>

intel/fs: Take into account amount of data read in spilling cost heuristic.

Until now the spilling cost calculation was neglecting the amount of
data read from the register during the spilling cost calculation.
This caused it to make suboptimal decisions in some cases leading to
higher memory bandwidth usage than necessary.

Improves Unigine Heaven performance by ~4% on BDW, reversing an
unintended FPS regression from my previous commit
147e71242ce539ff28e282f009c332818c35f5ac with n=12 and statistical
significance 5%.  In addition SynMark2 OglCSDof performance is
improved by an additional ~5% on SKL, and a Kerbal Space Program
apitrace around the Moho planet I can provide on request improves by
~20%.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/fs: Use regs_written() in spilling cost heuristic for improved accuracy.

This is what we use later on to compute the number of registers that
will actually get spilled to memory, so it's more likely to match
reality than the current open-coded approximation.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.

Curro pointed out that I should not just check for MACH, but use
the reads_accumulator_implicitly() helper, which would also prevent
the same bug with MAC and SADA2 (if we ever decide to use them).

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

android: radv/ac: Fix nir.h include

Fixes following building errors due to missing include paths:

external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error: 'nir/nir.h' file not found
         ^

external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found
         ^

Fixes: 224cf29 "radv/ac: add initial pre-pass for shader info gathering"
Acked-by: Dave Airlie <Airlied@redhat.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Fix typos.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: <mesa-stable@lists.freedesktop.org>

radv/ac: copy llvm machine feature flags from radeonsi.

This just updates this to use the same flags as radeonsi
for consistency.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

i965: remove now unused GLSL IR optimisations

These are no longer used since the previous commit.

Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: remove GLSL IR optimisation loop

IVB is running into some spilling issues in piglit with the
loop removed. However those tests are not really reflective
of a real world use case, also fp64 is brand new to IVB
so we leave the spilling issues to be resolved at a later
time.

Run time for shader-db on my machine goes from ~795 seconds to
~665 seconds.

shader-db results BDW:

total instructions in shared programs: 12969459 -> 12968891 (-0.00%)
instructions in affected programs: 1463154 -> 1462586 (-0.04%)
helped: 3622
HURT: 3326

total cycles in shared programs: 246453572 -> 246504318 (0.02%)
cycles in affected programs: 208842622 -> 208893368 (0.02%)
helped: 24029
HURT: 35407

total loops in shared programs: 2931 -> 2931 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 14560 -> 14498 (-0.43%)
spills in affected programs: 2270 -> 2208 (-2.73%)
helped: 17
HURT: 2

total fills in shared programs: 19671 -> 19632 (-0.20%)
fills in affected programs: 2060 -> 2021 (-1.89%)
helped: 17
HURT: 2

LOST:   17
GAINED: 40

Most of the hurt shaders are 1-2 instructions, with what looks like a max of 7.

I've looked at the worst cycles regressions and as far as I can tell its just
a scheduling difference.

Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: use ARB_enhahnced_layouts for packing where possible

If packing doesn't cross locations we can easily make use of
ARB_enhanced_layouts to do packing rather than using the GLSL IR
lowering pass lower_packed_varyings().

Shader-db Broadwell results:

total instructions in shared programs: 12977822 -> 12977819 (-0.00%)
instructions in affected programs: 1871 -> 1868 (-0.16%)
helped: 4
HURT: 3

total cycles in shared programs: 246567288 -> 246567668 (0.00%)
cycles in affected programs: 1370386 -> 1370766 (0.03%)
helped: 592
HURT: 733

Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: disable varying packing for varying used by interpolateAt*

Currently the NIR backends depend on GLSL IR copy propagation to
fix up the interpolateAt* function params after varying packing
changes the shader input to a global. It's possible copy propagation
might not always do what we need it too, and we also shouldn't
depend on optimisations to do this type of thing for us.

I'm not sure if the same is true for TGSI, but the following
commit should re-enable packing for most cases in a safer way,
so we just disable it everywhere.

No change in shader-db for i965 (BDW)

Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl_to_nir: skip ir_var_shader_shared variables

These should be lowered away in GLSL IR but if we don't get dead
code to clean them up it causes issues in glsl_to_nir.

We wan't to drop as many GLSL IR opts in future as we can so this
makes glsl_to_nir just ignore the vars if it sees them.

In future we will want to just use the nir lowering pass that
Vulkan currently uses.

Acked-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir/i965: add before ffma algebraic opts

This shuffles constants down in the reverse of what the previous
patch does and applies some simpilifications that may be made
possible from doing so.

Shader-db results BDW:

total instructions in shared programs: 12980814 -> 12977822 (-0.02%)
instructions in affected programs: 281889 -> 278897 (-1.06%)
helped: 1231
HURT: 128

total cycles in shared programs: 246562852 -> 246567288 (0.00%)
cycles in affected programs: 11271524 -> 11275960 (0.04%)
helped: 1630
HURT: 1378

V2: mark float opts as inexact

Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: shuffle constants to the top

V2: mark float opts as inexact

If one of the inputs to an mul/add is the result of another
mul/add there is a chance that we can reuse the result of that
mul/add in other calls if we do the multiplication in the right
order.

Also by attempting to move all constants to the top we increase
the chance of constant folding.

For example it is a fairly common pattern for shaders to do something
similar to this:

  const float a = 0.5;
  in vec4 b;
  in float c;

  ...

  b.x = b.x * c;
  b.y = b.y * c;

  ...

  b.x = b.x * a + a;
  b.y = b.y * a + a;

So by simply detecting that constant a is part of the multiplication
in ffma and switching it with previous fmul that updates b we end up
with:

  ...

  c = a * c;

  ...

  b.x = b.x * c + a;
  b.y = b.y * c + a;

Shader-db results BDW:

total instructions in shared programs: 13011050 -> 12967888 (-0.33%)
instructions in affected programs: 4118366 -> 4075204 (-1.05%)
helped: 17739
HURT: 1343

total cycles in shared programs: 246717952 -> 246410716 (-0.12%)
cycles in affected programs: 166870802 -> 166563566 (-0.18%)
helped: 18493
HURT: 7965

total spills in shared programs: 14937 -> 14560 (-2.52%)
spills in affected programs: 9331 -> 8954 (-4.04%)
helped: 284
HURT: 33

total fills in shared programs: 20211 -> 19671 (-2.67%)
fills in affected programs: 12586 -> 12046 (-4.29%)
helped: 286
HURT: 33

LOST:   39
GAINED: 33

Some of the hurt will go away when we shuffle things back down to the
bottom in the following patch. It's also noteworthy that almost all of the
spill changes are in Deus Ex both hurt and helped.

Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: add flt comparision simplification

Didn't turn out as useful as I'd hoped, but it will help alot more on
i965 by reducing regressions when we drop brw_do_channel_expressions()
and brw_do_vector_splitting().

I'm not sure how much sense 'is_not_used_by_conditional' makes on
platforms other than i965 but since this is a new opt it at least
won't do any harm.

shader-db BDW:

total instructions in shared programs: 13029581 -> 13029415 (-0.00%)
instructions in affected programs: 15268 -> 15102 (-1.09%)
helped: 86
HURT: 0

total cycles in shared programs: 247038346 -> 247036198 (-0.00%)
cycles in affected programs: 692634 -> 690486 (-0.31%)
helped: 183
HURT: 27

Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: Enable lowering fdiv in nir.

Results in faster code than the lowering by LLVM.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

freedreno/a5xx: hack for r8g8b8a8_snorm

Blob won't render to this format, and sampling from it it uses the same
fmt value for r8g8b8_snorm and r8g8b8a8_snorm.  But this is what is what
blocks us from jumping from gl30/gles20 to gl31/gles30.  So a hack it
is!

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: rgtc formats

Signed-off-by: Rob Clark <robdclark@gmail.com>

mesa: replace _mesa_index_buffer::type with index_size

This avoids repeated translations of the enum.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: Use the correct pipeline for dispatches.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes: ec15e0d30 "radv: optimise compute shader grid size emission."
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

etnaviv: Supertiled texture support on gc3000

Support supertiled textures on hardware that has the appropriate
feature flag SUPERTILED_TEXTURE.

Most of the scaffolding was already in place in etna_layout_multiple:

   case ETNA_LAYOUT_SUPER_TILED:
      *paddingX = 64;
      *paddingY = 64;
      *halign = TEXTURE_HALIGN_SUPER_TILED;

So this is just a matter of allowing it.

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

etnaviv: etnaviv_fence: Simplify the return code logic

The return code can be simplified by using the logical not operator.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

freedreno/a5xx: occlusion query

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: drop ring arg from _set_stage()

It is always the draw ring.  Except for a5xx queries like time-elapsed,
where we will eventually want to emit cmds into both binning and draw
rings.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: add support for hw accumulating queries

Some queries on a4xx and all queries on a5xx can do result accumulation
on CP so we don't need to track per-tile samples.  We do still need to
handle pausing/resuming while switching batches (in case the query is
active over multiple draws which are executed out of order).

So introduce new accumulated-query helpers for these sorts of queries,
since it doesn't really fit in cleanly with the original query infra-
structure.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: a bit of query refactor

Move a bit more of the logic shared by all query types (active tracking,
etc) into common code.  This avoids introducing a 3rd copy of that logic
for a5xx.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: make hw-query a helper

For a5xx (and actually some queries on a4xx) we can accumulate results
in the cmdstream, so we don't need this elaborate mechanism of tracking
per-tile query results.  So make it into vfuncs so generation specific
backend can use it when it makes sense.

Signed-off-by: Rob Clark <robdclark@gmail.com>

i965/vec4: Avoid reswizzling MACH instructions in opt_register_coalesce().

opt_register_coalesce() was optimizing sequences such as:

   mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D
   mach(8) vgrf5.xy:D, attr18.xyyy:D, attr19.xyyy:D
   mov(8) m4.zw:F, vgrf5.xxxy:F

into:

   mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D
   mach(8) m4.zw:D, attr18.xxxy:D, attr19.xxxy:D

This doesn't work - if we're going to reswizzle MACH, we'd need to
reswizzle the MUL as well.  Here, the MUL fills the accumulator's .zw
components with attr18.yy * attr19.yy.  But the MACH instruction expects
.z to contain attr18.x * attr19.x.  Bogus results ensue.

No change in shader-db on Haswell.  Prevents regressions in Timothy's
patches to use enhanced layouts for varying packing (which rearrange
code just enough to trigger this pre-existing bug, but were fine
themselves).

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

mesa: validate sampler type across the whole program

Currently we were only making sure types were the same within a
single stage. This looks to have regressed with 953a0af8e3f73.

Fixes: 953a0af8e3f73 ("mesa: validate sampler uniforms during gluniform calls")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
https://bugs.freedesktop.org/show_bug.cgi?id=97524

mesa: don't lock hashtables that are not shared across contexts

From Chapter 5 'Shared Objects and Multiple Contexts' of
the OpenGL 4.5 spec:

   "Objects which contain references to other objects include
   framebuffer, program pipeline, query, transform feedback,
   and vertex array objects.   Such objects are called container
   objects and are not shared"

For we leave locking in place for framebuffer objects because
the EXT fbo extension allowed sharing.

We could maybe just replace the hash with an ordinary hash table
but for now this should remove most of the unnecessary locking.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: Remove deleteFlag pattern from container objects.

This pattern was only useful when we used mutex locks, which the previous
commit removed.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: Remove unnecessary locking from container objects.

From Chapter 5 'Shared Objects and Multiple Contexts' of
the OpenGL 4.5 spec:

   "Objects which contain references to other objects include
   framebuffer, program pipeline, query, transform feedback,
   and vertex array objects.   Such objects are called container
   objects and are not shared"

For we leave locking in place for framebuffer objects because
the EXT fbo extension allowed sharing.

V2: (Timothy Arceri)
 - rebased and dropped changes to framebuffer objects

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa: remove fallback RefCount == 0 pattern

We should never get here if this is 0 unless there is a
bug. Replace the check with an assert.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

egl: add gitignore

Since commit ce562f9e3fa, two new files are generated.
We don't want to track them.

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

glsl: make use of glsl_type::is_float()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: make use of glsl_type::is_double()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: make use of glsl_type::is_integer_64()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: simplify glsl_type::is_integer_32_64()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: add glsl_type::is_integer_64()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: make use of glsl_type::is_boolean()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: make use of glsl_type::is_record()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: make use of glsl_type::is_interface()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: make use of glsl_type::is_array()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: make use glsl_type::is_atomic_uint()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

glsl: add glsl_type::is_atomic_uint() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

mesa/glthread: correctly compare thread handles

As mentioned in the manual - comparing pthread_t handles via the C
comparison operator is incorrect and pthread_equal() should be used
instead.

Cc: Timothy Arceri <tarceri@itsqueeze.com>
Fixes: d8d81fbc316 ("mesa: Add infrastructure for a worker thread to process GL commands.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

st/clover: add space between < and ::

As pointed out by compiler

./llvm/codegen.hpp:52:22: error: ‘<::’ cannot begin a template-argument list [-fpermissive]
./llvm/codegen.hpp:52:22: note: ‘<:’ is an alternate spelling for ‘[’. Insert whitespace between ‘<’ and ‘::’

Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>

glsl: get rid of values_for_type()

This function is actually a wrapper for component_slots()
and it always returns 1 (or N) for samplers. Since
component_slots() now return 1 for samplers, it can go.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glsl: make component_slots() returns 1 for sampler types

It looks inconsistent to return 1 for image types and 0 for
sampler types. Especially because component_slots() is mostly
used by values_for_type() which always returns 1 for samplers.

For bindless, this value will be bumped to 2 because the
ARB_bindless_texture states that bindless samplers/images
should consume two components.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

docs/features: mark KHR_no_error as started

The OpenGL extension KHR_no_error is exposed since commit
d42d150ad26e29d9e894ba9f9e28f8134e2e5393 by Timothy Arceri. Therefore it
should be marked as "started" in the features.txt

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Revert "android: fix segfault within swap_buffers"

This reverts commit 4d4558411db166d2d66f8cec9cb581149dbe1597.

This was a wrong call, while it fixed issue with 3DMark it
actually introduced regression elsewhere.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>

nvc0: Add support for setting viewport index/layer from VS/TES

This enables support on GM200+ for:
 - GL_AMD_vertex_shader_layer
 - GL_AMD_vertex_shader_layer_viewport_index
 - GL_ARB_shader_viewport_layer_array

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
[lyude: add relnotes/TES cap]
Signed-off-by: Lyude <lyude@redhat.com>
[imirkin: move relnotes to right place, add features.txt]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: Only store viewport in scratch register for GP

EMIT only applies to geometry shaders. For everything else, we want to
export the viewport normally.

Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Boyan Ding <boyan.j.ding@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

radv: Prefetch compute shader too.

For consistency, doesn't really impact performance.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

anv/query: Use genxml for MI_MATH

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed by: Iago Toral Quiroga <itoral@igalia.com>

genxml: Add better support for MI_MATH

This breaks the guts of MI_MATH (the instruction part) out into its own
structure with proper named values.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed by: Iago Toral Quiroga <itoral@igalia.com>

genxml/pack: Allow hex values in the XML

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

radv/ac: use tex_lz if we can.

Looking at some Talos shaders vs radeonsi, I noticed they use
tex_lz in a few places, so we should be able to as well.

Reviewed-by: Bas Nieuwenhuizen <basni@google.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

st/mesa: use one big translation table in st_pipe_vertex_format

for lower overhead.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: check in advance in st_draw_vbo whether the bitmap cache is empty

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: put the bitmap_cache structure inside st_context

This is nicer on caches, and the next commit will need to access
the structure from a different place.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: inline and optimize st_invalidate_readpix_cache

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

st/mesa: invalidate the readpix cache in st_indirect_draw_vbo

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>