yosys.git
4 years agotests: Parallelize
Xiretza [Wed, 16 Sep 2020 17:58:16 +0000 (19:58 +0200)]
tests: Parallelize

4 years agotests: Centralize test collection and Makefile generation
Xiretza [Wed, 16 Sep 2020 15:59:37 +0000 (17:59 +0200)]
tests: Centralize test collection and Makefile generation

4 years agoBump version
Yosys Bot [Sat, 19 Sep 2020 00:10:08 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2381 from YosysHQ/unsupported
clairexen [Fri, 18 Sep 2020 15:43:30 +0000 (17:43 +0200)]
Merge pull request #2381 from YosysHQ/unsupported

Better error for unsupported SVA sequence

4 years agoBetter error for unsupported SVA sequence
Miodrag Milanovic [Fri, 18 Sep 2020 15:08:00 +0000 (17:08 +0200)]
Better error for unsupported SVA sequence

4 years agoBump version
Yosys Bot [Fri, 18 Sep 2020 00:10:08 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2329 from antmicro/arrays-fix-multirange-size
clairexen [Thu, 17 Sep 2020 16:27:05 +0000 (18:27 +0200)]
Merge pull request #2329 from antmicro/arrays-fix-multirange-size

Rewrite multirange arrays sizes [n] as [n-1:0]

4 years agoMerge pull request #2330 from antmicro/arrays-fix-multirange-access
clairexen [Thu, 17 Sep 2020 16:21:53 +0000 (18:21 +0200)]
Merge pull request #2330 from antmicro/arrays-fix-multirange-access

Fix unsupported subarray access detection

4 years agoBump version
Yosys Bot [Fri, 11 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2369 from Xiretza/gitignores
Miodrag Milanović [Thu, 10 Sep 2020 11:37:49 +0000 (13:37 +0200)]
Merge pull request #2369 from Xiretza/gitignores

Add missing gitignores for test artifacts

4 years agoBump version
Yosys Bot [Fri, 4 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2371 from whitequark/cxxrtl-debug-info
whitequark [Thu, 3 Sep 2020 09:45:40 +0000 (09:45 +0000)]
Merge pull request #2371 from whitequark/cxxrtl-debug-info

cxxrtl: expose port direction and driver kind in debug information

4 years agoBump version
Yosys Bot [Thu, 3 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

4 years agocxxrtl: expose driver kind in debug information.
whitequark [Wed, 2 Sep 2020 17:16:10 +0000 (17:16 +0000)]
cxxrtl: expose driver kind in debug information.

This can be useful to determine whether the wire should be a part of
a design checkpoint, whether it can be used to override design state,
and whether driving it may cause a conflict.

4 years agocxxrtl: improve handling of FFs with async inputs (other than CLK).
whitequark [Wed, 2 Sep 2020 16:03:35 +0000 (16:03 +0000)]
cxxrtl: improve handling of FFs with async inputs (other than CLK).

Before this commit, the meaning of "sync def" included some flip-flop
cells but not others. There was no actual reason for this; it was
just poorly defined.

After this commit, a "sync def" means that a wire holds design state
because it is connected directly to a flip-flop output, and may never
be unbuffered. This is not affected by presence of async inputs.

4 years agocxxrtl: expose port direction in debug information.
whitequark [Wed, 2 Sep 2020 15:18:44 +0000 (15:18 +0000)]
cxxrtl: expose port direction in debug information.

This can be useful to distinguish e.g. a combinatorially driven wire
with type `CXXRTL_VALUE` from a module input with the same type, as
well as general introspection.

4 years agocxxrtl: fix typo in comment. NFC.
whitequark [Wed, 2 Sep 2020 15:23:40 +0000 (15:23 +0000)]
cxxrtl: fix typo in comment. NFC.

4 years agocxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC.
whitequark [Wed, 2 Sep 2020 15:11:55 +0000 (15:11 +0000)]
cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC.

Nodes driven by a constant value have type CXXRTL_VALUE and their
`next` pointer set to NULL. (This is already documented.)

4 years agoUse latest verific
Miodrag Milanovic [Wed, 2 Sep 2020 08:22:25 +0000 (10:22 +0200)]
Use latest verific

4 years agoBump version
Yosys Bot [Wed, 2 Sep 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2352 from zachjs/const-func-localparam
clairexen [Tue, 1 Sep 2020 15:31:48 +0000 (17:31 +0200)]
Merge pull request #2352 from zachjs/const-func-localparam

Allow localparams in constant functions

4 years agoMerge pull request #2366 from zachjs/library-format
clairexen [Tue, 1 Sep 2020 15:30:36 +0000 (17:30 +0200)]
Merge pull request #2366 from zachjs/library-format

Simple support for %l format specifier

4 years agoMerge pull request #2353 from zachjs/top-scope
clairexen [Tue, 1 Sep 2020 15:30:09 +0000 (17:30 +0200)]
Merge pull request #2353 from zachjs/top-scope

Module name scope support

4 years agoMerge pull request #2365 from zachjs/const-arg-loop-split-type
clairexen [Tue, 1 Sep 2020 15:28:35 +0000 (17:28 +0200)]
Merge pull request #2365 from zachjs/const-arg-loop-split-type

Fix constant args used with function ports split across declarations

4 years agoBump version
Yosys Bot [Tue, 1 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

4 years agoAdd missing gitignores for test artifacts
Xiretza [Mon, 31 Aug 2020 17:42:10 +0000 (19:42 +0200)]
Add missing gitignores for test artifacts

4 years agoReorder to prevent crash
Miodrag Milanovic [Mon, 31 Aug 2020 10:22:26 +0000 (12:22 +0200)]
Reorder to prevent crash

4 years agoMerge pull request #2368 from YosysHQ/verific_portrange
clairexen [Mon, 31 Aug 2020 09:58:29 +0000 (11:58 +0200)]
Merge pull request #2368 from YosysHQ/verific_portrange

Fix import of VHDL enums

4 years agoast recognize lower case x and z and verific gives upper case
Miodrag Milanovic [Sun, 30 Aug 2020 11:33:03 +0000 (13:33 +0200)]
ast recognize lower case x and z and verific gives upper case

4 years agoDo not check for 1 and 0 only
Miodrag Milanovic [Sun, 30 Aug 2020 11:15:06 +0000 (13:15 +0200)]
Do not check for 1 and 0 only

4 years agoFix import of VHDL enums
Miodrag Milanovic [Sun, 30 Aug 2020 10:25:23 +0000 (12:25 +0200)]
Fix import of VHDL enums

4 years agoBump version
Yosys Bot [Sun, 30 Aug 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

4 years agowrite_smt2: fix SMT-LIB tutorial URL
whitequark [Sat, 29 Aug 2020 20:02:35 +0000 (20:02 +0000)]
write_smt2: fix SMT-LIB tutorial URL

4 years agoSimple support for %l format specifier
Zachary Snow [Sat, 29 Aug 2020 17:33:31 +0000 (13:33 -0400)]
Simple support for %l format specifier

Yosys doesn't support libraries, so this provides the same behavior as
%m, as some other tools have opted to do.

4 years agoFix constant args used with function ports split across declarations
Zachary Snow [Sat, 29 Aug 2020 17:31:02 +0000 (13:31 -0400)]
Fix constant args used with function ports split across declarations

4 years agoBump version
Yosys Bot [Sat, 29 Aug 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

4 years agointel_alm: better map wide but shallow multiplies
Dan Ravensloft [Wed, 26 Aug 2020 20:47:06 +0000 (21:47 +0100)]
intel_alm: better map wide but shallow multiplies

4 years agoBump version
Yosys Bot [Fri, 28 Aug 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2364 from whitequark/manual-typo
Miodrag Milanović [Thu, 27 Aug 2020 16:35:53 +0000 (18:35 +0200)]
Merge pull request #2364 from whitequark/manual-typo

manual: fix typo

4 years agomanual: fix typo.
whitequark [Thu, 27 Aug 2020 16:34:48 +0000 (16:34 +0000)]
manual: fix typo.

4 years agoMerge pull request #2357 from whitequark/cxxflags-MP
whitequark [Thu, 27 Aug 2020 11:40:57 +0000 (11:40 +0000)]
Merge pull request #2357 from whitequark/cxxflags-MP

Add -MP to CXXFLAGS

4 years agoMerge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap
whitequark [Thu, 27 Aug 2020 11:28:31 +0000 (11:28 +0000)]
Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmap

flatten, techmap: don't canonicalize tpl driven bits via sigmap

4 years agoMerge pull request #2358 from whitequark/rename-ilang-to-rtlil
whitequark [Thu, 27 Aug 2020 11:24:06 +0000 (11:24 +0000)]
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil

Replace "ILANG" with "RTLIL" everywhere

4 years agodfflegalize: Fix decision tree for adffe.
Marcelina Kościelnicka [Thu, 27 Aug 2020 09:58:56 +0000 (11:58 +0200)]
dfflegalize: Fix decision tree for adffe.

When an adffe is being legalized, and is not natively supported,
prioritize unmapping to adff over converting to dffsre if dffsre is not
natively supported itself.

Fixes #2361.

4 years agoBump version
Yosys Bot [Thu, 27 Aug 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

4 years agointel_alm: Add multiply signedness to cells
Dan Ravensloft [Wed, 26 Aug 2020 17:44:48 +0000 (18:44 +0100)]
intel_alm: Add multiply signedness to cells

Quartus assumes unsigned multiplication by default, breaking signed
multiplies, so add an input signedness parameter to the MISTRAL_MUL*
cells to propagate to Quartus' <family>_mac cells.

4 years agoReplace "ILANG" with "RTLIL" everywhere.
whitequark [Wed, 26 Aug 2020 17:29:32 +0000 (17:29 +0000)]
Replace "ILANG" with "RTLIL" everywhere.

The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.

4 years agoAdd -MP to CXXFLAGS.
whitequark [Wed, 26 Aug 2020 16:53:47 +0000 (16:53 +0000)]
Add -MP to CXXFLAGS.

This avoids an issue where deleting or moving headers breaks the next
incremental build until the outdated *.d files are deleted.

4 years agoflatten, techmap: don't canonicalize tpl driven bits via sigmap.
whitequark [Wed, 26 Aug 2020 16:20:32 +0000 (16:20 +0000)]
flatten, techmap: don't canonicalize tpl driven bits via sigmap.

For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.

4 years agoMerge pull request #2355 from YosysHQ/verific_improvements
Miodrag Milanović [Wed, 26 Aug 2020 11:26:34 +0000 (13:26 +0200)]
Merge pull request #2355 from YosysHQ/verific_improvements

Add formal apps and template generators

4 years agoAdd formal apps and template generators
Miodrag Milanovic [Wed, 26 Aug 2020 08:39:57 +0000 (10:39 +0200)]
Add formal apps and template generators

4 years agoMerge pull request #2351 from pbsds/proc_nomux
whitequark [Wed, 26 Aug 2020 08:23:54 +0000 (08:23 +0000)]
Merge pull request #2351 from pbsds/proc_nomux

Add -nomux switch to proc

4 years agoBump version
Yosys Bot [Sun, 23 Aug 2020 00:10:08 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2349 from nmoroze/smt2-bugfix
clairexen [Sat, 22 Aug 2020 10:28:39 +0000 (12:28 +0200)]
Merge pull request #2349 from nmoroze/smt2-bugfix

Ensure smt2 comments are associated with accessors

4 years agoModule name scope support
Zachary Snow [Fri, 21 Aug 2020 00:15:08 +0000 (20:15 -0400)]
Module name scope support

4 years agoAllow localparams in constant functions
Zachary Snow [Fri, 21 Aug 2020 00:09:54 +0000 (20:09 -0400)]
Allow localparams in constant functions

4 years agoBump version
Yosys Bot [Fri, 21 Aug 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

4 years agosynth_intel: Remove incomplete Arria 10 GX support.
Marcelina Kościelnicka [Thu, 20 Aug 2020 19:59:37 +0000 (21:59 +0200)]
synth_intel: Remove incomplete Arria 10 GX support.

The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.

4 years agoproc: Add -nomux switch
Peder Bergebakken Sundt [Thu, 20 Aug 2020 20:58:08 +0000 (22:58 +0200)]
proc: Add -nomux switch

running proc -nomux will ommit the proc_mux pass

4 years agoEnsure smt2 comments are associated with accessors
Noah Moroze [Thu, 20 Aug 2020 20:00:05 +0000 (16:00 -0400)]
Ensure smt2 comments are associated with accessors

4 years agointel: move Cyclone V support to intel_alm
Dan Ravensloft [Mon, 27 Jul 2020 13:21:05 +0000 (14:21 +0100)]
intel: move Cyclone V support to intel_alm

4 years agoMerge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
clairexen [Thu, 20 Aug 2020 14:25:56 +0000 (16:25 +0200)]
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes

techmap/shift_shiftx: Remove the "shiftx2mux" special path.

4 years agoMerge pull request #2344 from YosysHQ/mwk/opt_share-fixes
clairexen [Thu, 20 Aug 2020 14:24:53 +0000 (16:24 +0200)]
Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes

opt_share: Refactor, fix some bugs.

4 years agoMerge pull request #2337 from YosysHQ/mwk/clean-keep-wire
clairexen [Thu, 20 Aug 2020 14:23:55 +0000 (16:23 +0200)]
Merge pull request #2337 from YosysHQ/mwk/clean-keep-wire

opt_clean: Fix module keep rules.

4 years agoMerge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed
clairexen [Thu, 20 Aug 2020 14:23:07 +0000 (16:23 +0200)]
Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed

peeopt.shiftmul: Add a signedness check.

4 years agoMerge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup
clairexen [Thu, 20 Aug 2020 14:21:58 +0000 (16:21 +0200)]
Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanup

Remove passes redundant with opt_dff

4 years agoMerge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix
clairexen [Thu, 20 Aug 2020 14:21:09 +0000 (16:21 +0200)]
Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fix

techmap.CONSTMAP: Handle outputs before inputs.

4 years agoMerge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign
clairexen [Thu, 20 Aug 2020 14:19:37 +0000 (16:19 +0200)]
Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign

peepopt.muldiv: Add a signedness check.

4 years agoMerge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
clairexen [Thu, 20 Aug 2020 14:18:40 +0000 (16:18 +0200)]
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern

techmap: Add support for [] wildcards in techmap_celltype.

4 years agotechmap/shift_shiftx: Remove the "shiftx2mux" special path.
Marcelina Kościelnicka [Wed, 19 Aug 2020 11:59:59 +0000 (13:59 +0200)]
techmap/shift_shiftx: Remove the "shiftx2mux" special path.

Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.

4 years agoBump version
Yosys Bot [Thu, 20 Aug 2020 00:10:07 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2122 from PeterCrozier/struct_array2
clairexen [Wed, 19 Aug 2020 15:58:37 +0000 (17:58 +0200)]
Merge pull request #2122 from PeterCrozier/struct_array2

Support 2D bit arrays in structures. Optimise array indexing.

4 years agoBump version
Yosys Bot [Wed, 19 Aug 2020 00:10:09 +0000 (00:10 +0000)]
Bump version

4 years agoEnsure \A_SIGNED is never used with $shiftx
Xiretza [Fri, 3 Jul 2020 11:13:21 +0000 (13:13 +0200)]
Ensure \A_SIGNED is never used with $shiftx

It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.

4 years agoRespect \A_SIGNED for $shift
Xiretza [Fri, 3 Jul 2020 11:13:21 +0000 (13:13 +0200)]
Respect \A_SIGNED for $shift

This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).

4 years agoinclude both power-of-two and non-power-of-two testcases
N. Engelhardt [Tue, 18 Aug 2020 16:54:22 +0000 (18:54 +0200)]
include both power-of-two and non-power-of-two testcases

4 years agoMerge pull request #2339 from zachjs/display-format-0s
clairexen [Tue, 18 Aug 2020 15:39:01 +0000 (17:39 +0200)]
Merge pull request #2339 from zachjs/display-format-0s

Allow %0s $display format specifier

4 years agoMerge pull request #2338 from zachjs/const-branch-finish
clairexen [Tue, 18 Aug 2020 15:38:07 +0000 (17:38 +0200)]
Merge pull request #2338 from zachjs/const-branch-finish

Propagate const_fold through generate blocks and branches

4 years agoMerge pull request #2317 from zachjs/expand-genblock
clairexen [Tue, 18 Aug 2020 15:37:11 +0000 (17:37 +0200)]
Merge pull request #2317 from zachjs/expand-genblock

Fix generate scoping issues

4 years agoMerge branch 'zachjs-const-func-block-var'
Claire Wolf [Tue, 18 Aug 2020 15:32:00 +0000 (17:32 +0200)]
Merge branch 'zachjs-const-func-block-var'

4 years agoMerge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs...
Claire Wolf [Tue, 18 Aug 2020 15:27:51 +0000 (17:27 +0200)]
Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into zachjs-const-func-block-var

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
4 years agoMerge pull request #2281 from zachjs/const-real
clairexen [Tue, 18 Aug 2020 15:22:20 +0000 (17:22 +0200)]
Merge pull request #2281 from zachjs/const-real

Allow reals as constant function parameters

4 years agoopt_share: Refactor, fix some bugs.
Marcelina Kościelnicka [Mon, 17 Aug 2020 15:13:17 +0000 (17:13 +0200)]
opt_share: Refactor, fix some bugs.

Fixes #2334.
Fixes #2335.
Fixes #2336.

4 years agoBump version
Yosys Bot [Fri, 14 Aug 2020 00:10:13 +0000 (00:10 +0000)]
Bump version

4 years agointel_alm: fix typo in MISTRAL_MUL27X27 cell name
Dan Ravensloft [Thu, 13 Aug 2020 14:30:03 +0000 (15:30 +0100)]
intel_alm: fix typo in MISTRAL_MUL27X27 cell name

4 years agoBump version
Yosys Bot [Thu, 13 Aug 2020 00:10:08 +0000 (00:10 +0000)]
Bump version

4 years agoMerge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout
whitequark [Wed, 12 Aug 2020 20:02:18 +0000 (20:02 +0000)]
Merge pull request #2340 from andy-knowles/cxxrtl-fix-alu-carryout

cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False

4 years agocxxrtl.h: Fix incorrect CarryOut in alu()
Andy Knowles [Wed, 12 Aug 2020 19:04:34 +0000 (21:04 +0200)]
cxxrtl.h: Fix incorrect CarryOut in alu()

4 years agointel_alm: add more megafunctions. NFC.
Dan Ravensloft [Wed, 12 Aug 2020 13:55:42 +0000 (14:55 +0100)]
intel_alm: add more megafunctions. NFC.

4 years agocxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False
Andy Knowles [Wed, 12 Aug 2020 09:32:57 +0000 (11:32 +0200)]
cxxrtl.h: Fix incorrect CarryOut in alu when Bits % 32 != 0 && Invert == False

4 years agoBump version
Yosys Bot [Mon, 10 Aug 2020 09:30:51 +0000 (09:30 +0000)]
Bump version

4 years agoPropagate const_fold through generate blocks and branches
Zachary Snow [Sun, 9 Aug 2020 15:52:55 +0000 (09:52 -0600)]
Propagate const_fold through generate blocks and branches

4 years agoAllow %0s $display format specifier
Zachary Snow [Sun, 9 Aug 2020 15:31:57 +0000 (09:31 -0600)]
Allow %0s $display format specifier

4 years agoopt_clean: Fix module keep rules.
Marcelina Kościelnicka [Sun, 9 Aug 2020 11:53:01 +0000 (13:53 +0200)]
opt_clean: Fix module keep rules.

- wires with keep attribute now force a module to be kept
- presence of $memwr and $meminit cells no longer forces a module to be
  kept

4 years agoRemove now-redundant dff2dffe pass.
Marcelina Kościelnicka [Tue, 21 Jul 2020 17:24:09 +0000 (19:24 +0200)]
Remove now-redundant dff2dffe pass.

4 years agoRemove now-redundant dff2dffs pass.
Marcelina Kościelnicka [Tue, 21 Jul 2020 14:41:26 +0000 (16:41 +0200)]
Remove now-redundant dff2dffs pass.

4 years agopeepopt: Remove now-redundant dffmux pattern.
Marcelina Kościelnicka [Wed, 15 Jul 2020 00:37:43 +0000 (02:37 +0200)]
peepopt: Remove now-redundant dffmux pattern.

4 years agoRemove now-redundant opt_rmdff pass.
Marcelina Kościelnicka [Wed, 15 Jul 2020 00:54:40 +0000 (02:54 +0200)]
Remove now-redundant opt_rmdff pass.

4 years agoReplace opt_rmdff with opt_dff.
Marcelina Kościelnicka [Mon, 20 Jul 2020 21:19:51 +0000 (23:19 +0200)]
Replace opt_rmdff with opt_dff.

4 years agopeeopt.shiftmul: Add a signedness check.
Marcelina Kościelnicka [Wed, 5 Aug 2020 19:01:20 +0000 (21:01 +0200)]
peeopt.shiftmul: Add a signedness check.

Fixes #2332.