openpower-isa.git
2 years agorepeat power decode test to check performance
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 14:39:37 +0000 (14:39 +0000)]
repeat power decode test to check performance

2 years agobit of a tidyup of crtl:
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 14:26:47 +0000 (14:26 +0000)]
bit of a tidyup of crtl:
* code-comments for template-creation
* use "with open(xxx) as file" rather than explicit open-then-close
* use abspath on __file__ to get the relative position of the templates
  (makes it possible to run from locations other than current directory)
* add the module location to sys.path so as to be able to get at it
  (again even when running from locations other than cwd)

2 years agoadd load-store byte-reverse 64-bit unit test
Luke Kenneth Casson Leighton [Thu, 23 Dec 2021 12:40:56 +0000 (12:40 +0000)]
add load-store byte-reverse 64-bit unit test
(ldbrx/stdbrx)

2 years agoAdd CRTL templates
Mikolaj Wielgus [Thu, 23 Dec 2021 01:59:13 +0000 (01:59 +0000)]
Add CRTL templates

Forgot to add them in the previous commit.

2 years agoGive unique names to CRTL-generated modules
Mikolaj Wielgus [Thu, 23 Dec 2021 01:52:51 +0000 (01:52 +0000)]
Give unique names to CRTL-generated modules

test_power_decoder.py now passes.

2 years agoMove "pending" set to C
Mikolaj Wielgus [Thu, 23 Dec 2021 00:39:04 +0000 (00:39 +0000)]
Move "pending" set to C

Finally something works.

2 years agoMake _PySignalState CRTL-aware
Mikolaj Wielgus [Wed, 22 Dec 2021 14:22:16 +0000 (14:22 +0000)]
Make _PySignalState CRTL-aware

2 years agotake a copy of the wb_get memory and then for each unit test
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 15:46:32 +0000 (15:46 +0000)]
take a copy of the wb_get memory and then for each unit test
overwrite it (resetting) if any unit test has a replacement memory

2 years agoISACaller (actually RADIXMMU) only do virtual memory mode
Luke Kenneth Casson Leighton [Tue, 21 Dec 2021 14:41:32 +0000 (14:41 +0000)]
ISACaller (actually RADIXMMU) only do virtual memory mode
when MSR.DR is set (which is virtual memory requested bit)

2 years agoGenerate variable declaration in some missing places
Mikolaj Wielgus [Mon, 20 Dec 2021 18:07:32 +0000 (18:07 +0000)]
Generate variable declaration in some missing places

2 years agocreate header/footer for crtl code-generation
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 15:47:50 +0000 (15:47 +0000)]
create header/footer for crtl code-generation
code +=
code +=
...
is a bit naff

2 years agowhoops forgot to trap if non-execute (instruction) invalid
Luke Kenneth Casson Leighton [Mon, 20 Dec 2021 14:40:57 +0000 (14:40 +0000)]
whoops forgot to trap if non-execute (instruction) invalid
ISACaller RADIXMMU returns exception, there are two types:
LDST (0x300) and I-Fetch (0x400)

2 years agoTODO notes for executing ISACaller Invalid Instruction Fetch
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 21:29:50 +0000 (21:29 +0000)]
TODO notes for executing ISACaller Invalid Instruction Fetch
must set some SRR bits coming from the MMU

2 years agopass the mode (LOAD,EXECUTE,STORE) through ISACaller RADIX MMU
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 21:27:09 +0000 (21:27 +0000)]
pass the mode (LOAD,EXECUTE,STORE) through ISACaller RADIX MMU
so that the right exception type can be raised (0x300 rather than 0x400)

2 years agoadd "stop at pc" argument to TestCase,
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 20:50:46 +0000 (20:50 +0000)]
add "stop at pc" argument to TestCase,
used to hard-stop if an instruction at this address is attempted to
be executed (without executing it)

2 years agosv/binutils.py: provide sketch sv_decode.vhdl converter
Dmitry Selyutin [Sun, 19 Dec 2021 19:37:34 +0000 (19:37 +0000)]
sv/binutils.py: provide sketch sv_decode.vhdl converter

2 years agosave mmu simulation to different gtkwave file in TestRunnerBase
Luke Kenneth Casson Leighton [Sun, 19 Dec 2021 19:00:38 +0000 (19:00 +0000)]
save mmu simulation to different gtkwave file in TestRunnerBase

2 years agobit more verbose info about number of instructions run
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 18:46:44 +0000 (18:46 +0000)]
bit more verbose info about number of instructions run

2 years agouse new core domain variable in TestRunnerBase
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 15:37:34 +0000 (15:37 +0000)]
use new core domain variable in TestRunnerBase
and add the dbgsync domain back in

2 years agoupdate comments in wb_get
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 11:51:56 +0000 (11:51 +0000)]
update comments in wb_get

2 years agoooo annoying, it is actually icache.ibus
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:56:21 +0000 (01:56 +0000)]
ooo annoying, it is actually icache.ibus

2 years agowhoops error in accessing icache.ibus which is an intermediary
Luke Kenneth Casson Leighton [Sat, 18 Dec 2021 01:08:11 +0000 (01:08 +0000)]
whoops error in accessing icache.ibus which is an intermediary
set of signals

2 years agoCall the simulator-generated C using the CFFI
Mikolaj Wielgus [Fri, 17 Dec 2021 22:34:06 +0000 (22:34 +0000)]
Call the simulator-generated C using the CFFI

2 years agobug where t1 was set to zero but s2 was not in imdct36_standalone.c
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 20:27:35 +0000 (20:27 +0000)]
bug where t1 was set to zero but s2 was not in imdct36_standalone.c

2 years agostart/stop wb_get in TestRunnerBase, otherwise it never ends
Luke Kenneth Casson Leighton [Thu, 16 Dec 2021 14:21:11 +0000 (14:21 +0000)]
start/stop wb_get in TestRunnerBase, otherwise it never ends

2 years agomust read off of ibus in wb_get TestRunnerBase
Luke Kenneth Casson Leighton [Wed, 15 Dec 2021 15:47:06 +0000 (15:47 +0000)]
must read off of ibus in wb_get TestRunnerBase

2 years agoAdd CFFI as dependency
Mikolaj Wielgus [Tue, 14 Dec 2021 15:50:16 +0000 (15:50 +0000)]
Add CFFI as dependency

2 years agoadd namedtuple MSRSpec
Tobias Platen [Mon, 13 Dec 2021 12:17:02 +0000 (13:17 +0100)]
add namedtuple MSRSpec

2 years agocopy over fake OP_FETCH_FAILED and instruction on instr_fault
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 18:56:48 +0000 (18:56 +0000)]
copy  over fake OP_FETCH_FAILED and instruction on instr_fault

2 years agoenable mmu_cache_wb for wb_get mode in TestRunnerBase
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 17:22:56 +0000 (17:22 +0000)]
enable mmu_cache_wb for wb_get mode in TestRunnerBase

2 years agoadd pretty-print of MMU memory to be used for a TestRunner test
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 15:48:37 +0000 (15:48 +0000)]
add pretty-print of MMU memory to be used for a TestRunner test

2 years agoremove ROTL64(1, idx), just use TLI[7-idx] it is shorter and readable
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 15:19:48 +0000 (15:19 +0000)]
remove ROTL64(1, idx), just use TLI[7-idx] it is shorter and readable

2 years agouse concat in ternlogi to reduce code size
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 15:13:15 +0000 (15:13 +0000)]
use concat in ternlogi to reduce code size

2 years agoadd ternlogi to SVP64Asm
Jacob Lifshay [Fri, 10 Dec 2021 21:19:12 +0000 (13:19 -0800)]
add ternlogi to SVP64Asm

2 years agoformat code
Jacob Lifshay [Fri, 10 Dec 2021 21:07:47 +0000 (13:07 -0800)]
format code

2 years agochange ternlogi to not have Rc field
Jacob Lifshay [Fri, 10 Dec 2021 20:34:23 +0000 (12:34 -0800)]
change ternlogi to not have Rc field

2 years agoadd .gitignore to ignore the generated vhdl
Jacob Lifshay [Fri, 10 Dec 2021 20:30:12 +0000 (12:30 -0800)]
add .gitignore to ignore the generated vhdl

2 years agoadd I-Cache wishbone bus to wb_get when MMU and ROM mode enabled
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 15:46:11 +0000 (15:46 +0000)]
add I-Cache wishbone bus to wb_get when MMU and ROM mode enabled

2 years agoadd warning about creation of "-.csv" which indicates that
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 10:39:01 +0000 (10:39 +0000)]
add warning about creation of "-.csv" which indicates that
some SVP64 instructions have not been correctly identified

2 years agoadd FAST SPRs temporarily to power_enums
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 10:01:57 +0000 (10:01 +0000)]
add FAST SPRs temporarily to power_enums

2 years agomake ternlogi tests run
Jacob Lifshay [Thu, 9 Dec 2021 06:04:10 +0000 (22:04 -0800)]
make ternlogi tests run

2 years agorename ternaryi to ternlogi
Jacob Lifshay [Thu, 9 Dec 2021 04:52:09 +0000 (20:52 -0800)]
rename ternaryi to ternlogi

2 years agoadd initial ternlogi pseudo-code
Jacob Lifshay [Thu, 9 Dec 2021 04:51:41 +0000 (20:51 -0800)]
add initial ternlogi pseudo-code

2 years agoadd instr_fault to PowerDecoder2
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 19:15:53 +0000 (19:15 +0000)]
add instr_fault to PowerDecoder2
this, like LDST exceptions, allows instruction PTE fault-detection
to propagate from I-Cache to Issuer to PowerDecoder2 to OP_FETCH_FAILED
to MMU FSM to MMU to do MMU_LOOKUP to get the PTE which then...
you get the idea

2 years agowhitespace
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 18:56:51 +0000 (18:56 +0000)]
whitespace

2 years agocode-comments for LDSTException.instr_fault
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 13:45:09 +0000 (13:45 +0000)]
code-comments for LDSTException.instr_fault
(which is not actually an exception)

2 years agoadd an on_Display function which is being used by some of us
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 12:47:24 +0000 (12:47 +0000)]
add an on_Display function which is being used by some of us
for debugging purposes (needs a patch, normally would not be needed
but because this is low-level a dummy on_Display has to be provided)

2 years agofound a way to print out the names of the signals
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 12:46:16 +0000 (12:46 +0000)]
found a way to print out the names of the signals
will be useful to see what the heck is going on in the auto-generated c

2 years agoabsolute import again
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 12:30:56 +0000 (12:30 +0000)]
absolute import again

2 years agouse full-path imports (so we know where they come from)
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 12:17:10 +0000 (12:17 +0000)]
use full-path imports (so we know where they come from)

2 years agoWIP: Output C instead of Python for Nmigen simulation
Mikolaj Wielgus [Wed, 8 Dec 2021 11:26:58 +0000 (11:26 +0000)]
WIP: Output C instead of Python for Nmigen simulation

2 years agoSource Nmigen simulator from this repository
Mikolaj Wielgus [Wed, 8 Dec 2021 08:09:28 +0000 (08:09 +0000)]
Source Nmigen simulator from this repository

2 years agowhoops wrong number
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 15:10:47 +0000 (15:10 +0000)]
whoops wrong number

2 years agoadd OP_FETCH_FAILED micro-op
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 14:59:03 +0000 (14:59 +0000)]
add OP_FETCH_FAILED micro-op

2 years agofix broken url
Jacob Lifshay [Tue, 7 Dec 2021 03:00:28 +0000 (19:00 -0800)]
fix broken url

2 years agofix microwatt_mmu and and wishbone_memory output in gtkwave
Tobias Platen [Sun, 5 Dec 2021 17:33:32 +0000 (18:33 +0100)]
fix microwatt_mmu and and wishbone_memory output in gtkwave

2 years agoconnect to dcache.bus standard interface when using wb_get
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 01:07:50 +0000 (01:07 +0000)]
connect to dcache.bus standard interface when using wb_get

2 years agocorrect import of wb_get function
Luke Kenneth Casson Leighton [Sun, 5 Dec 2021 00:26:30 +0000 (00:26 +0000)]
correct import of wb_get function

2 years agoadd name parameter to wb_get
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 18:14:43 +0000 (18:14 +0000)]
add name parameter to wb_get

2 years agoadd wb_get function for emulating wishbone interface
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 17:59:24 +0000 (17:59 +0000)]
add wb_get function for emulating wishbone interface

2 years agoraise a MemException in ISACaller RADIXMMU
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 17:47:36 +0000 (17:47 +0000)]
raise a MemException in ISACaller RADIXMMU
and capture it in ISACaller, and throw TRAP 0x300

2 years agoenable MMU in SimRunner if requested. now HDL and ISACaller run MMU
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 17:47:03 +0000 (17:47 +0000)]
enable MMU in SimRunner if requested.  now HDL and ISACaller run MMU

2 years agotest in SimState for access to RADIX memory, bypass and get contents direct
Luke Kenneth Casson Leighton [Sat, 4 Dec 2021 17:46:23 +0000 (17:46 +0000)]
test in SimState for access to RADIX memory, bypass and get contents direct

2 years agoadd a namedtuple LDSTExceptionTuple which allows obtaining
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 17:32:00 +0000 (17:32 +0000)]
add a namedtuple LDSTExceptionTuple which allows obtaining
list of all the exception types in LDSTException

2 years agoadd link to exceptions in gtkw traces
Luke Kenneth Casson Leighton [Fri, 3 Dec 2021 14:22:43 +0000 (14:22 +0000)]
add link to exceptions in gtkw traces

2 years agoregspec_decode_write now stores the decoded write info into Signals
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 15:48:36 +0000 (15:48 +0000)]
regspec_decode_write now stores the decoded write info into Signals
to make it easier to debug

2 years agospecify length in RegDecodeInfo explicitly so that the information
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 15:39:44 +0000 (15:39 +0000)]
specify length in RegDecodeInfo explicitly so that the information
that needs to be captured (held by the ReservationStation) is
not too great.  some of the info is actually expressions, hence why
using len() or Signal.like() does not work, it is too long

2 years agouse namedtuple in get_rdflags
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 15:05:39 +0000 (15:05 +0000)]
use namedtuple in get_rdflags

2 years agouse namedtuple for regspec_decode
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 15:04:30 +0000 (15:04 +0000)]
use namedtuple for regspec_decode

2 years agoadd module to regspec_decode_* and get_rdflags
Luke Kenneth Casson Leighton [Thu, 2 Dec 2021 14:55:54 +0000 (14:55 +0000)]
add module to regspec_decode_* and get_rdflags

2 years agomove ternlogi to SHIFT_ROT unit
Jacob Lifshay [Thu, 2 Dec 2021 03:00:36 +0000 (19:00 -0800)]
move ternlogi to SHIFT_ROT unit

2 years agofix sv_analysis command, cuz script created by setup.py passes no parameters to function
Jacob Lifshay [Thu, 2 Dec 2021 00:49:51 +0000 (16:49 -0800)]
fix sv_analysis command, cuz script created by setup.py passes no parameters to function

2 years agoformat code
Jacob Lifshay [Thu, 2 Dec 2021 00:42:13 +0000 (16:42 -0800)]
format code

2 years agofix expected state in hazard test
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 18:05:34 +0000 (18:05 +0000)]
fix expected state in hazard test

2 years agofix expected state in hazard case_regression_1
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 18:03:02 +0000 (18:03 +0000)]
fix expected state in hazard case_regression_1

2 years agoadd a proper twin addi regression which tests ReservationStations
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 13:43:51 +0000 (13:43 +0000)]
add a proper twin addi regression which tests ReservationStations
increase number of operations in hazard random test to 20

2 years agoadd regspec_decode which takes readmode arg and returns read/write
Luke Kenneth Casson Leighton [Wed, 1 Dec 2021 12:06:46 +0000 (12:06 +0000)]
add regspec_decode which takes readmode arg and returns read/write
as appropriate

2 years agosv_analysis: decouple declarations and definitions
Dmitry Selyutin [Tue, 30 Nov 2021 20:31:08 +0000 (20:31 +0000)]
sv_analysis: decouple declarations and definitions

2 years agosv_analysis: use is instead of eq for enums
Dmitry Selyutin [Tue, 30 Nov 2021 13:42:10 +0000 (13:42 +0000)]
sv_analysis: use is instead of eq for enums

2 years agosv_analysis: fix single-line binutils comments
Dmitry Selyutin [Tue, 30 Nov 2021 13:41:19 +0000 (13:41 +0000)]
sv_analysis: fix single-line binutils comments

2 years agoadd randomised hazard test
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 18:29:09 +0000 (18:29 +0000)]
add randomised hazard test

2 years agoadd two more hazard tests
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 16:18:18 +0000 (16:18 +0000)]
add two more hazard tests

2 years agoattempting to use PowerDecode2 in non-svp64 mode
Luke Kenneth Casson Leighton [Tue, 30 Nov 2021 10:43:47 +0000 (10:43 +0000)]
attempting to use PowerDecode2 in non-svp64 mode

2 years agosv_analysis: decouple common disclaimer
Dmitry Selyutin [Sat, 27 Nov 2021 20:28:22 +0000 (20:28 +0000)]
sv_analysis: decouple common disclaimer

2 years agosv_analysis: introduce stub binutils format
Dmitry Selyutin [Sat, 27 Nov 2021 19:36:25 +0000 (19:36 +0000)]
sv_analysis: introduce stub binutils format

2 years agosv_analysis: support format argument
Dmitry Selyutin [Sat, 27 Nov 2021 19:35:01 +0000 (19:35 +0000)]
sv_analysis: support format argument

2 years agoadd extra overlap hazard test
Luke Kenneth Casson Leighton [Sat, 27 Nov 2021 14:29:51 +0000 (14:29 +0000)]
add extra overlap hazard test

2 years agoShorten expected state code for case_extsb using exts function
R Veera Kumar [Fri, 26 Nov 2021 17:48:02 +0000 (23:18 +0530)]
Shorten expected state code for case_extsb using exts function

2 years agoShorten expected state code for case_extsb in alu_cases unit test
R Veera Kumar [Fri, 26 Nov 2021 03:09:56 +0000 (08:39 +0530)]
Shorten expected state code for case_extsb in alu_cases unit test

2 years agoShorten expected state code for case_rand in alu_cases unit test
R Veera Kumar [Fri, 26 Nov 2021 02:53:12 +0000 (08:23 +0530)]
Shorten expected state code for case_rand in alu_cases unit test

2 years agoShorten case_rand_imm alu test case code
R Veera Kumar [Fri, 26 Nov 2021 02:26:50 +0000 (07:56 +0530)]
Shorten case_rand_imm alu test case code

Shorten addis sub test code
Shorten subfic sub test code in general
In subfic case shorten carry_out32 execution code
Make carry_out32 variable boolean and expected state ca var less confusing

2 years agoMake carry_out32 variable boolean and expected state ca var less confusing
R Veera Kumar [Fri, 26 Nov 2021 01:53:29 +0000 (07:23 +0530)]
Make carry_out32 variable boolean and expected state ca var less confusing

2 years agoShortened code in case_addis_nonzero_r0 alu test case
R Veera Kumar [Thu, 25 Nov 2021 10:15:21 +0000 (15:45 +0530)]
Shortened code in case_addis_nonzero_r0 alu test case

2 years agoCorrect add-equal operator in case_rand_imm
R Veera Kumar [Thu, 25 Nov 2021 09:45:18 +0000 (15:15 +0530)]
Correct add-equal operator in case_rand_imm

2 years agoShort the code of case_rand_imm
R Veera Kumar [Thu, 25 Nov 2021 01:21:23 +0000 (06:51 +0530)]
Short the code of case_rand_imm

2 years agoFix line so that 80 characters per line is kept and removed a comment
R Veera Kumar [Wed, 24 Nov 2021 23:47:35 +0000 (05:17 +0530)]
Fix line so that 80 characters per line is kept and removed a comment

2 years agoAdd expected state to case_rand_imm in alu_cases unit test
R Veera Kumar [Wed, 24 Nov 2021 23:39:34 +0000 (05:09 +0530)]
Add expected state to case_rand_imm in alu_cases unit test

2 years agocorrections to hazard overlap test
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 23:12:00 +0000 (23:12 +0000)]
corrections to hazard overlap test

2 years agoadd extra hazard unit tests
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 22:46:37 +0000 (22:46 +0000)]
add extra hazard unit tests

2 years agotidyup on case_0_adde
Luke Kenneth Casson Leighton [Wed, 24 Nov 2021 16:17:29 +0000 (16:17 +0000)]
tidyup on case_0_adde