yosys.git
4 years agoRemove clkpart
Eddie Hung [Fri, 6 Dec 2019 01:25:26 +0000 (17:25 -0800)]
Remove clkpart

4 years agoRevert "Special abc9_clock wire to contain only clock signal"
Eddie Hung [Thu, 5 Dec 2019 19:11:53 +0000 (11:11 -0800)]
Revert "Special abc9_clock wire to contain only clock signal"

This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.

4 years agoMissing wire declaration
Eddie Hung [Thu, 5 Dec 2019 07:04:40 +0000 (23:04 -0800)]
Missing wire declaration

4 years agoabc9_map.v to transform INIT=1 to INIT=0
Eddie Hung [Thu, 5 Dec 2019 05:36:41 +0000 (21:36 -0800)]
abc9_map.v to transform INIT=1 to INIT=0

4 years agoOh deary me
Eddie Hung [Thu, 5 Dec 2019 04:33:24 +0000 (20:33 -0800)]
Oh deary me

4 years agoBump ABC to get "&verify -s" fix
Eddie Hung [Thu, 5 Dec 2019 00:37:56 +0000 (16:37 -0800)]
Bump ABC to get "&verify -s" fix

4 years agooutput reg Q -> output Q to suppress warning
Eddie Hung [Thu, 5 Dec 2019 00:34:34 +0000 (16:34 -0800)]
output reg Q -> output Q to suppress warning

4 years agoabc9_map.v to do `zinit' and make INIT = 1'b0
Eddie Hung [Thu, 5 Dec 2019 00:11:02 +0000 (16:11 -0800)]
abc9_map.v to do `zinit' and make INIT = 1'b0

4 years agoCleanup
Eddie Hung [Wed, 4 Dec 2019 03:21:47 +0000 (19:21 -0800)]
Cleanup

4 years agoAdd assertion
Eddie Hung [Wed, 4 Dec 2019 03:21:42 +0000 (19:21 -0800)]
Add assertion

4 years agowrite_xaiger to consume abc9_init attribute for abc9_flops
Eddie Hung [Wed, 4 Dec 2019 02:47:44 +0000 (18:47 -0800)]
write_xaiger to consume abc9_init attribute for abc9_flops

4 years agoAdd abc9_init wire, attach to abc9_flop cell
Eddie Hung [Wed, 4 Dec 2019 02:47:09 +0000 (18:47 -0800)]
Add abc9_init wire, attach to abc9_flop cell

4 years agoRevert "Add INIT value to abc9_control"
Eddie Hung [Tue, 3 Dec 2019 23:40:44 +0000 (15:40 -0800)]
Revert "Add INIT value to abc9_control"

This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22.

4 years agoUpdate ABCREV for upstream bugfix
Eddie Hung [Tue, 3 Dec 2019 23:09:33 +0000 (15:09 -0800)]
Update ABCREV for upstream bugfix

4 years agotechmap abc_unmap.v before xilinx_srl -fixed
Eddie Hung [Tue, 3 Dec 2019 22:27:45 +0000 (14:27 -0800)]
techmap abc_unmap.v before xilinx_srl -fixed

4 years agoAdd INIT value to abc9_control
Eddie Hung [Mon, 2 Dec 2019 22:17:06 +0000 (14:17 -0800)]
Add INIT value to abc9_control

4 years agoCleanup
Eddie Hung [Mon, 2 Dec 2019 07:43:28 +0000 (23:43 -0800)]
Cleanup

4 years agoUse pool instead of std::set for determinism
Eddie Hung [Mon, 2 Dec 2019 07:26:17 +0000 (23:26 -0800)]
Use pool instead of std::set for determinism

4 years agoUse pool<> not std::set<> for determinism
Eddie Hung [Mon, 2 Dec 2019 07:19:32 +0000 (23:19 -0800)]
Use pool<> not std::set<> for determinism

5 years agoclkpart -unpart into 'finalize'
Eddie Hung [Thu, 28 Nov 2019 20:59:43 +0000 (12:59 -0800)]
clkpart -unpart into 'finalize'

5 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Thu, 28 Nov 2019 20:58:30 +0000 (12:58 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

5 years agoMove \init signal for non-port signals as long as internally driven
Eddie Hung [Thu, 28 Nov 2019 20:57:36 +0000 (12:57 -0800)]
Move \init signal for non-port signals as long as internally driven

5 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 21:24:03 +0000 (13:24 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

5 years agoFix multiple driver issue
Eddie Hung [Wed, 27 Nov 2019 21:21:59 +0000 (13:21 -0800)]
Fix multiple driver issue

5 years agoAdd multiple driver testcase
Eddie Hung [Wed, 27 Nov 2019 21:22:26 +0000 (13:22 -0800)]
Add multiple driver testcase

5 years agoFix multiple driver issue
Eddie Hung [Wed, 27 Nov 2019 21:21:59 +0000 (13:21 -0800)]
Fix multiple driver issue

5 years agoAdd comment, use sigmap
Eddie Hung [Wed, 27 Nov 2019 21:20:12 +0000 (13:20 -0800)]
Add comment, use sigmap

5 years agoRevert "Fold loop"
Eddie Hung [Wed, 27 Nov 2019 20:35:25 +0000 (12:35 -0800)]
Revert "Fold loop"

This reverts commit da51492dbcc9f19a4808ef18e8ae1222bc55b118.

5 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 18:17:10 +0000 (10:17 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff

5 years agoean call after abc{,9}
Eddie Hung [Wed, 27 Nov 2019 17:10:34 +0000 (09:10 -0800)]
ean call after abc{,9}

5 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 16:19:13 +0000 (08:19 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

5 years agoDo not replace constants with same wire
Eddie Hung [Wed, 27 Nov 2019 16:18:41 +0000 (08:18 -0800)]
Do not replace constants with same wire

5 years agoMerge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
Eddie Hung [Wed, 27 Nov 2019 16:00:22 +0000 (08:00 -0800)]
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd

xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder

5 years agoMerge pull request #1501 from YosysHQ/dave/mem_copy_attr
Clifford Wolf [Wed, 27 Nov 2019 10:25:23 +0000 (11:25 +0100)]
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr

memory_collect: Copy attr from RTLIL::Memory to  cell

5 years agoMerge pull request #1534 from YosysHQ/mwk/opt_share-fix
Clifford Wolf [Wed, 27 Nov 2019 10:23:16 +0000 (11:23 +0100)]
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix

opt_share: Fix handling of fine cells.

5 years agoMerge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
Eddie Hung [Wed, 27 Nov 2019 09:04:29 +0000 (01:04 -0800)]
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve

write_xaiger improvements

5 years agoMerge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 09:03:33 +0000 (01:03 -0800)]
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff

5 years agoMerge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 09:02:21 +0000 (01:02 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff

5 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 09:02:16 +0000 (01:02 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

5 years agoCleanup
Eddie Hung [Wed, 27 Nov 2019 09:01:24 +0000 (01:01 -0800)]
Cleanup

5 years agoCheck for nullptr
Eddie Hung [Wed, 27 Nov 2019 08:51:39 +0000 (00:51 -0800)]
Check for nullptr

5 years agoStray log_dump
Eddie Hung [Wed, 27 Nov 2019 08:50:25 +0000 (00:50 -0800)]
Stray log_dump

5 years agoRevert "submod to bitty rather bussy, for bussy wires used as input and output"
Eddie Hung [Wed, 27 Nov 2019 08:48:22 +0000 (00:48 -0800)]
Revert "submod to bitty rather bussy, for bussy wires used as input and output"

This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45.

5 years agoPromote output wires in sigmap so that can be detected
Eddie Hung [Wed, 27 Nov 2019 07:39:14 +0000 (23:39 -0800)]
Promote output wires in sigmap so that can be detected

5 years agoFix wire width
Eddie Hung [Wed, 27 Nov 2019 07:38:49 +0000 (23:38 -0800)]
Fix wire width

5 years agoFix submod -hidden
Eddie Hung [Tue, 26 Nov 2019 19:57:26 +0000 (11:57 -0800)]
Fix submod -hidden

5 years agoAdd -hidden option to submod
Eddie Hung [Tue, 26 Nov 2019 19:35:15 +0000 (11:35 -0800)]
Add -hidden option to submod

5 years agoNo need for -abc9
Eddie Hung [Wed, 27 Nov 2019 07:08:14 +0000 (23:08 -0800)]
No need for -abc9

5 years agoopt_share: Fix handling of fine cells.
Marcin Kościelnicki [Tue, 26 Nov 2019 23:46:21 +0000 (00:46 +0100)]
opt_share: Fix handling of fine cells.

Fixes #1525.

5 years agolatch -> box
Eddie Hung [Wed, 27 Nov 2019 06:59:05 +0000 (22:59 -0800)]
latch -> box

5 years agoMerge branch 'master' into xaig_dff
Eddie Hung [Wed, 27 Nov 2019 06:56:53 +0000 (22:56 -0800)]
Merge branch 'master' into xaig_dff

5 years agoAdd citation
Eddie Hung [Wed, 27 Nov 2019 06:51:16 +0000 (22:51 -0800)]
Add citation

5 years agoCheck for either sign or zero extension for postAdd packing
Eddie Hung [Wed, 27 Nov 2019 05:26:53 +0000 (21:26 -0800)]
Check for either sign or zero extension for postAdd packing

5 years agoRemove notes
Eddie Hung [Wed, 27 Nov 2019 06:41:35 +0000 (22:41 -0800)]
Remove notes

5 years agoFold loop
Eddie Hung [Mon, 25 Nov 2019 23:43:37 +0000 (15:43 -0800)]
Fold loop

5 years agoDo not sigmap keep bits inside write_xaiger
Eddie Hung [Mon, 25 Nov 2019 23:42:07 +0000 (15:42 -0800)]
Do not sigmap keep bits inside write_xaiger

5 years agoxaiger: do not promote output wires
Eddie Hung [Wed, 27 Nov 2019 03:03:02 +0000 (19:03 -0800)]
xaiger: do not promote output wires

5 years agoAdd testcase derived from fastfir_dynamictaps benchmark
Eddie Hung [Wed, 27 Nov 2019 05:26:30 +0000 (21:26 -0800)]
Add testcase derived from fastfir_dynamictaps benchmark

5 years agoxaiger: do not promote output wires
Eddie Hung [Wed, 27 Nov 2019 03:03:02 +0000 (19:03 -0800)]
xaiger: do not promote output wires

5 years agoMove 'clean' from map_luts to finalize
Eddie Hung [Tue, 26 Nov 2019 22:51:39 +0000 (14:51 -0800)]
Move 'clean' from map_luts to finalize

5 years agoFix submod -hidden
Eddie Hung [Tue, 26 Nov 2019 19:57:26 +0000 (11:57 -0800)]
Fix submod -hidden

5 years agoclkpart to use 'submod -hidden'
Eddie Hung [Tue, 26 Nov 2019 19:35:32 +0000 (11:35 -0800)]
clkpart to use 'submod -hidden'

5 years agoAdd -hidden option to submod
Eddie Hung [Tue, 26 Nov 2019 19:35:15 +0000 (11:35 -0800)]
Add -hidden option to submod

5 years agoUpdate docs with bullet points
Eddie Hung [Tue, 26 Nov 2019 19:12:58 +0000 (11:12 -0800)]
Update docs with bullet points

5 years agoxilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki [Tue, 26 Nov 2019 04:04:28 +0000 (05:04 +0100)]
xilinx: Add simulation models for IOBUF and OBUFT.

5 years agoMove \init from source wire to submod if output port
Eddie Hung [Tue, 26 Nov 2019 00:07:47 +0000 (16:07 -0800)]
Move \init from source wire to submod if output port

5 years agoAdd testcase where \init is copied
Eddie Hung [Tue, 26 Nov 2019 00:07:35 +0000 (16:07 -0800)]
Add testcase where \init is copied

5 years agoFold loop
Eddie Hung [Mon, 25 Nov 2019 23:43:37 +0000 (15:43 -0800)]
Fold loop

5 years agoDo not sigmap keep bits inside write_xaiger
Eddie Hung [Mon, 25 Nov 2019 23:42:07 +0000 (15:42 -0800)]
Do not sigmap keep bits inside write_xaiger

5 years agoclkpart to analyse async flops too
Eddie Hung [Mon, 25 Nov 2019 20:04:11 +0000 (12:04 -0800)]
clkpart to analyse async flops too

5 years agoFix debug
Eddie Hung [Mon, 25 Nov 2019 20:59:34 +0000 (12:59 -0800)]
Fix debug

5 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Mon, 25 Nov 2019 20:42:09 +0000 (12:42 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff

5 years agoSpecial abc9_clock wire to contain only clock signal
Eddie Hung [Mon, 25 Nov 2019 20:36:13 +0000 (12:36 -0800)]
Special abc9_clock wire to contain only clock signal

5 years agoabc9 to contain time call
Eddie Hung [Mon, 25 Nov 2019 20:35:57 +0000 (12:35 -0800)]
abc9 to contain time call

5 years agoabc9 to no longer to clock partitioning, operate on whole modules only
Eddie Hung [Mon, 25 Nov 2019 20:35:38 +0000 (12:35 -0800)]
abc9 to no longer to clock partitioning, operate on whole modules only

5 years agoclkpart to analyse async flops too
Eddie Hung [Mon, 25 Nov 2019 20:04:11 +0000 (12:04 -0800)]
clkpart to analyse async flops too

5 years agoclkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki [Sun, 24 Nov 2019 15:05:45 +0000 (16:05 +0100)]
clkbufmap: Add support for inverters in clock path.

5 years agoxilinx: Use INV instead of LUT1 when applicable
Marcin Kościelnicki [Sun, 24 Nov 2019 13:17:46 +0000 (14:17 +0100)]
xilinx: Use INV instead of LUT1 when applicable

5 years agoMerge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 18:29:03 +0000 (10:29 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff

5 years agoMore oopsies
Eddie Hung [Sat, 23 Nov 2019 18:28:46 +0000 (10:28 -0800)]
More oopsies

5 years agoConditioning abc9 on POs not accurate due to cells
Eddie Hung [Sat, 23 Nov 2019 18:26:55 +0000 (10:26 -0800)]
Conditioning abc9 on POs not accurate due to cells

5 years agoFor abc9, run clkpart before ff_map and after abc9
Eddie Hung [Sat, 23 Nov 2019 18:18:22 +0000 (10:18 -0800)]
For abc9, run clkpart before ff_map and after abc9

5 years agoMerge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 18:18:06 +0000 (10:18 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff

5 years agoPrint ".en=" only if there is an enable signal
Eddie Hung [Sat, 23 Nov 2019 18:17:31 +0000 (10:17 -0800)]
Print ".en=" only if there is an enable signal

5 years agoEscape IdStrings
Eddie Hung [Sat, 23 Nov 2019 18:16:56 +0000 (10:16 -0800)]
Escape IdStrings

5 years agoMore sane naming of submod
Eddie Hung [Sat, 23 Nov 2019 18:01:09 +0000 (10:01 -0800)]
More sane naming of submod

5 years agoAdd -set_attr option, -unpart to take attr name
Eddie Hung [Sat, 23 Nov 2019 17:52:17 +0000 (09:52 -0800)]
Add -set_attr option, -unpart to take attr name

5 years agoMerge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 16:39:19 +0000 (08:39 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff

5 years agoMerge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 16:38:48 +0000 (08:38 -0800)]
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff

5 years agoMerge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
Eddie Hung [Sat, 23 Nov 2019 16:22:03 +0000 (08:22 -0800)]
Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff

xaig_dff to support async flops $_DFF_[NP][NP][01]_

5 years agoDo not use log_signal() for empty SigSpec to prevent "{ }"
Eddie Hung [Sat, 23 Nov 2019 07:29:10 +0000 (23:29 -0800)]
Do not use log_signal() for empty SigSpec to prevent "{ }"

5 years agoCall submod once, more meaningful submod names, ignore largest domain
Eddie Hung [Sat, 23 Nov 2019 07:16:15 +0000 (23:16 -0800)]
Call submod once, more meaningful submod names, ignore largest domain

5 years agoMerge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 07:01:18 +0000 (23:01 -0800)]
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff

5 years agoMerge pull request #1520 from pietrmar/fix-1463
Eddie Hung [Sat, 23 Nov 2019 06:45:40 +0000 (22:45 -0800)]
Merge pull request #1520 from pietrmar/fix-1463

coolrunner2: remove spurious log_pop() call, fixes #1463

5 years agoMerge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
Eddie Hung [Sat, 23 Nov 2019 06:28:35 +0000 (22:28 -0800)]
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff

5 years agoRemove redundant flatten
Eddie Hung [Sat, 23 Nov 2019 06:22:56 +0000 (22:22 -0800)]
Remove redundant flatten

5 years agocoolrunner2: remove spurious log_pop() call, fixes #1463
Martin Pietryka [Sat, 23 Nov 2019 05:18:23 +0000 (06:18 +0100)]
coolrunner2: remove spurious log_pop() call, fixes #1463

This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.

Signed-off-by: Martin Pietryka <martin@pietryka.at>
5 years agosubmod to bitty rather bussy, for bussy wires used as input and output
Eddie Hung [Sat, 23 Nov 2019 04:53:58 +0000 (20:53 -0800)]
submod to bitty rather bussy, for bussy wires used as input and output

5 years agoStray dump
Eddie Hung [Sat, 23 Nov 2019 04:53:48 +0000 (20:53 -0800)]
Stray dump

5 years agoMove clkpart into passes/hierarchy
Eddie Hung [Sat, 23 Nov 2019 01:25:53 +0000 (17:25 -0800)]
Move clkpart into passes/hierarchy