yosys.git
4 years agoMerge pull request #2088 from rswarbrick/count-at
whitequark [Thu, 28 May 2020 09:41:17 +0000 (09:41 +0000)]
Merge pull request #2088 from rswarbrick/count-at

Minor optimisation in Module::wire() and Module::cell()

4 years agoMerge pull request #2087 from rswarbrick/lex-warn
whitequark [Thu, 28 May 2020 09:41:04 +0000 (09:41 +0000)]
Merge pull request #2087 from rswarbrick/lex-warn

Silence spurious warning in Verilog lexer when compiling with GCC

4 years agoMerge pull request #2086 from rswarbrick/sigbit
whitequark [Thu, 28 May 2020 09:40:49 +0000 (09:40 +0000)]
Merge pull request #2086 from rswarbrick/sigbit

Use default copy constructor for RTLIL::SigBit

4 years agoMerge pull request #2084 from rswarbrick/c_str
whitequark [Thu, 28 May 2020 09:40:35 +0000 (09:40 +0000)]
Merge pull request #2084 from rswarbrick/c_str

Use c_str(), not str() for IdString/std::string == and != operators

4 years agoMerge pull request #2090 from whitequark/cxxrtl-fixes
whitequark [Tue, 26 May 2020 22:18:14 +0000 (22:18 +0000)]
Merge pull request #2090 from whitequark/cxxrtl-fixes

Minor fixes for CXXRTL

4 years agocxxrtl: make logging a little bit nicer.
whitequark [Tue, 26 May 2020 21:37:32 +0000 (21:37 +0000)]
cxxrtl: make logging a little bit nicer.

4 years agocxxrtl: add missing parts of commit 281c9685.
whitequark [Tue, 26 May 2020 06:00:40 +0000 (06:00 +0000)]
cxxrtl: add missing parts of commit 281c9685.

4 years agoSilence spurious warning in Verilog lexer when compiling with GCC
Rupert Swarbrick [Fri, 22 May 2020 13:29:42 +0000 (14:29 +0100)]
Silence spurious warning in Verilog lexer when compiling with GCC

The chosen value shouldn't have any effect. I considered something
clearly wrong like -1, but there's no checking inside the generated
lexer, and I suspect this will cause even weirder bugs if triggered
than just setting it to INITIAL.

4 years agoMinor optimisation in Module::wire() and Module::cell()
Rupert Swarbrick [Tue, 26 May 2020 14:19:39 +0000 (15:19 +0100)]
Minor optimisation in Module::wire() and Module::cell()

The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.

Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().

Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.

4 years agoUse default copy constructor for RTLIL::SigBit
Rupert Swarbrick [Fri, 22 May 2020 15:59:24 +0000 (16:59 +0100)]
Use default copy constructor for RTLIL::SigBit

There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).

This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.

4 years agoUse c_str(), not str() for IdString/std::string == and != operators
Rupert Swarbrick [Tue, 26 May 2020 10:51:06 +0000 (11:51 +0100)]
Use c_str(), not str() for IdString/std::string == and != operators

These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.

Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.

Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.

4 years agoMerge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy
Eddie Hung [Mon, 25 May 2020 21:21:10 +0000 (14:21 -0700)]
Merge pull request #2078 from YosysHQ/eddie/xilinx_sim_tidy

xilinx: tidy up cells_sim.v a little

4 years agotests: xilinx macc test to have initval, shorten BMC depth for runtime
Eddie Hung [Mon, 25 May 2020 16:35:41 +0000 (09:35 -0700)]
tests: xilinx macc test to have initval, shorten BMC depth for runtime

4 years agoxilinx: tidy up cells_sim.v a little
Eddie Hung [Mon, 25 May 2020 16:47:08 +0000 (09:47 -0700)]
xilinx: tidy up cells_sim.v a little

4 years agoMerge pull request #2044 from YosysHQ/eddie/fix2037
Eddie Hung [Mon, 25 May 2020 16:14:00 +0000 (09:14 -0700)]
Merge pull request #2044 from YosysHQ/eddie/fix2037

verilog: allow attributes on behavioural statements (including null statement)

4 years agoverilog: move attr from simple_behav_stmt to its children to attach
Eddie Hung [Thu, 21 May 2020 16:46:26 +0000 (09:46 -0700)]
verilog: move attr from simple_behav_stmt to its children to attach

4 years agotest: add attribute-before-stmt test from @nakengelhardt
Eddie Hung [Thu, 14 May 2020 23:32:14 +0000 (16:32 -0700)]
test: add attribute-before-stmt test from @nakengelhardt

4 years agoverilog: do not warn for attributes on null statements
Eddie Hung [Thu, 14 May 2020 17:46:40 +0000 (10:46 -0700)]
verilog: do not warn for attributes on null statements

4 years agotests: add an generate-else test too
Eddie Hung [Mon, 11 May 2020 17:26:08 +0000 (10:26 -0700)]
tests: add an generate-else test too

4 years agoverilog: handle empty generate statement by removing gen_stmt_or_null...
Eddie Hung [Mon, 11 May 2020 17:20:33 +0000 (10:20 -0700)]
verilog: handle empty generate statement by removing gen_stmt_or_null...

... rule which causes a s/r conflict. Now we get an empty genblock,
which should be okay.

4 years agoverilog: fix #2037 by permitting (and freeing) attributes on null stmt
Eddie Hung [Mon, 11 May 2020 16:33:19 +0000 (09:33 -0700)]
verilog: fix #2037 by permitting (and freeing) attributes on null stmt

4 years agotests: add #2037 testcase
Eddie Hung [Mon, 11 May 2020 16:33:11 +0000 (09:33 -0700)]
tests: add #2037 testcase

4 years agoMerge pull request #2015 from boqwxp/qbfsat-bisection
clairexen [Mon, 25 May 2020 13:50:18 +0000 (15:50 +0200)]
Merge pull request #2015 from boqwxp/qbfsat-bisection

qbfsat: Add an iterative bisection optimization method and make it the default.

4 years agoMerge pull request #2075 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung [Sun, 24 May 2020 17:10:50 +0000 (10:10 -0700)]
Merge pull request #2075 from YosysHQ/eddie/xaiger_cleanup

xaiger: do not derive cells

4 years agoxaiger: add testcase
Eddie Hung [Sun, 24 May 2020 15:48:23 +0000 (08:48 -0700)]
xaiger: add testcase

4 years agoxaiger: do not derive cells
Eddie Hung [Sun, 24 May 2020 15:17:30 +0000 (08:17 -0700)]
xaiger: do not derive cells

4 years agoMerge pull request #2074 from YosysHQ/eddie/ecp5_cleanup
Eddie Hung [Sat, 23 May 2020 16:28:42 +0000 (09:28 -0700)]
Merge pull request #2074 from YosysHQ/eddie/ecp5_cleanup

ecp5: cleanup unused +/ecp5/abc9_model.v

4 years agoecp5: cleanup unused +/ecp5/abc9_model.v
Eddie Hung [Sat, 23 May 2020 15:17:40 +0000 (08:17 -0700)]
ecp5: cleanup unused +/ecp5/abc9_model.v

4 years agoqbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d60f9ad4cdeec9366...
Alberto Gonzalez [Thu, 21 May 2020 23:20:44 +0000 (23:20 +0000)]
qbfsat: Remove cruft inadvertently left untouched in commit 86fc49a9d60f9ad4cdeec93663e7245a9fdf60c6.

4 years agoqbfsat: Add bisection mode and make it the default.
Alberto Gonzalez [Sat, 25 Apr 2020 04:12:02 +0000 (04:12 +0000)]
qbfsat: Add bisection mode and make it the default.

Also adds `-nooptimize` and reorganizes `qbfsat.cc` a bit.

4 years agoMerge pull request #2072 from whitequark/cxxrtl-dont-purge
whitequark [Fri, 22 May 2020 20:08:39 +0000 (20:08 +0000)]
Merge pull request #2072 from whitequark/cxxrtl-dont-purge

cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level

4 years agocxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.
whitequark [Fri, 22 May 2020 17:44:05 +0000 (17:44 +0000)]
cxxrtl: get rid of -O5 aka `opt_clean -purge` optimization level.

This isn't actually necessary anymore after scheduling was improved,
and `clean -purge` disrupts the mapping between wires in the input
RTLIL netlist and the output CXXRTL code.

4 years agoabc9_ops: update comment
Eddie Hung [Fri, 22 May 2020 04:39:13 +0000 (21:39 -0700)]
abc9_ops: update comment

4 years agoMerge pull request #2057 from YosysHQ/eddie/fix_task_attr
Eddie Hung [Thu, 21 May 2020 18:00:36 +0000 (11:00 -0700)]
Merge pull request #2057 from YosysHQ/eddie/fix_task_attr

verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)

4 years agoUpdate frontends/verilog/verilog_parser.y
Eddie Hung [Thu, 21 May 2020 16:10:56 +0000 (09:10 -0700)]
Update frontends/verilog/verilog_parser.y

Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
4 years agoMerge pull request #2059 from boqwxp/logger-vector-to-dict
Miodrag Milanović [Thu, 21 May 2020 13:36:30 +0000 (15:36 +0200)]
Merge pull request #2059 from boqwxp/logger-vector-to-dict

log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.

4 years agoMerge pull request #2046 from PeterCrozier/trap
N. Engelhardt [Wed, 20 May 2020 08:12:24 +0000 (10:12 +0200)]
Merge pull request #2046 from PeterCrozier/trap

Extend YS_DEBUGTRAP to MacOS.

4 years agoMerge pull request #2054 from boqwxp/fix-smtbmc
N. Engelhardt [Wed, 20 May 2020 06:55:36 +0000 (08:55 +0200)]
Merge pull request #2054 from boqwxp/fix-smtbmc

smtbmc: Fix return status handling.

4 years agosmtbmc: Fix typo in error message.
Alberto Gonzalez [Tue, 19 May 2020 16:13:44 +0000 (16:13 +0000)]
smtbmc: Fix typo in error message.

Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
4 years agoAdd force_downto and force_upto wire attributes.
Marcelina Kościelnicka [Mon, 18 May 2020 16:15:03 +0000 (18:15 +0200)]
Add force_downto and force_upto wire attributes.

Fixes #2058.

4 years agoMerge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
Eddie Hung [Mon, 18 May 2020 15:06:50 +0000 (08:06 -0700)]
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff

abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)

4 years agoRevert "Add support for non-power-of-two mem chunks in verific importer"
Claire Wolf [Sun, 17 May 2020 09:31:11 +0000 (11:31 +0200)]
Revert "Add support for non-power-of-two mem chunks in verific importer"

This reverts commit 173aa27ca5ef6e7c0a9277e8da7765adcd63bfe9.

4 years agolog: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning...
Alberto Gonzalez [Thu, 14 May 2020 22:52:07 +0000 (22:52 +0000)]
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.

4 years agoabc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
Eddie Hung [Thu, 14 May 2020 23:44:35 +0000 (16:44 -0700)]
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_

instead of moving them to $__ prefix

4 years agoverilog: attributes before task enable (but 13 s/r conflicts)
Eddie Hung [Thu, 14 May 2020 23:10:11 +0000 (16:10 -0700)]
verilog: attributes before task enable (but 13 s/r conflicts)

4 years agotests: attributes before task enable
Eddie Hung [Thu, 14 May 2020 23:09:41 +0000 (16:09 -0700)]
tests: attributes before task enable

4 years agoMerge pull request #2055 from YosysHQ/eddie/logger_multiple
Eddie Hung [Thu, 14 May 2020 22:30:08 +0000 (15:30 -0700)]
Merge pull request #2055 from YosysHQ/eddie/logger_multiple

logger: fix for multiple calls with same pattern

4 years agoopt_expr: Sx to Sz; spotted by @Xiretza
Eddie Hung [Thu, 14 May 2020 19:14:23 +0000 (12:14 -0700)]
opt_expr: Sx to Sz; spotted by @Xiretza

4 years agoMerge pull request #1994 from YosysHQ/eddie/fix_bug1758
Eddie Hung [Thu, 14 May 2020 18:56:22 +0000 (11:56 -0700)]
Merge pull request #1994 from YosysHQ/eddie/fix_bug1758

opt_expr: improve single-bit $and/$or/$xor/$xnor cells; gate cells too

4 years agologger: clean up doc
Eddie Hung [Thu, 14 May 2020 17:38:31 +0000 (10:38 -0700)]
logger: clean up doc

4 years agoabc9_ops: -prep_hier to create unmap module that removes Q's (* init *)
Eddie Hung [Thu, 14 May 2020 09:09:13 +0000 (02:09 -0700)]
abc9_ops: -prep_hier to create unmap module that removes Q's (* init *)

4 years agoabc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
Eddie Hung [Thu, 14 May 2020 07:29:45 +0000 (00:29 -0700)]
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it

4 years agoFix broken test when ignoring abc9_flop with init == 1'b1
Eddie Hung [Thu, 14 May 2020 05:10:24 +0000 (22:10 -0700)]
Fix broken test when ignoring abc9_flop with init == 1'b1

4 years agoabc9_ops/xaiger: further reducing Module::derive() calls by ...
Eddie Hung [Thu, 14 May 2020 04:56:06 +0000 (21:56 -0700)]
abc9_ops/xaiger: further reducing Module::derive() calls by ...

replacing _all_ (* abc9_box *) instantiations with their derived types

4 years agoCleanup; reduce Module::derive() calls
Eddie Hung [Thu, 14 May 2020 01:02:05 +0000 (18:02 -0700)]
Cleanup; reduce Module::derive() calls

4 years agoecp5: latches_map.v if *not* -asyncprld
Eddie Hung [Wed, 13 May 2020 21:42:18 +0000 (14:42 -0700)]
ecp5: latches_map.v if *not* -asyncprld

4 years agoecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v
Eddie Hung [Wed, 13 May 2020 21:16:42 +0000 (14:16 -0700)]
ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.v

4 years agoecp5: fix rebase mistake
Eddie Hung [Wed, 13 May 2020 21:12:06 +0000 (14:12 -0700)]
ecp5: fix rebase mistake

4 years agoabc9: update to =_$abc9_flops pattern which includes whiteboxes
Eddie Hung [Thu, 23 Apr 2020 00:37:07 +0000 (17:37 -0700)]
abc9: update to =_$abc9_flops pattern which includes whiteboxes

4 years agoabc9_ops: update docs
Eddie Hung [Wed, 22 Apr 2020 20:07:19 +0000 (13:07 -0700)]
abc9_ops: update docs

4 years agoxilinx: gate specify/attributes from iverilog
Eddie Hung [Wed, 22 Apr 2020 03:44:11 +0000 (20:44 -0700)]
xilinx: gate specify/attributes from iverilog

4 years agoabc9: only do +/abc9_map if `DFF
Eddie Hung [Wed, 22 Apr 2020 00:54:24 +0000 (17:54 -0700)]
abc9: only do +/abc9_map if `DFF

4 years agoabc9: rework submod -- since it won't move (* keep *) cells
Eddie Hung [Wed, 22 Apr 2020 00:25:15 +0000 (17:25 -0700)]
abc9: rework submod -- since it won't move (* keep *) cells

4 years agoecp5: TRELLIS_FF bypass path only in async mode
Eddie Hung [Wed, 22 Apr 2020 00:04:26 +0000 (17:04 -0700)]
ecp5: TRELLIS_FF bypass path only in async mode

4 years agotiminginfo: ignore $specify2 cells if EN is false
Eddie Hung [Wed, 22 Apr 2020 00:03:28 +0000 (17:03 -0700)]
timinginfo: ignore $specify2 cells if EN is false

4 years agoxilinx/ice40/ecp5: zinit requires selected wires, so select them all
Eddie Hung [Tue, 21 Apr 2020 22:45:05 +0000 (15:45 -0700)]
xilinx/ice40/ecp5: zinit requires selected wires, so select them all

4 years agoabc9_ops: move assert
Eddie Hung [Tue, 21 Apr 2020 22:44:56 +0000 (15:44 -0700)]
abc9_ops: move assert

4 years agoabc9: put 'aigmap' back
Eddie Hung [Tue, 21 Apr 2020 22:42:05 +0000 (15:42 -0700)]
abc9: put 'aigmap' back

4 years agoxilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells
Eddie Hung [Tue, 21 Apr 2020 21:13:38 +0000 (14:13 -0700)]
xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cells

4 years agoabc9_ops: fix bypass boxes using (* abc9_bypass *)
Eddie Hung [Tue, 21 Apr 2020 21:12:28 +0000 (14:12 -0700)]
abc9_ops: fix bypass boxes using (* abc9_bypass *)

4 years agoabc9_ops: tidy up, suppress error if no boxes/holes
Eddie Hung [Tue, 21 Apr 2020 19:42:09 +0000 (12:42 -0700)]
abc9_ops: tidy up, suppress error if no boxes/holes

4 years agoabc9_ops: -prep_delays to not insert delay box if input connection is const
Eddie Hung [Tue, 21 Apr 2020 19:32:30 +0000 (12:32 -0700)]
abc9_ops: -prep_delays to not insert delay box if input connection is const

4 years agoabc9_ops: cleanup; -prep_dff -> -prep_dff_submod
Eddie Hung [Tue, 21 Apr 2020 19:30:25 +0000 (12:30 -0700)]
abc9_ops: cleanup; -prep_dff -> -prep_dff_submod

4 years agoabc9_ops: add -prep_bypass for auto bypass boxes; refactor
Eddie Hung [Tue, 21 Apr 2020 19:22:39 +0000 (12:22 -0700)]
abc9_ops: add -prep_bypass for auto bypass boxes; refactor

Eliminate need for abc9_{,un}map.v in xilinx
-prep_dff_{hier,unmap} -> -prep_hier

4 years agoabc9_ops: -reintegrate to handle $_FF_; cleanup
Eddie Hung [Thu, 16 Apr 2020 21:03:54 +0000 (14:03 -0700)]
abc9_ops: -reintegrate to handle $_FF_; cleanup

4 years agoxaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity
Eddie Hung [Thu, 16 Apr 2020 21:02:42 +0000 (14:02 -0700)]
xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity

4 years agoaiger: -xaiger to return $_FF_ flops
Eddie Hung [Thu, 16 Apr 2020 21:01:54 +0000 (14:01 -0700)]
aiger: -xaiger to return $_FF_ flops

4 years agoabc9: not enough to techmap_fail on (* init=1 *), hide them using $__
Eddie Hung [Thu, 16 Apr 2020 19:08:59 +0000 (12:08 -0700)]
abc9: not enough to techmap_fail on (* init=1 *), hide them using $__

4 years agoabc9: test to use box file instead of auto
Eddie Hung [Thu, 16 Apr 2020 17:49:33 +0000 (10:49 -0700)]
abc9: test to use box file instead of auto

4 years agoabc9: restore selected_modules()
Eddie Hung [Thu, 16 Apr 2020 17:40:33 +0000 (10:40 -0700)]
abc9: restore selected_modules()

4 years agosynth_*: no need to explicitly read +/abc9_model.v
Eddie Hung [Thu, 16 Apr 2020 17:25:41 +0000 (10:25 -0700)]
synth_*: no need to explicitly read +/abc9_model.v

4 years agoRevert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"
Eddie Hung [Thu, 16 Apr 2020 17:25:22 +0000 (10:25 -0700)]
Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"

This reverts commit 759283fa65b1195ebe3a5bc6890ec622febca0eb, reversing
changes made to f41c7ccfff4bf104c646ca4b85e079a0f91c9151.

4 years agoabc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too
Eddie Hung [Thu, 16 Apr 2020 17:24:02 +0000 (10:24 -0700)]
abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too

4 years agokernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
Eddie Hung [Thu, 16 Apr 2020 17:21:08 +0000 (10:21 -0700)]
kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

4 years agoabc9_ops: -prep_dff_map to error if async flop found
Eddie Hung [Wed, 15 Apr 2020 23:29:11 +0000 (16:29 -0700)]
abc9_ops: -prep_dff_map to error if async flop found

4 years agoUncomment negative setup times; clamp to zero for connectivity
Eddie Hung [Wed, 19 Feb 2020 01:59:33 +0000 (17:59 -0800)]
Uncomment negative setup times; clamp to zero for connectivity

4 years agoabc9: remove redundant wbflip
Eddie Hung [Wed, 15 Apr 2020 23:18:37 +0000 (16:18 -0700)]
abc9: remove redundant wbflip

4 years agoxaiger: always sort input/output bits by port id
Eddie Hung [Wed, 15 Apr 2020 23:16:30 +0000 (16:16 -0700)]
xaiger: always sort input/output bits by port id

redundant for normal design, but necessary for holes

4 years agoabc9: generate $abc9_holes design instead of <name>$holes
Eddie Hung [Wed, 15 Apr 2020 23:13:57 +0000 (16:13 -0700)]
abc9: generate $abc9_holes design instead of <name>$holes

4 years agoabc9_ops: more robust
Eddie Hung [Wed, 15 Apr 2020 22:50:57 +0000 (15:50 -0700)]
abc9_ops: more robust

4 years agoabc9: suppress warnings when no compatible + used flop boxes formed
Eddie Hung [Wed, 15 Apr 2020 22:41:55 +0000 (15:41 -0700)]
abc9: suppress warnings when no compatible + used flop boxes formed

4 years agoxilinx: update abc9_dff tests
Eddie Hung [Wed, 15 Apr 2020 19:28:03 +0000 (12:28 -0700)]
xilinx: update abc9_dff tests

4 years agoxilinx: remove no-longer-relevant test
Eddie Hung [Wed, 15 Apr 2020 19:27:26 +0000 (12:27 -0700)]
xilinx: remove no-longer-relevant test

4 years agoaiger/xaiger: use odd for negedge clk, even for posedge
Eddie Hung [Wed, 15 Apr 2020 19:15:36 +0000 (12:15 -0700)]
aiger/xaiger: use odd for negedge clk, even for posedge

Since abc9 doesn't like negative mergeability values

4 years agoabc9: cleanup
Eddie Hung [Wed, 15 Apr 2020 16:38:29 +0000 (09:38 -0700)]
abc9: cleanup

4 years agoRevert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"
Eddie Hung [Tue, 14 Apr 2020 19:56:28 +0000 (12:56 -0700)]
Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"

This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.

4 years agoabc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output
Eddie Hung [Tue, 14 Apr 2020 19:35:12 +0000 (12:35 -0700)]
abc9_ops: -prep_dff_map to check $_DFF_[NP]_.Q drives module output

4 years agoabc9_ops: do away with '$abc9_cells' selection
Eddie Hung [Tue, 14 Apr 2020 18:38:44 +0000 (11:38 -0700)]
abc9_ops: do away with '$abc9_cells' selection

4 years agoabc9_ops: use new 'design -delete' and 'select -unset'
Eddie Hung [Tue, 14 Apr 2020 18:10:48 +0000 (11:10 -0700)]
abc9_ops: use new 'design -delete' and 'select -unset'

4 years agoecp5: (* abc9_flop *) gated behind YOSYS
Eddie Hung [Tue, 14 Apr 2020 17:36:07 +0000 (10:36 -0700)]
ecp5: (* abc9_flop *) gated behind YOSYS