yosys.git
5 years agoFix typo, and have !{PRE,CLR} behave as CE
Eddie Hung [Thu, 11 Jul 2019 00:15:49 +0000 (17:15 -0700)]
Fix typo, and have !{PRE,CLR} behave as CE

5 years agoMove ABC FF stuff to abc_ff.v; add support for other FD* types
Eddie Hung [Thu, 11 Jul 2019 00:06:05 +0000 (17:06 -0700)]
Move ABC FF stuff to abc_ff.v; add support for other FD* types

5 years agoUncomment IS_C_INVERTED parameter
Eddie Hung [Wed, 10 Jul 2019 23:23:15 +0000 (16:23 -0700)]
Uncomment IS_C_INVERTED parameter

5 years agosynth_xilinx's map_cells stage to techmap ff_map.v
Eddie Hung [Wed, 10 Jul 2019 23:15:57 +0000 (16:15 -0700)]
synth_xilinx's map_cells stage to techmap ff_map.v

5 years agoFix box numbering
Eddie Hung [Wed, 10 Jul 2019 23:12:33 +0000 (16:12 -0700)]
Fix box numbering

5 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Wed, 10 Jul 2019 23:05:41 +0000 (16:05 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_dff

5 years agoMerge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Eddie Hung [Wed, 10 Jul 2019 21:38:13 +0000 (14:38 -0700)]
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime

Error out if -abc9 and -retime specified

5 years agoMerge pull request #1148 from YosysHQ/xc7mux
Eddie Hung [Wed, 10 Jul 2019 21:38:00 +0000 (14:38 -0700)]
Merge pull request #1148 from YosysHQ/xc7mux

synth_xilinx to infer wide multiplexers using new '-widemux <min>' option

5 years agoError out if -abc9 and -retime specified
Eddie Hung [Wed, 10 Jul 2019 19:47:48 +0000 (12:47 -0700)]
Error out if -abc9 and -retime specified

5 years agoAdd some spacing
Eddie Hung [Wed, 10 Jul 2019 19:32:33 +0000 (12:32 -0700)]
Add some spacing

5 years agoAdd some ASCII art explaining mux decomposition
Eddie Hung [Wed, 10 Jul 2019 19:20:04 +0000 (12:20 -0700)]
Add some ASCII art explaining mux decomposition

5 years agoMerge pull request #1177 from YosysHQ/clifford/async
Clifford Wolf [Wed, 10 Jul 2019 06:48:20 +0000 (08:48 +0200)]
Merge pull request #1177 from YosysHQ/clifford/async

Fix clk2fflogic adff reset semantic to negative hold time on reset

5 years agoCall muxpack and pmux2shiftx before cmp2lut
Eddie Hung [Wed, 10 Jul 2019 04:26:38 +0000 (21:26 -0700)]
Call muxpack and pmux2shiftx before cmp2lut

5 years agoRestore opt_clean back to original place
Eddie Hung [Tue, 9 Jul 2019 21:29:58 +0000 (14:29 -0700)]
Restore opt_clean back to original place

5 years agoRestore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
Eddie Hung [Tue, 9 Jul 2019 21:28:54 +0000 (14:28 -0700)]
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6

5 years agosynth_ecp5: Fix typo in copyright header
David Shah [Tue, 9 Jul 2019 21:26:10 +0000 (22:26 +0100)]
synth_ecp5: Fix typo in copyright header

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1174 from YosysHQ/eddie/fix1173
Clifford Wolf [Tue, 9 Jul 2019 20:59:51 +0000 (22:59 +0200)]
Merge pull request #1174 from YosysHQ/eddie/fix1173

Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero

5 years agoMerge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
Clifford Wolf [Tue, 9 Jul 2019 20:51:25 +0000 (22:51 +0200)]
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position

write_verilog: fix placement of case attributes

5 years agoFix tests/various/async FFL test
Clifford Wolf [Tue, 9 Jul 2019 20:44:39 +0000 (22:44 +0200)]
Fix tests/various/async FFL test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove tests/various/async, disable failing ffl test
Clifford Wolf [Tue, 9 Jul 2019 20:21:25 +0000 (22:21 +0200)]
Improve tests/various/async, disable failing ffl test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoExtend using A[1] to preserve don't care
Eddie Hung [Tue, 9 Jul 2019 19:35:41 +0000 (12:35 -0700)]
Extend using A[1] to preserve don't care

5 years agoMerge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc
Eddie Hung [Tue, 9 Jul 2019 19:19:40 +0000 (12:19 -0700)]
Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc

Revert "Add "synth -keepdc" option"

5 years agoMerge remote-tracking branch 'origin/eddie/fix1173' into xc7mux
Eddie Hung [Tue, 9 Jul 2019 19:16:33 +0000 (12:16 -0700)]
Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux

5 years agowrite_verilog: fix placement of case attributes. NFC.
whitequark [Tue, 9 Jul 2019 19:14:03 +0000 (19:14 +0000)]
write_verilog: fix placement of case attributes. NFC.

5 years agoIncrement _TECHMAP_BITS_CONNMAP_ by one since counting from zero
Eddie Hung [Tue, 9 Jul 2019 19:14:00 +0000 (12:14 -0700)]
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero

5 years agoAdd tests/various/async.{sh,v}
Clifford Wolf [Tue, 9 Jul 2019 18:58:59 +0000 (20:58 +0200)]
Add tests/various/async.{sh,v}

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove tests/various/run-test.sh
Clifford Wolf [Tue, 9 Jul 2019 18:58:28 +0000 (20:58 +0200)]
Improve tests/various/run-test.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd tests/simple_abc9/.gitignore
Clifford Wolf [Tue, 9 Jul 2019 18:58:01 +0000 (20:58 +0200)]
Add tests/simple_abc9/.gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoExtend during mux decomposition with 1'bx
Eddie Hung [Tue, 9 Jul 2019 17:59:37 +0000 (10:59 -0700)]
Extend during mux decomposition with 1'bx

5 years agoFix typo and comments
Eddie Hung [Tue, 9 Jul 2019 17:38:07 +0000 (10:38 -0700)]
Fix typo and comments

5 years agoMerge pull request #1170 from YosysHQ/eddie/fix_double_underscore
Eddie Hung [Tue, 9 Jul 2019 17:22:57 +0000 (10:22 -0700)]
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore

Rename __builtin_bswap32 -> bswap32

5 years agoMerge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Tue, 9 Jul 2019 17:22:49 +0000 (10:22 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux

5 years agosynth_xilinx to call commands of synth -coarse directly
Eddie Hung [Tue, 9 Jul 2019 17:21:54 +0000 (10:21 -0700)]
synth_xilinx to call commands of synth -coarse directly

5 years agoRevert "synth_xilinx to call "synth -run coarse" with "-keepdc""
Eddie Hung [Tue, 9 Jul 2019 17:15:02 +0000 (10:15 -0700)]
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""

This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.

5 years agoRevert "Add "synth -keepdc" option"
Eddie Hung [Tue, 9 Jul 2019 17:14:23 +0000 (10:14 -0700)]
Revert "Add "synth -keepdc" option"

5 years agoRename __builtin_bswap32 -> bswap32
Eddie Hung [Tue, 9 Jul 2019 16:35:09 +0000 (09:35 -0700)]
Rename __builtin_bswap32 -> bswap32

5 years agoFix spacing
Eddie Hung [Tue, 9 Jul 2019 16:22:12 +0000 (09:22 -0700)]
Fix spacing

5 years agoFix spacing
Eddie Hung [Tue, 9 Jul 2019 16:16:00 +0000 (09:16 -0700)]
Fix spacing

5 years agoMerge pull request #1168 from whitequark/bugpoint-processes
Clifford Wolf [Tue, 9 Jul 2019 14:59:43 +0000 (16:59 +0200)]
Merge pull request #1168 from whitequark/bugpoint-processes

Add support for processes in bugpoint

5 years agoMerge pull request #1169 from whitequark/more-proc-cleanups
Clifford Wolf [Tue, 9 Jul 2019 14:59:18 +0000 (16:59 +0200)]
Merge pull request #1169 from whitequark/more-proc-cleanups

A new proc_prune pass

5 years agoMerge pull request #1163 from whitequark/more-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:57:16 +0000 (16:57 +0200)]
Merge pull request #1163 from whitequark/more-case-attrs

More support for case rule attributes

5 years agoMerge pull request #1162 from whitequark/rtlil-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:56:29 +0000 (16:56 +0200)]
Merge pull request #1162 from whitequark/rtlil-case-attrs

Allow attributes on individual switch cases in RTLIL

5 years agoMerge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
Clifford Wolf [Tue, 9 Jul 2019 14:49:08 +0000 (16:49 +0200)]
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup

Cleanup synth_xilinx SRL inference, make more consistent

5 years agoproc_prune: promote assigns to module connections when legal.
whitequark [Tue, 9 Jul 2019 08:14:52 +0000 (08:14 +0000)]
proc_prune: promote assigns to module connections when legal.

This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)

5 years agoproc_prune: new pass.
whitequark [Mon, 8 Jul 2019 15:19:01 +0000 (15:19 +0000)]
proc_prune: new pass.

The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.

5 years agobugpoint: add -assigns and -updates options.
whitequark [Tue, 9 Jul 2019 09:08:38 +0000 (09:08 +0000)]
bugpoint: add -assigns and -updates options.

5 years agoproc_clean: add -quiet option.
whitequark [Tue, 9 Jul 2019 08:57:57 +0000 (08:57 +0000)]
proc_clean: add -quiet option.

This is useful for other passes that call it often, like bugpoint.

5 years agoDecompose mux inputs in delay-orientated (rather than area) fashion
Eddie Hung [Tue, 9 Jul 2019 06:51:13 +0000 (23:51 -0700)]
Decompose mux inputs in delay-orientated (rather than area) fashion

5 years agoDo not call opt -mux_undef (part of -full) before muxcover
Eddie Hung [Tue, 9 Jul 2019 06:49:16 +0000 (23:49 -0700)]
Do not call opt -mux_undef (part of -full) before muxcover

5 years agoAdd one more comment
Eddie Hung [Tue, 9 Jul 2019 06:05:48 +0000 (23:05 -0700)]
Add one more comment

5 years agoLess thinking
Eddie Hung [Tue, 9 Jul 2019 06:02:57 +0000 (23:02 -0700)]
Less thinking

5 years agoReword
Eddie Hung [Tue, 9 Jul 2019 05:56:19 +0000 (22:56 -0700)]
Reword

5 years agoMerge pull request #1166 from YosysHQ/eddie/synth_keepdc
Eddie Hung [Tue, 9 Jul 2019 04:43:16 +0000 (21:43 -0700)]
Merge pull request #1166 from YosysHQ/eddie/synth_keepdc

Add "synth -keepdc" option

5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Tue, 9 Jul 2019 02:26:43 +0000 (19:26 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agosynth_xilinx to call "synth -run coarse" with "-keepdc"
Eddie Hung [Tue, 9 Jul 2019 02:23:24 +0000 (19:23 -0700)]
synth_xilinx to call "synth -run coarse" with "-keepdc"

5 years agoMerge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux
Eddie Hung [Tue, 9 Jul 2019 02:21:53 +0000 (19:21 -0700)]
Merge remote-tracking branch 'origin/eddie/synth_keepdc' into xc7mux

5 years agoClarify script -scriptwire doc
Eddie Hung [Tue, 9 Jul 2019 02:21:21 +0000 (19:21 -0700)]
Clarify script -scriptwire doc

5 years agoAdd synth -keepdc to CHANGELOG
Eddie Hung [Tue, 9 Jul 2019 02:15:37 +0000 (19:15 -0700)]
Add synth -keepdc to CHANGELOG

5 years agoClarify 'wreduce -keepdc' doc
Eddie Hung [Tue, 9 Jul 2019 02:15:07 +0000 (19:15 -0700)]
Clarify 'wreduce -keepdc' doc

5 years agoAdd synth -keepdc option
Eddie Hung [Tue, 9 Jul 2019 02:14:54 +0000 (19:14 -0700)]
Add synth -keepdc option

5 years agoMap $__XILINX_SHIFTX in a more balanced manner
Eddie Hung [Tue, 9 Jul 2019 00:06:35 +0000 (17:06 -0700)]
Map $__XILINX_SHIFTX in a more balanced manner

5 years agoCapitalisation
Eddie Hung [Tue, 9 Jul 2019 00:06:22 +0000 (17:06 -0700)]
Capitalisation

5 years agoAdd synth_xilinx -widemux recommended value
Eddie Hung [Tue, 9 Jul 2019 00:04:39 +0000 (17:04 -0700)]
Add synth_xilinx -widemux recommended value

5 years agoMerge pull request #1164 from YosysHQ/eddie/muxcover_mux2
Eddie Hung [Mon, 8 Jul 2019 21:34:37 +0000 (14:34 -0700)]
Merge pull request #1164 from YosysHQ/eddie/muxcover_mux2

Add muxcover -mux2=cost option

5 years agoMerge pull request #1160 from ZirconiumX/cyclone_v
David Shah [Mon, 8 Jul 2019 20:04:33 +0000 (21:04 +0100)]
Merge pull request #1160 from ZirconiumX/cyclone_v

synth_intel: Warn about untested Quartus backend

5 years agoUpdate muxcover doc as per @ZirconiumX
Eddie Hung [Mon, 8 Jul 2019 19:50:59 +0000 (12:50 -0700)]
Update muxcover doc as per @ZirconiumX

5 years agoFixes for 2:1 muxes
Eddie Hung [Mon, 8 Jul 2019 19:03:38 +0000 (12:03 -0700)]
Fixes for 2:1 muxes

5 years agosynth_xilinx -widemux=2 is minimum now
Eddie Hung [Mon, 8 Jul 2019 18:29:21 +0000 (11:29 -0700)]
synth_xilinx -widemux=2 is minimum now

5 years agoParametric muxcover costs as per @daveshah1
Eddie Hung [Mon, 8 Jul 2019 18:08:20 +0000 (11:08 -0700)]
Parametric muxcover costs as per @daveshah1

5 years agoMerge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7mux
Eddie Hung [Mon, 8 Jul 2019 18:00:31 +0000 (11:00 -0700)]
Merge remote-tracking branch 'origin/eddie/muxcover_mux2' into xc7mux

5 years agoatoi -> stoi
Eddie Hung [Mon, 8 Jul 2019 18:00:06 +0000 (11:00 -0700)]
atoi -> stoi

5 years agoAdd muxcover -mux2=cost option
Eddie Hung [Mon, 8 Jul 2019 17:59:12 +0000 (10:59 -0700)]
Add muxcover -mux2=cost option

5 years agoatoi -> stoi as per @daveshah1
Eddie Hung [Mon, 8 Jul 2019 17:48:10 +0000 (10:48 -0700)]
atoi -> stoi as per @daveshah1

5 years agoMerge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Mon, 8 Jul 2019 17:46:08 +0000 (10:46 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux

5 years agoverilog_backend: dump attributes on SwitchRule.
whitequark [Mon, 8 Jul 2019 15:11:29 +0000 (15:11 +0000)]
verilog_backend: dump attributes on SwitchRule.

This appears to be an omission.

5 years agoproc_mux: consider \src attribute on CaseRule.
whitequark [Mon, 8 Jul 2019 13:18:18 +0000 (13:18 +0000)]
proc_mux: consider \src attribute on CaseRule.

5 years agoverilog_backend: dump attributes on CaseRule, as comments.
whitequark [Mon, 8 Jul 2019 12:48:50 +0000 (12:48 +0000)]
verilog_backend: dump attributes on CaseRule, as comments.

Attributes are not permitted in that position by Verilog grammar.

5 years agogenrtlil: emit \src attribute on CaseRule.
whitequark [Mon, 8 Jul 2019 12:29:08 +0000 (12:29 +0000)]
genrtlil: emit \src attribute on CaseRule.

5 years agoAllow attributes on individual switch cases in RTLIL.
whitequark [Mon, 8 Jul 2019 11:34:58 +0000 (11:34 +0000)]
Allow attributes on individual switch cases in RTLIL.

The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.

5 years agosynth_intel: Warn about untested Quartus backend
Dan Ravensloft [Sun, 7 Jul 2019 15:00:38 +0000 (16:00 +0100)]
synth_intel: Warn about untested Quartus backend

5 years agoMerge pull request #1159 from btut/fix/1090_segfault_cell_and_wire
Clifford Wolf [Fri, 5 Jul 2019 09:57:41 +0000 (11:57 +0200)]
Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire

Throw runtime exception when trying to convert inexistend C++ object to Python

5 years agoThrow runtime exception when trying to convert a c++-pointer to a
Benedikt Tutzer [Thu, 4 Jul 2019 12:20:13 +0000 (14:20 +0200)]
Throw runtime exception when trying to convert a c++-pointer to a
python-object in case the pointer is a nullptr to avoid a segfault.

Fixes #1090

5 years agoMerge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
Eddie Hung [Wed, 3 Jul 2019 16:43:00 +0000 (09:43 -0700)]
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell

 write_xaiger to treat unknown cell connections as keep-s

5 years agoMerge pull request #1147 from YosysHQ/clifford/fix1144
Clifford Wolf [Wed, 3 Jul 2019 10:30:37 +0000 (12:30 +0200)]
Merge pull request #1147 from YosysHQ/clifford/fix1144

Improve specify dummy parser

5 years agoFix tests/various/specify.v
Clifford Wolf [Wed, 3 Jul 2019 09:25:05 +0000 (11:25 +0200)]
Fix tests/various/specify.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoSome cleanups in "ignore specify parser"
Clifford Wolf [Wed, 3 Jul 2019 09:22:10 +0000 (11:22 +0200)]
Some cleanups in "ignore specify parser"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #1154 from whitequark/manual-sync-always
Clifford Wolf [Wed, 3 Jul 2019 08:45:29 +0000 (10:45 +0200)]
Merge pull request #1154 from whitequark/manual-sync-always

manual: explain the purpose of `sync always`

5 years agowrite_xaiger to treat unknown cell connections as keep-s
Eddie Hung [Wed, 3 Jul 2019 02:14:30 +0000 (19:14 -0700)]
write_xaiger to treat unknown cell connections as keep-s

5 years agoAdd test
Eddie Hung [Wed, 3 Jul 2019 02:13:40 +0000 (19:13 -0700)]
Add test

5 years agoMerge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Tue, 2 Jul 2019 19:35:45 +0000 (12:35 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_dff

5 years agoSafe side: all flops have different mergeability class
Eddie Hung [Tue, 2 Jul 2019 19:21:03 +0000 (12:21 -0700)]
Safe side: all flops have different mergeability class

5 years agoMerge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Tue, 2 Jul 2019 17:21:10 +0000 (10:21 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux

5 years agoMerge pull request #1150 from YosysHQ/eddie/script_from_wire
Eddie Hung [Tue, 2 Jul 2019 17:20:42 +0000 (10:20 -0700)]
Merge pull request #1150 from YosysHQ/eddie/script_from_wire

Add "script -select [selection]" to allow commands to be taken from wires

5 years agomanual: explain the purpose of `sync always`.
whitequark [Tue, 2 Jul 2019 17:10:13 +0000 (17:10 +0000)]
manual: explain the purpose of `sync always`.

5 years agoMerge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup
Eddie Hung [Tue, 2 Jul 2019 16:21:02 +0000 (09:21 -0700)]
Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup

5 years agoMerge remote-tracking branch 'origin/eddie/script_from_wire' into xc7mux
Eddie Hung [Tue, 2 Jul 2019 16:04:50 +0000 (09:04 -0700)]
Merge remote-tracking branch 'origin/eddie/script_from_wire' into xc7mux

5 years agoMerge pull request #1153 from YosysHQ/dave/fix_multi_mux
David Shah [Tue, 2 Jul 2019 15:47:54 +0000 (16:47 +0100)]
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux

memory_dff: Fix checking of feedback mux input when more than one mux

5 years agoUpdate test for Pass::call_on_module()
Eddie Hung [Tue, 2 Jul 2019 15:22:31 +0000 (08:22 -0700)]
Update test for Pass::call_on_module()

5 years agoUse Pass::call_on_module() as per @cliffordwolf comments
Eddie Hung [Tue, 2 Jul 2019 15:20:37 +0000 (08:20 -0700)]
Use Pass::call_on_module() as per @cliffordwolf comments

5 years agoUpdate test too
Eddie Hung [Tue, 2 Jul 2019 15:19:23 +0000 (08:19 -0700)]
Update test too