xmlconfig: read more config files from drirc.d/

Driver and application can put their drirc files in
${datadir}/drirc.d/ with name xxx.conf. Config files
will be read and applied in file name alphabetic order.

So there are three places for drirc listed in order:
1. /usr/share/drirc.d/
2. /etc/drirc
3. ~/.drirc

v4:
  fix meson build

v3:
  1. seperate driParseConfigFiles refine into another patch
  2. fix entries[i] mem leak

v2:
  drop /etc/drirc.d

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

xmlconfig: refine driParseConfigFiles to use parseOneConfigFile

Also prepare for the usage of following parseConfigDir patch.

Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: add #include <limits.h>]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

anv/pipeline: Lower pipeline layouts etc. after linking

This allows us to use the link-optimized shader for determining binding
table layouts and, more importantly, URB layouts.  For apps running on
DXVK, this is extremely important as DXVK likes to declare max-size
inputs and outputs and this lets is massively shrink our URB space
requirements.

VkPipeline-db results (Batman pipelines only) on KBL:

    total instructions in shared programs: 820403 -> 790008 (-3.70%)
    instructions in affected programs: 273759 -> 243364 (-11.10%)
    helped: 622
    HURT: 42

    total spills in shared programs: 8449 -> 5212 (-38.31%)
    spills in affected programs: 3427 -> 190 (-94.46%)
    helped: 607
    HURT: 2

    total fills in shared programs: 11638 -> 6067 (-47.87%)
    fills in affected programs: 5879 -> 308 (-94.76%)
    helped: 606
    HURT: 3

Looking at shaders by hand, it makes the URB between TCS and TES go from
containing 32 per-vertex varyings per tessellation shader pair to a more
reasonable 8-12.  For a 3-vertex patch, that's at least half the URB
space no matter how big the patch section is.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

anv/pipeline: Set tess IO read/written key fields in compile_*

We want these to be set as close to the final compile as possible so
that they are guaranteed to happen after nir_shader_gather_info is
called.  The next commit is going to move nir_shader_gather_info to
after the linking step which makes this necessary.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

anv/pipeline: Use more fields from stage in compile_cs

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/apply_pipeline_layout: Add to the bind map instead of replacing it

This commit makes three changes.  One is to only walk the descriptors once
and set bind map sizes at the same time as filling out the entries.  The
second is to make the pass additive so that we can put stuff in the bind
map before applying the pipeline layout.  Third, we switch to using
designated initializers.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv/lower_ycbcr: Use the binding array size for bounds checks

Because lower_ycbcr gets called before apply_pipeline_layout, the
indices are all logical and the binding layout HW size is actually too
big for the bounds check.  We should just use the regular logical array
size instead.

Fixes: f3e91e78a33 "anv: add nir lowering pass for ycbcr textures"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

python: Open the template as text, with an explicit encoding

In commit bd27203f4d808763ac24ac94eb677cacf3e7cb99 we changed this to
open in binary mode, to then explicitly decode the lines with the right
encoding.

Unfortunately, that broke the build on Windows, where the template file
can have '\r\n' as line terminators: opening in binary mode would keep
those terminators and break the regexp.

We need to go back to text mode, where the "universal newlines" mode
takes care of this.

However, to fix the initial issue, let's specify the encoding explicitly
when opening the file, and make sure it is open in text mode, so we only
get unicode strings.

Reviewed-by: Jose Fonseca <jfonseca@vmware>

python: Help Python 2 print the line

Reviewed-by: Jose Fonseca <jfonseca@vmware>

freedreno/a6xx: streamout

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: fragz fixes

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: scissor fixes

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: fix srgb

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: fix dEQP-GLES3.functional.fence_sync.*

Signed-off-by: Rob Clark <robdclark@gmail.com>

radv/winsys: fix creating the BO list for virtual buffers

When the number of unique BO is 0, we optimize the list creation
by copying all buffers of the current CS directly into it. But
this is only valid if the CS doesn't have virtual buffers,
otherwise they are not added and hw might report VM faults.

This fixes VM faults with:
dEQP-VK.sparse_resources.image_sparse_binding.2d.rgba8ui.1024_128_1

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

freedreno: Add a6xx backend

This adds a freedreno backend for the a6xx generation GPUs, which at
the time of this commit is about 98% GLES2 conformant. Much remains to
be done - both performance work and feature work towards more recent
GLES versions, but this is a good start.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

pull in a6xx registers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: Fix warnings

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

scons: Check for mako 0.8.0

v2: - Use distutils to do the version checking

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107565
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

scons: Require python 2.7

less than 2.7 is not supported.

v2: - Remove check for python >= 2.0, since we've already enforced 2.7

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

meson: use python3 module to find python3

This handy helper is nice for OSes that are not linux or BSD like (mac
and windows) as it knows how to find python3 in odd places.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

meson: Ensure that mako is >= 0.8.0

It's what autotools has required for a long time.

v3: - Use distutils.version.StrictVersion instead of comparing strings

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

svga: simplify Mesa version string

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

bin: always define MESA_GIT_SHA1 to make it directly usable in code

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

git_sha1: simplify logic

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

i965: drop unused assignment

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: drop cast-to-void of used variable

`device` is used 2 lines below, even visible in the diff context printed.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

anv: use safer snprintf() to ensure NULL string-terminator

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/batch-decoder: replace local ARRAY_LENGTH() macro with global ARRAY_SIZE()

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel: various python cleanups

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: check for buffer overflow *before* corrupting our memory

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl/wayland: remove sign from bitfield `formats`

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mailmap: add various typos of Emil's address from the log

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: some spelling fixes

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

radv: initialize the DCC predicate correctly when it's compressed

We have to do a fast-clear eliminate when clearing DCC
metadata with 0x20202020. I don't know if that fixes anything
but that seems correct to me.

CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix missing initialization of the conditional rendering state

This was missing when VK_EXT_conditional_rendering has been
implemented. The predication type should be -1 to avoid
restoring previous state when performing a decompression pass
with DCC enabled.

Note that we don't have to handle secondary command buffers
because we don't support this feature currently.

CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

bin: split `write_if_different()` out

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

bin: whitespace cleanup

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

radv: Revert divisor = 0 case for vertex attribute extension.

Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.

Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to version 2."
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Possible on-demand compilation fix.

Seems that in a single case we use the renderpass before checking
the pipeline, so check the renderpass before we use it.

Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/st: fix array indices off-by-one error in remapping

When moving the array sizes from the old list to the new one it was
not taken into account that the array indices start with one, but the
array_size array started at index zero, which resulted in incorrect array
sizes when arrays were merged. Correct this by copying the array_size
values of the retained arrays with an offset of -1.

Also fix whitespaces for the replaced lines.

Fixes: d8c2119f9b0b257a23ceb398f6d0d78da916417e
  mesa/st/glsl_to_tgsi: Expose array live range tracking and merging
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

meson: fix build for egl platform_x11 without dri3 and gbm

Compiling EGL's platform_x11 without dri3 and gbm yields this compile
failure:

platform_x11 needs inc_loader:

../mesa-18.2.0-rc2/src/egl/drivers/dri2/platform_x11.c:48:10: fatal
error: loader.h: No such file or directory
 #include "loader.h"
          ^~~~~~~~~~

Fixes: 108d257a1685 ("meson: build libEGL")
Bugzilla: https://bugs.gentoo.org/663534
Reviewed-by: Matt Turner <mattst88@gmail.com>

Revert "intel/nir: Call nir_lower_io_to_scalar_early"

Commit 4434591bf56a6b0 caused substantially more URB messages in
geometry and tessellation shaders.  Before we can really enable this
sort of optimization,  We either need some way of combining them back
together into vectors or we need to do cross-stage vector element
elimination without splitting everything into scalars.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107510
Fixes: 4434591bf56a6 "intel/nir: Call nir_lower_io_to_scalar_early"
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>

i965: do not emit empty surface state

If called with an empty size, brw_emit_buffer_surface_state asserts.
We already have a dedicated helper for uploading nothing, so let's use
that instead.

Avoids an assert in
dEQP-GLES31.functional.shaders.opaque_type_indexing.ssbo.const_literal_vertex
when running a debug build of i965.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/ppgtt: 4096 replaced by PAGE_SIZE

Usage of number 4096 replaced by PAGE_SIZE.

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/ppgtt: memory address alignment

Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).

-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved to separate commit
-v5: restored alignment to page-size for 0-size.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to brw_bufmgr.)
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

radv: add Doom workaround

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Emitting 3DSTATE_SO_BUFFER of 0-size.

Avoided filling of whole structure and bo-allocation if
size of surface is 0.

Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>

virgl: report actual max-texture sizes

Instead of doing conservative guesses, we should report the max levels
based on the max sizes we get from GL on the host.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>

virgl: do not use SP_MAX_TEXTURE_*_LEVELS defines

These macro-names are also used for softpipe, so let's avoid confusion
by avoiding them. Besides, they are just used in one place in virgl, so
let's just inline them into the place they are used instead.

While we're at it, fixup an error in the comment for the 3D version.
Mesa subtracts computes max-size by doing by 2^(n-1), which means this
should be 256 cubed, not 512 cubed. The other comments are correct.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jakob Bornecrantz <jakob@collabora.com>

docs: Add news item for 18.1.6

radv: disable the auto-waitcnt-before-barrier LLVM option

This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.

Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix memory leaks in radv_load_meta_pipeline()

Reported by Coverity.

Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS

The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.

COMPUTE_RESOURCE_LIMITS is correctly set when generating
compute pipelines, so we don't need to initialize it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

docs: update calendar 18.2.0-rc3 is out

Signed-off-by: Andres Gomez <agomez@igalia.com>

radv/meta_decompress: fix pointer to integer conversion

VK_NULL_HANDLE replaces NULL to avoid following building error:

external/mesa/src/amd/vulkan/radv_meta_decompress.c:365:54: error:
incompatible pointer to integer conversion passing 'void *' to parameter
of type 'VkShaderModule' (aka 'unsigned long long') [-Werror,-Wint-conversion]
                VkResult ret = create_pipeline(cmd_buffer->device, NULL, samples,
                                                                   ^~~~
prebuilts/clang/host/linux-x86/clang-4053586/lib64/clang/5.0.300080/include/stddef.h:105:16:
note: expanded from macro 'NULL'
#  define NULL ((void*)0)
               ^~~~~~~~~~
external/mesa/src/amd/vulkan/radv_meta_decompress.c:97:32:
note: passing argument to parameter 'vs_module_h' here
                VkShaderModule vs_module_h,
                               ^
1 error generated.

Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

egl/android: fix regression in drm_gralloc path (v2)

This patch fixes a regression in mesa 18.2 and mesa-dev branches
for HAVE_DRM_GRALLOC code path which is causing black screen on Android
and prevents boot due to SIGSEGV MAPERR crash related to unproper handling
of drm_gralloc drm FD in new droid_open_device() path.

Problem is due to c7bb82136b ("egl/android: Add DRM node probing and filtering")

To avoid the crash the former existing working droid_open_device() is restored,
renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC braces.

Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation
and Androdi GUI booting is fixed with i965, nouveau, radeon.
The changes are compatible with gbm_gralloc, I've tested build with hwc too.

(v2) remove indentation from HAVE_DRM_GRALLOC pre-processor directive

NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD
is not necessary and it's actually causing a redefinition building error,
because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported
by libgralloc_drm which is currently still a dependency.

Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering")
Cc: "18.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>

mesa: shader dump/read support for ARB programs

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106283
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

glsl: Avoid calling get_array_element for scalar constants

Accessing scalar constant as an array in function call or
initializer list triggered assert in get_array_element.
Examples:
   func(0[0]);
   vec2 t = { 0[0], 0 };

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107550

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

radeonsi: enable 1 missing PS_SU perf counter on Polaris

radeonsi: use radeon_info::name

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

ac: add radeon_info::name

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: split si_clear_buffer to remove enum si_method

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: replace CP_DMA_USE_L2 with enum si_cache_policy

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: declare coher in si_copy_buffer

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: make PFP_SYNC_ME an explicit CP DMA flag

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: don't use emit_data->args in load_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: don't use emit_data->args in store_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: don't use emit_data->args in atomic_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: don't use emit_data->args in build_interp_intrinsic

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: inline atomic_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: inline store_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: inline load_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: merge txq_emit and resq_emit

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: inline resq_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: inline txq_fetch_args

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: use get_resinfo directly in lower_gather4_integer

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: inline tex_fetch_args into build_tex_intrinsic

The diff looks like it moves code that I didn't touch.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: remove fetch_args callbacks for ALU instructions

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.c

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: implement EXT_window_rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium/u_blitter: save/restore window rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

noop: implement set_window_rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ddebug: implement set_window_rectangles

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Add a new CFL PCI ID.

One more CFL ID added to spec.

Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

freedreno/ir3: add support for a6xx 'merged' register set

Starting with a6xx, half and full precision registers conflict.  Which
makes things a bit more efficient, ie. if some parts of the shader are
heavy on half-precision and others on full precision, you don't have to
allocate the worst case for both.  But it means we need to setup some
additional conflicts.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: small RA cleanup

Collapse is_temp() into it's only callsite, and pass compiler object as
struct rather than void.  Just cleanups to reduce noise in next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: stop hard-coding FS input regs

We originally did this because at the time we didn't know all the
bitfields to configure where various frag shader sysval's went.  But
we do.

So switch to using sysvals for all the frag shader inputs.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: use r63.x for unused inputs

This way, unused sysval inputs, like frag_vcoord, get the correct regid
value to disable the input.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: create all inputs in first block

create_input()/create_input_compmask() should take the ctx as arg,
rather than block, to enforce that all inputs are created in the first
block, so that RA sees them as live at the start of the shader.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: rename s/frag_pos/frag_vcoord/g

Make it more clear that this is varying fetch related.  Also fixup some
comments.  Just cleanup for next patches.

Signed-off-by: Rob Clark <robdclark@gmail.com>

compiler: add SYSTEM_VALUE_VARYING_COORD

Used internally in freedreno/ir3 for the vec2 value that hw passes to
shader to use as coordinate for bary.f (varying fetch) instruction.
This is not the same as SYSTEM_VALUE_FRAG_COORD.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: move per-generation compiler config

Move it from the compile ctx to the compiler object, before adding
new things for a6xx.

Signed-off-by: Rob Clark <robdclark@gmail.com>

radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.

Behavior wrt firstInstance got changed, and a divisor of 0 has been
disallowed.

The new version of the ext got published in specification 1.1.81.

Sending to stable since the only known user is DXVK, which needs
this for correctness.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: 18.2 <mesa-stable@lists.freedesktop.org>

radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.

Follow radeonsi.

Fixes: 3665f66ef26 "radv: Add support for ETC2 textures."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Fix missing Android platform define.

CC: <mesa-stable@lists.freedesktop.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

freedreno: move free() into fdN_context_destroy()

Following patches will be doing further cleanup after calling
fd_context_destroy() so it is easier if we move the free() into
the per-gen backend code.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: a2xx: ir2 update

this patch brings a number of changes to ir2:
-ir2 now generates CF clauses as necessary during assembly. this simplifies
 fd2_program/fd2_compiler and is necessary to implement optimization passes
-ir2 now has separate vector/scalar instructions. this will make it easier
 to implementing scheduling of scalar+vector instructions together. dst_reg
 is also now seperate from src registers instead of a single list
-ir2 now implements register allocation. this makes it possible to compile
 shaders which have more than 64 TGSI registers
-ir2 now implements the following optimizations: removal of IN/OUT MOV
 instructions generated by TGSI and removal of unused instructions when
 some exports are disabled
-ir2 now allows full 8-bit index for constants
-ir2_alloc no longer allocates 4 times too many bytes

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>

docs: update calendar 18.2.0-rc1 and 18.2.0-rc2 are out

Signed-off-by: Andres Gomez <agomez@igalia.com>