yosys.git
5 years agoFix a syntax bug in ilang backend related to process case statements
Clifford Wolf [Thu, 14 Mar 2019 16:50:20 +0000 (17:50 +0100)]
Fix a syntax bug in ilang backend related to process case statements

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #869 from cr1901/win-shell
Clifford Wolf [Thu, 14 Mar 2019 15:43:23 +0000 (16:43 +0100)]
Merge pull request #869 from cr1901/win-shell

Install launcher executable when running yosys-smtbmc on Windows.

5 years agoInstall launcher executable when running yosys-smtbmc on Windows.
William D. Jones [Tue, 12 Mar 2019 21:55:47 +0000 (17:55 -0400)]
Install launcher executable when running yosys-smtbmc on Windows.

Signed-off-by: William D. Jones <thor0505@comcast.net>
5 years agoMerge pull request #868 from YosysHQ/clifford/fixmem
Clifford Wolf [Wed, 13 Mar 2019 12:40:30 +0000 (13:40 +0100)]
Merge pull request #868 from YosysHQ/clifford/fixmem

Various mem2reg-related improvements in handling of memories

5 years agoFix a bug in handling quotes in multi-cmd lines in Yosys scripts
Clifford Wolf [Tue, 12 Mar 2019 20:14:50 +0000 (21:14 +0100)]
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #866 from YosysHQ/clifford/idstuff
Clifford Wolf [Tue, 12 Mar 2019 19:27:36 +0000 (20:27 +0100)]
Merge pull request #866 from YosysHQ/clifford/idstuff

Improve determinism of IdString DB for similar scripts

5 years agoRemove ice40/cells_sim.v hack to avoid warning for blocking memory writes
Clifford Wolf [Tue, 12 Mar 2019 19:14:18 +0000 (20:14 +0100)]
Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove handling of memories used in mem index expressions on LHS of an assignment
Clifford Wolf [Tue, 12 Mar 2019 19:12:02 +0000 (20:12 +0100)]
Improve handling of memories used in mem index expressions on LHS of an assignment

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRemove outdated "blocking assignment to memory" warning
Clifford Wolf [Tue, 12 Mar 2019 19:10:55 +0000 (20:10 +0100)]
Remove outdated "blocking assignment to memory" warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoOnly set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
Clifford Wolf [Tue, 12 Mar 2019 19:09:47 +0000 (20:09 +0100)]
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove determinism of IdString DB for similar scripts
Clifford Wolf [Mon, 11 Mar 2019 19:12:28 +0000 (20:12 +0100)]
Improve determinism of IdString DB for similar scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #864 from YosysHQ/svalabelfix
Eddie Hung [Mon, 11 Mar 2019 18:58:07 +0000 (11:58 -0700)]
Merge pull request #864 from YosysHQ/svalabelfix

Fix handling of cases that look like sva labels, fixes #862

5 years agoAdd ENABLE_GLOB Makefile switch
Clifford Wolf [Mon, 11 Mar 2019 08:08:36 +0000 (01:08 -0700)]
Add ENABLE_GLOB Makefile switch

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix handling of cases that look like sva labels, fixes #862
Clifford Wolf [Sun, 10 Mar 2019 23:27:18 +0000 (16:27 -0700)]
Fix handling of cases that look like sva labels, fixes #862

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix typo in ice40_braminit help msg
Clifford Wolf [Sat, 9 Mar 2019 21:24:55 +0000 (13:24 -0800)]
Fix typo in ice40_braminit help msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #859 from smunaut/ice40_braminit
Clifford Wolf [Sat, 9 Mar 2019 21:24:10 +0000 (13:24 -0800)]
Merge pull request #859 from smunaut/ice40_braminit

iCE40 BRAM primitives init from file

5 years agoFix signed $shift/$shiftx handling in write_smt2
Clifford Wolf [Sat, 9 Mar 2019 21:19:41 +0000 (13:19 -0800)]
Fix signed $shift/$shiftx handling in write_smt2

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd $dffsr support to async2sync
Clifford Wolf [Sat, 9 Mar 2019 19:52:00 +0000 (11:52 -0800)]
Add $dffsr support to async2sync

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #858 from YosysHQ/clifford/svalabels
Clifford Wolf [Sat, 9 Mar 2019 19:14:57 +0000 (11:14 -0800)]
Merge pull request #858 from YosysHQ/clifford/svalabels

Add support for using SVA labels in yosys-smtbmc console output

5 years agoMerge pull request #861 from YosysHQ/verific_chparam
Clifford Wolf [Sat, 9 Mar 2019 07:02:56 +0000 (23:02 -0800)]
Merge pull request #861 from YosysHQ/verific_chparam

Add -chparam option to verific command

5 years agoAlso add support for labels on sva module items, fixes #699
Clifford Wolf [Sat, 9 Mar 2019 06:53:58 +0000 (22:53 -0800)]
Also add support for labels on sva module items, fixes #699

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUpdate help message for -chparam
Eddie Hung [Sat, 9 Mar 2019 01:56:16 +0000 (01:56 +0000)]
Update help message for -chparam

5 years agoAdd -chparam option to verific command
Eddie Hung [Sat, 9 Mar 2019 01:54:01 +0000 (01:54 +0000)]
Add -chparam option to verific command

5 years agoFix spelling
Eddie Hung [Sat, 9 Mar 2019 00:43:50 +0000 (00:43 +0000)]
Fix spelling

5 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Fri, 8 Mar 2019 06:44:50 +0000 (22:44 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys

5 years agoFix handling of task output ports in clocked always blocks, fixes #857
Clifford Wolf [Fri, 8 Mar 2019 06:44:37 +0000 (22:44 -0800)]
Fix handling of task output ports in clocked always blocks, fixes #857

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoice40: Run ice40_braminit pass by default
Sylvain Munaut [Thu, 7 Mar 2019 23:11:17 +0000 (00:11 +0100)]
ice40: Run ice40_braminit pass by default

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
5 years agoice40: Add ice40_braminit pass to allow initialization of BRAM from file
Sylvain Munaut [Thu, 7 Mar 2019 22:48:10 +0000 (23:48 +0100)]
ice40: Add ice40_braminit pass to allow initialization of BRAM from file

This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
5 years agoMerge pull request #856 from kprasadvnsi/master
Clifford Wolf [Thu, 7 Mar 2019 19:34:12 +0000 (11:34 -0800)]
Merge pull request #856 from kprasadvnsi/master

examples/anlogic/ now also output the SVF file.

5 years agoUse SVA label in smt export if available
Clifford Wolf [Thu, 7 Mar 2019 19:31:46 +0000 (11:31 -0800)]
Use SVA label in smt export if available

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd support for SVA labels in read_verilog
Clifford Wolf [Thu, 7 Mar 2019 19:17:32 +0000 (11:17 -0800)]
Add support for SVA labels in read_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd hack for handling SVA labels via Verific
Clifford Wolf [Thu, 7 Mar 2019 18:52:44 +0000 (10:52 -0800)]
Add hack for handling SVA labels via Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd link to SF2 / igloo2 macro library guide
Clifford Wolf [Thu, 7 Mar 2019 17:08:26 +0000 (09:08 -0800)]
Add link to SF2 / igloo2 macro library guide

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprovements in sf2 cells_sim.v
Clifford Wolf [Thu, 7 Mar 2019 00:18:49 +0000 (16:18 -0800)]
Improvements in sf2 cells_sim.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd sf2 techmap rules for more FF types
Clifford Wolf [Wed, 6 Mar 2019 23:47:54 +0000 (15:47 -0800)]
Add sf2 techmap rules for more FF types

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoRefactor SF2 iobuf insertion, Add clkint insertion
Clifford Wolf [Wed, 6 Mar 2019 08:41:02 +0000 (00:41 -0800)]
Refactor SF2 iobuf insertion, Add clkint insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove igloo2 example
Clifford Wolf [Wed, 6 Mar 2019 04:47:07 +0000 (20:47 -0800)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove igloo2 example
Clifford Wolf [Wed, 6 Mar 2019 04:35:48 +0000 (20:35 -0800)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprovements in SF2 flow and demo
Clifford Wolf [Wed, 6 Mar 2019 03:49:39 +0000 (19:49 -0800)]
Improvements in SF2 flow and demo

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoexamples/anlogic/ now also output the SVF file.
Kali Prasad [Wed, 6 Mar 2019 04:21:11 +0000 (09:51 +0530)]
examples/anlogic/ now also output the SVF file.

5 years agoFix spelling in pmgen/README.md
Eddie Hung [Wed, 6 Mar 2019 01:55:29 +0000 (17:55 -0800)]
Fix spelling in pmgen/README.md

5 years agoImprove igloo2 exmaple
Clifford Wolf [Wed, 6 Mar 2019 01:27:58 +0000 (17:27 -0800)]
Improve igloo2 exmaple

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #842 from litghost/merge_upstream
Clifford Wolf [Tue, 5 Mar 2019 23:33:19 +0000 (15:33 -0800)]
Merge pull request #842 from litghost/merge_upstream

Changes required for VPR place and route in synth_xilinx

5 years agoMerge pull request #850 from daveshah1/ecp5_warn_conflict
Clifford Wolf [Tue, 5 Mar 2019 23:23:01 +0000 (15:23 -0800)]
Merge pull request #850 from daveshah1/ecp5_warn_conflict

ecp5: Demote conflicting FF init values to a warning

5 years agoAdd missing newline
Clifford Wolf [Tue, 5 Mar 2019 23:21:04 +0000 (15:21 -0800)]
Add missing newline

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #851 from kprasadvnsi/master
Clifford Wolf [Tue, 5 Mar 2019 23:20:03 +0000 (15:20 -0800)]
Merge pull request #851 from kprasadvnsi/master

Added examples/anlogic/

5 years agoMerge pull request #852 from ucb-bar/firrtlfixes
Clifford Wolf [Tue, 5 Mar 2019 23:19:28 +0000 (15:19 -0800)]
Merge pull request #852 from ucb-bar/firrtlfixes

Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails

5 years agoUse "write_edif -pvector bra" for Xilinx EDIF files
Clifford Wolf [Tue, 5 Mar 2019 23:16:13 +0000 (15:16 -0800)]
Use "write_edif -pvector bra" for Xilinx EDIF files

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoEnsure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Jim Lawson [Mon, 4 Mar 2019 21:23:58 +0000 (13:23 -0800)]
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".

5 years agoAdded examples/anlogic/
Kali Prasad [Mon, 4 Mar 2019 17:56:56 +0000 (23:26 +0530)]
Added examples/anlogic/

5 years agoRevert BRAM WRITE_MODE changes.
Keith Rothman [Mon, 4 Mar 2019 17:22:22 +0000 (09:22 -0800)]
Revert BRAM WRITE_MODE changes.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoecp5: Demote conflicting FF init values to a warning
David Shah [Mon, 4 Mar 2019 11:18:53 +0000 (11:18 +0000)]
ecp5: Demote conflicting FF init values to a warning

Signed-off-by: David Shah <dave@ds0.me>
5 years agoImprove igloo2 example
Clifford Wolf [Mon, 4 Mar 2019 07:54:35 +0000 (23:54 -0800)]
Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUpdate igloo2 example to Libero v12.0
Clifford Wolf [Mon, 4 Mar 2019 05:35:57 +0000 (21:35 -0800)]
Update igloo2 example to Libero v12.0

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #848 from YosysHQ/clifford/fix763
Clifford Wolf [Sun, 3 Mar 2019 00:32:58 +0000 (16:32 -0800)]
Merge pull request #848 from YosysHQ/clifford/fix763

Fix error for wire decl in always block, fixes 763

5 years agoMerge pull request #849 from YosysHQ/clifford/dynports
Clifford Wolf [Sun, 3 Mar 2019 00:01:31 +0000 (16:01 -0800)]
Merge pull request #849 from YosysHQ/clifford/dynports

Only run derive on blackbox modules when ports have dynamic size

5 years agoOnly run derive on blackbox modules when ports have dynamic size
Clifford Wolf [Sat, 2 Mar 2019 20:36:46 +0000 (12:36 -0800)]
Only run derive on blackbox modules when ports have dynamic size

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix error for wire decl in always block, fixes #763
Clifford Wolf [Sat, 2 Mar 2019 19:40:57 +0000 (11:40 -0800)]
Fix error for wire decl in always block, fixes #763

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix $global_clock handling vs autowire
Clifford Wolf [Sat, 2 Mar 2019 18:38:13 +0000 (10:38 -0800)]
Fix $global_clock handling vs autowire

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #847 from YosysHQ/clifford/fix785
Clifford Wolf [Sat, 2 Mar 2019 18:27:58 +0000 (10:27 -0800)]
Merge pull request #847 from YosysHQ/clifford/fix785

Fix $readmem[hb] for mem2reg memories, fixes #785

5 years agoFix $readmem[hb] for mem2reg memories, fixes #785
Clifford Wolf [Sat, 2 Mar 2019 17:58:20 +0000 (09:58 -0800)]
Fix $readmem[hb] for mem2reg memories, fixes #785

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #843 from YosysHQ/clifford/mem2regconstidx
Clifford Wolf [Sat, 2 Mar 2019 16:40:54 +0000 (08:40 -0800)]
Merge pull request #843 from YosysHQ/clifford/mem2regconstidx

Use mem2reg on memories that only have constant-index write ports

5 years agoMerge pull request #845 from YosysHQ/clifford/travisnomacos
Clifford Wolf [Sat, 2 Mar 2019 16:40:17 +0000 (08:40 -0800)]
Merge pull request #845 from YosysHQ/clifford/travisnomacos

Disable macOS builds in Travis

5 years agoDisable macOS builds in Travis
Clifford Wolf [Sat, 2 Mar 2019 16:29:28 +0000 (08:29 -0800)]
Disable macOS builds in Travis

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoTry again for passes/pmgen/ice40_dsp_pm.h rule
Larry Doolittle [Sat, 2 Mar 2019 04:15:20 +0000 (20:15 -0800)]
Try again for passes/pmgen/ice40_dsp_pm.h rule

Tested on both in-tree and out-of-tree builds

5 years agoRevert FF models to include IS_x_INVERTED parameters.
Keith Rothman [Fri, 1 Mar 2019 22:41:21 +0000 (14:41 -0800)]
Revert FF models to include IS_x_INVERTED parameters.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoUse singular for disabling of DRAM or BRAM inference.
Keith Rothman [Fri, 1 Mar 2019 22:35:14 +0000 (14:35 -0800)]
Use singular for disabling of DRAM or BRAM inference.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoMinor improvements in README
Clifford Wolf [Fri, 1 Mar 2019 22:29:17 +0000 (14:29 -0800)]
Minor improvements in README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoUse mem2reg on memories that only have constant-index write ports
Clifford Wolf [Fri, 1 Mar 2019 21:35:09 +0000 (13:35 -0800)]
Use mem2reg on memories that only have constant-index write ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoFix "write_edif -gndvccy"
Clifford Wolf [Fri, 1 Mar 2019 20:59:07 +0000 (12:59 -0800)]
Fix "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoModify arguments to match existing style.
Keith Rothman [Fri, 1 Mar 2019 20:14:27 +0000 (12:14 -0800)]
Modify arguments to match existing style.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoChanges required for VPR place and route synth_xilinx.
Keith Rothman [Fri, 1 Mar 2019 19:21:07 +0000 (11:21 -0800)]
Changes required for VPR place and route synth_xilinx.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoMerge pull request #841 from mmicko/master
Clifford Wolf [Fri, 1 Mar 2019 18:53:23 +0000 (10:53 -0800)]
Merge pull request #841 from mmicko/master

Fix ECP5 cells_sim for iverilog

5 years agoFix ECP5 cells_sim for iverilog
Miodrag Milanovic [Fri, 1 Mar 2019 18:25:23 +0000 (19:25 +0100)]
Fix ECP5 cells_sim for iverilog

5 years agoImprove "read" error msg
Clifford Wolf [Fri, 1 Mar 2019 04:34:42 +0000 (20:34 -0800)]
Improve "read" error msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
Clifford Wolf [Fri, 1 Mar 2019 04:27:27 +0000 (20:27 -0800)]
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

5 years agoHotfix for "make test"
Clifford Wolf [Fri, 1 Mar 2019 04:26:54 +0000 (20:26 -0800)]
Hotfix for "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #837 from YosysHQ/clifford/fix835
Clifford Wolf [Fri, 1 Mar 2019 01:40:38 +0000 (17:40 -0800)]
Merge pull request #837 from YosysHQ/clifford/fix835

Fix multiple issues in wreduce FF handling, fixes #835

5 years agoFix multiple issues in wreduce FF handling, fixes #835
Clifford Wolf [Fri, 1 Mar 2019 01:24:46 +0000 (17:24 -0800)]
Fix multiple issues in wreduce FF handling, fixes #835

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoice40: use 2 bits for READ/WRITE MODE for SB_RAM map
Elms [Fri, 1 Mar 2019 00:22:24 +0000 (16:22 -0800)]
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>
5 years agoMerge pull request #834 from YosysHQ/clifford/siminit
Clifford Wolf [Thu, 28 Feb 2019 23:03:55 +0000 (15:03 -0800)]
Merge pull request #834 from YosysHQ/clifford/siminit

Add "write_verilog -siminit"

5 years agoAdd "write_verilog -siminit"
Clifford Wolf [Thu, 28 Feb 2019 22:56:55 +0000 (14:56 -0800)]
Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoReduce amount of trailing whitespace in code base
Larry Doolittle [Tue, 26 Feb 2019 18:28:42 +0000 (10:28 -0800)]
Reduce amount of trailing whitespace in code base

5 years agoFix pmgen for in-tree builds
Clifford Wolf [Thu, 28 Feb 2019 22:56:05 +0000 (14:56 -0800)]
Fix pmgen for in-tree builds

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #794 from daveshah1/ecp5improve
Clifford Wolf [Thu, 28 Feb 2019 22:46:56 +0000 (14:46 -0800)]
Merge pull request #794 from daveshah1/ecp5improve

ECP5 Improvements

5 years agoMerge pull request #827 from ucb-bar/firrtlfixes
Clifford Wolf [Thu, 28 Feb 2019 22:45:04 +0000 (14:45 -0800)]
Merge pull request #827 from ucb-bar/firrtlfixes

Fix FIRRTL to Verilog process instance subfield assignment.

5 years agoFix pmgen for out-of-tree build
Clifford Wolf [Thu, 28 Feb 2019 22:00:58 +0000 (14:00 -0800)]
Fix pmgen for out-of-tree build

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #833 from YosysHQ/clifford/fix831
Clifford Wolf [Thu, 28 Feb 2019 21:40:27 +0000 (13:40 -0800)]
Merge pull request #833 from YosysHQ/clifford/fix831

Fix smt2 code generation for partially initialized memory words, fixe…

5 years agoFix smt2 code generation for partially initialized memowy words, fixes #831
Clifford Wolf [Thu, 28 Feb 2019 20:15:58 +0000 (12:15 -0800)]
Fix smt2 code generation for partially initialized memowy words, fixes #831

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #832 from YosysHQ/supercover
Clifford Wolf [Thu, 28 Feb 2019 20:08:01 +0000 (12:08 -0800)]
Merge pull request #832 from YosysHQ/supercover

Add "supercover" pass

5 years agoImprovements in "supercover" pass
Clifford Wolf [Wed, 27 Feb 2019 19:45:13 +0000 (11:45 -0800)]
Improvements in "supercover" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "supercover" skeleton
Clifford Wolf [Wed, 27 Feb 2019 19:37:08 +0000 (11:37 -0800)]
Add "supercover" skeleton

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agotechlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
Larry Doolittle [Mon, 25 Feb 2019 06:09:54 +0000 (22:09 -0800)]
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module

5 years agoClean up some whitepsace outliers
Larry Doolittle [Mon, 25 Feb 2019 06:08:52 +0000 (22:08 -0800)]
Clean up some whitepsace outliers

5 years agoFix FIRRTL to Verilog process instance subfield assignment.
Jim Lawson [Tue, 26 Feb 2019 00:18:13 +0000 (16:18 -0800)]
Fix FIRRTL to Verilog process instance subfield assignment.
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)

5 years agoecp5: Compatibility with Migen AsyncResetSynchronizer
David Shah [Tue, 19 Feb 2019 19:35:10 +0000 (19:35 +0000)]
ecp5: Compatibility with Migen AsyncResetSynchronizer

Signed-off-by: David Shah <davey1576@gmail.com>
5 years agoMinor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check
Clifford Wolf [Sun, 24 Feb 2019 19:41:36 +0000 (20:41 +0100)]
Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #812 from ucb-bar/arrayhierarchyfixes
Clifford Wolf [Sun, 24 Feb 2019 19:39:13 +0000 (11:39 -0800)]
Merge pull request #812 from ucb-bar/arrayhierarchyfixes

Define basic_cell_type() function and use it to derive the cell type …

5 years agoCleanups in ARST handling in wreduce
Clifford Wolf [Sun, 24 Feb 2019 19:34:23 +0000 (20:34 +0100)]
Cleanups in ARST handling in wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #824 from litghost/fix_reduce_on_ff
Clifford Wolf [Sun, 24 Feb 2019 19:29:14 +0000 (11:29 -0800)]
Merge pull request #824 from litghost/fix_reduce_on_ff

Fix WREDUCE on FF not fixing ARST_VALUE parameter.