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Luke Kenneth Casson Leighton [Sat, 11 Sep 2021 14:37:46 +0000 (15:37 +0100)]
update README.txt to add extra notes
Luke Kenneth Casson Leighton [Thu, 10 Jun 2021 15:46:52 +0000 (16:46 +0100)]
whoops spimaster (mspi0) not connected up
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 19:07:51 +0000 (20:07 +0100)]
doh, supposed to subtract 16 not throw the calculation away
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 15:50:54 +0000 (16:50 +0100)]
sort out PLL connection, in and out of peripheral interconnect
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:50:19 +0000 (14:50 +0100)]
try setting domain to "CPU"
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:46:29 +0000 (14:46 +0100)]
try setting actual clk to pllclk_o
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:42:41 +0000 (14:42 +0100)]
add PLL clock loop-back into CPU
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:41:10 +0000 (14:41 +0100)]
add PLL clock loop-back into CPU
Luke Kenneth Casson Leighton [Wed, 9 Jun 2021 13:20:16 +0000 (14:20 +0100)]
remove 16 NC, added 16 VCC/VDD
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:45:41 +0000 (15:45 +0100)]
syntax error in pll.v
Luke Kenneth Casson Leighton [Thu, 3 Jun 2021 14:43:21 +0000 (15:43 +0100)]
dummy PLL added with bypass, rename ref to ref_v due to ref being keyword
Luke Kenneth Casson Leighton [Wed, 26 May 2021 14:04:23 +0000 (15:04 +0100)]
remove wb err signal from sram4k
Luke Kenneth Casson Leighton [Tue, 25 May 2021 11:44:57 +0000 (12:44 +0100)]
increase not-connected pins in ls180
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:58:15 +0000 (12:58 +0100)]
match up PLL names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:54:54 +0000 (12:54 +0100)]
match up PLL names
Luke Kenneth Casson Leighton [Sat, 22 May 2021 11:27:17 +0000 (12:27 +0100)]
rename vco_test_ana to pll_testout_o
Luke Kenneth Casson Leighton [Sat, 22 May 2021 10:48:31 +0000 (11:48 +0100)]
reduce nc pins by 5 for PLL
Luke Kenneth Casson Leighton [Sun, 9 May 2021 14:41:33 +0000 (15:41 +0100)]
code-comments about ls180 imports
Luke Kenneth Casson Leighton [Mon, 3 May 2021 12:00:10 +0000 (13:00 +0100)]
must only try to connect jtag when variant requests it
Luke Kenneth Casson Leighton [Mon, 3 May 2021 11:58:49 +0000 (12:58 +0100)]
comment that variant for debug must be --variant=standard
Luke Kenneth Casson Leighton [Thu, 22 Apr 2021 00:43:51 +0000 (01:43 +0100)]
comments on DMI interface
Luke Kenneth Casson Leighton [Tue, 20 Apr 2021 11:52:15 +0000 (12:52 +0100)]
code-comments for sim.py debug mode
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:39:25 +0000 (21:39 +0100)]
sort out names
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:18:31 +0000 (21:18 +0100)]
rename spblock_512 4k sram module to lowercase
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:16:09 +0000 (21:16 +0100)]
whoops clk_sel_i renamed accidentally
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 20:05:42 +0000 (21:05 +0100)]
rename PLL pins to match LIP6.fr PLL
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 16:51:01 +0000 (17:51 +0100)]
rename XICS memmap regions
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 16:51:19 +0000 (17:51 +0100)]
add SPBlock_512W64B8W.v to sources
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 15:42:22 +0000 (16:42 +0100)]
put imports into conditional blocks. makes core.py "safe" for litex upstream
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 15:40:56 +0000 (16:40 +0100)]
remove unneeded option
Luke Kenneth Casson Leighton [Sun, 18 Apr 2021 11:54:09 +0000 (12:54 +0100)]
update to build ls180 4k SRAMs
Luke Kenneth Casson Leighton [Thu, 15 Apr 2021 14:06:14 +0000 (15:06 +0100)]
got ft232 openocd test working
Luke Kenneth Casson Leighton [Thu, 8 Apr 2021 20:31:05 +0000 (21:31 +0100)]
reduce jtag data bus width to 32, to match litex
set (ignored) pc_i to 64 bit
remove mem_2.init cp
Luke Kenneth Casson Leighton [Tue, 6 Apr 2021 14:11:23 +0000 (15:11 +0100)]
more experimenting with STLinkv2 openocd
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 17:56:28 +0000 (18:56 +0100)]
add stlink directdap config
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 11:57:31 +0000 (12:57 +0100)]
hla newtap is apparently the command to run, to request a JTAG tap be set up
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 11:31:45 +0000 (12:31 +0100)]
add first version opnocd_stlinkv2.cfg
Luke Kenneth Casson Leighton [Mon, 5 Apr 2021 11:05:49 +0000 (12:05 +0100)]
sort out sdr and sdmmc OE pad drive, no longer one signal
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 22:24:00 +0000 (23:24 +0100)]
disable PLL so increase not-connected by another 4 pins
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 21:35:52 +0000 (22:35 +0100)]
remove cocotb, moved to soc-cocotb-sim (as submodule)
Staf Verhaegen [Thu, 1 Apr 2021 14:26:28 +0000 (16:26 +0200)]
Use correct ir_width for libresoc JTAG TAP.
No need to define IDCODE anymore as default will now be OK.
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:23:28 +0000 (15:23 +0100)]
whitespace
Staf Verhaegen [Thu, 1 Apr 2021 12:49:55 +0000 (14:49 +0200)]
Document c4m-jtag dependency.
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:23:58 +0000 (13:23 +0100)]
disable PLL for litex build, new variant
Staf Verhaegen [Thu, 1 Apr 2021 12:10:07 +0000 (14:10 +0200)]
Fix svf file for limited c4m-jtag SVF grammar.
Staf Verhaegen [Thu, 1 Apr 2021 11:23:04 +0000 (13:23 +0200)]
First setup for cocotb test run.
Currently only test bench is using Icarus Verilog on pre-layout design
without SRAMs.
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:53:41 +0000 (11:53 +0100)]
update Makefile to build 4ksrams
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:12:50 +0000 (19:12 +0100)]
move name of XICS ICS/ICP to match latest litex pythondata-microwatt
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 17:57:06 +0000 (18:57 +0100)]
must not add bus width parameter
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 17:03:35 +0000 (18:03 +0100)]
fix issues with port direction on several pads
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 14:24:38 +0000 (14:24 +0000)]
latest fighting with litex to get pad directions connected up
Luke Kenneth Casson Leighton [Thu, 25 Mar 2021 06:08:27 +0000 (06:08 +0000)]
debugging ls180 litex hell
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:51:02 +0000 (12:51 +0000)]
sort out naming of IOpads for bi-directional pins
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:50:42 +0000 (12:50 +0000)]
SDR pad mask output for DM
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 14:14:38 +0000 (14:14 +0000)]
unneeded file
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 13:50:42 +0000 (13:50 +0000)]
splitting out litex files from soc repo into separate repo
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 13:42:15 +0000 (13:42 +0000)]
first (empty) commit