mesa.git
9 years agoilo: update CLIP related functions for Gen8
Chia-I Wu [Tue, 27 Jan 2015 11:57:40 +0000 (19:57 +0800)]
ilo: update CLIP related functions for Gen8

9 years agoilo: update SF_CLIP_VIEWPORT for Gen8
Chia-I Wu [Mon, 26 Jan 2015 08:23:29 +0000 (16:23 +0800)]
ilo: update SF_CLIP_VIEWPORT for Gen8

9 years agoilo: update streamout related functions for Gen8
Chia-I Wu [Mon, 26 Jan 2015 08:37:38 +0000 (16:37 +0800)]
ilo: update streamout related functions for Gen8

9 years agoilo: update 3DSTATE_{DS,HS,GS} for Gen8
Chia-I Wu [Mon, 26 Jan 2015 08:08:23 +0000 (16:08 +0800)]
ilo: update 3DSTATE_{DS,HS,GS} for Gen8

9 years agoilo: update 3DSTATE_CONSTANT_x for Gen8
Chia-I Wu [Mon, 26 Jan 2015 07:51:41 +0000 (15:51 +0800)]
ilo: update 3DSTATE_CONSTANT_x for Gen8

9 years agoilo: update 3DSTATE_URB_x for Gen8
Chia-I Wu [Tue, 27 Jan 2015 16:20:09 +0000 (00:20 +0800)]
ilo: update 3DSTATE_URB_x for Gen8

9 years agoilo: update 3DSTATE_PUSH_CONSTANT_ALLOC_x for Gen8
Chia-I Wu [Tue, 27 Jan 2015 16:07:15 +0000 (00:07 +0800)]
ilo: update 3DSTATE_PUSH_CONSTANT_ALLOC_x for Gen8

9 years agoilo: update render engine common helpers for Gen8
Chia-I Wu [Mon, 26 Jan 2015 07:34:34 +0000 (15:34 +0800)]
ilo: update render engine common helpers for Gen8

9 years agoilo: update BLT helpers for Gen8
Chia-I Wu [Sun, 25 Jan 2015 08:19:14 +0000 (16:19 +0800)]
ilo: update BLT helpers for Gen8

9 years agoilo: update MI helpers for Gen8
Chia-I Wu [Sun, 25 Jan 2015 07:25:33 +0000 (15:25 +0800)]
ilo: update MI helpers for Gen8

9 years agoilo: add functions for Gen8 relocs
Chia-I Wu [Sun, 25 Jan 2015 10:04:25 +0000 (18:04 +0800)]
ilo: add functions for Gen8 relocs

Extend ilo_builder_writer_reloc() for Gen8 memory addressing.  Add new
wrappers, ilo_builder_surface_reloc64(() and ilo_builder_batch_reloc64().

9 years agoilo: update the toy compiler for Gen8
Chia-I Wu [Fri, 23 Jan 2015 17:12:04 +0000 (01:12 +0800)]
ilo: update the toy compiler for Gen8

Based on what we know from the classic driver.

9 years agoilo: update genhw headers
Chia-I Wu [Fri, 23 Jan 2015 07:44:53 +0000 (15:44 +0800)]
ilo: update genhw headers

Accumulated changes for various renames and additions, including Gen8
definitions.  Some of the dynamic state __SIZE no longer means the size of an
element, but the size of an array of elements.  The changes can be seen in
ilo_render_dynamic.c.

9 years agoilo: clean up ilo_gpe_init_dsa()
Chia-I Wu [Mon, 26 Jan 2015 06:58:16 +0000 (14:58 +0800)]
ilo: clean up ilo_gpe_init_dsa()

Add dsa_get_stencil_enable_gen6(), dsa_get_depth_enable_gen6(), and
dsa_get_alpha_enable_gen6() to be called from ilo_gpe_init_dsa().

9 years agoilo: clean up ilo_gpe_init_blend()
Chia-I Wu [Sun, 25 Jan 2015 17:08:31 +0000 (01:08 +0800)]
ilo: clean up ilo_gpe_init_blend()

Make ilo_blend_state more space efficient and forward-looking.

9 years agoilo: clean up sample patterns
Chia-I Wu [Mon, 26 Jan 2015 06:00:25 +0000 (14:00 +0800)]
ilo: clean up sample patterns

Use signed int for sample positions and add helpers to access them.  Call them
patterns instead of positions.

9 years agoglsl: Optimize (f2i(trunc x)) into (f2i x).
Matt Turner [Fri, 30 Jan 2015 21:42:19 +0000 (13:42 -0800)]
glsl: Optimize (f2i(trunc x)) into (f2i x).

total instructions in shared programs: 5950326 -> 5949286 (-0.02%)
instructions in affected programs:     88264 -> 87224 (-1.18%)
helped:                                692

9 years agoglsl: Optimize round-half-up pattern.
Matt Turner [Wed, 28 Jan 2015 18:09:14 +0000 (10:09 -0800)]
glsl: Optimize round-half-up pattern.

Hurts some Psychonauts shaders, but after the next patch (which this
enables) they're fewer instructions than before this patch.

9 years agoglsl: Add trunc() to ir_builder.
Matt Turner [Fri, 30 Jan 2015 21:50:28 +0000 (13:50 -0800)]
glsl: Add trunc() to ir_builder.

9 years agoi965: Add LINTERP/CINTERP to can_do_cmod().
Matt Turner [Sat, 24 Jan 2015 05:58:51 +0000 (21:58 -0800)]
i965: Add LINTERP/CINTERP to can_do_cmod().

LINTERP is implemented as a PLN instruction or a LINE+MAC. PLN and MAC
can do conditional mod. CINTERP is just a MOV.

total instructions in shared programs: 5952103 -> 5950284 (-0.03%)
instructions in affected programs:     324573 -> 322754 (-0.56%)
helped:                                1819

We lose the SIMD16 in one Unigine Heaven shader which appears six times
in shader-db.

9 years agoprogram: Remove _mesa_nop_vertex_program/_mesa_nop_fragment_program.
Matt Turner [Wed, 11 Feb 2015 02:45:18 +0000 (18:45 -0800)]
program: Remove _mesa_nop_vertex_program/_mesa_nop_fragment_program.

Dead since

   commit 284ce20901b0c2cfab1d952cc129b8f3cd068f12
   Author: Eric Anholt <eric@anholt.net>
   Date:   Fri Aug 20 10:52:14 2010 -0700

       Remove remnants of the old glsl compiler.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agonir: Recognize open-coded fmin/fmax.
Matt Turner [Wed, 11 Feb 2015 05:43:32 +0000 (21:43 -0800)]
nir: Recognize open-coded fmin/fmax.

And unfortunately other shaders do the same thing but with >=/<= which
we can't apply this optimization to because of NaNs.

instructions in affected programs:     23309 -> 22938 (-1.59%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agonir: Add algebraic opt for int comparisons with identical operands.
Eric Anholt [Sat, 7 Feb 2015 01:12:59 +0000 (17:12 -0800)]
nir: Add algebraic opt for int comparisons with identical operands.

No change on shader-db on i965.

v2: Reword the comment due to feedback from Erik Faye-Lund

Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v1)
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> (v1)
9 years agonir: Fix load_const comparisons for CSE.
Eric Anholt [Sat, 7 Feb 2015 01:16:29 +0000 (17:16 -0800)]
nir: Fix load_const comparisons for CSE.

We want the size of a float per component, not the size of a whole vec4.

NIR instructions on i965:
total instructions in shared programs: 1261937 -> 1261929 (-0.00%)
instructions in affected programs:     114 -> 106 (-7.02%)

Looking at one of these examples (tesseract), it's from vec4 load_consts
for a MRT solid fill, which do get CSEed now that we don't memcmp off the
end of the const value and into the SSA def.  For the 1-component loads
that are common in i965, we were only memcmping off into the rest of the
usually zero-filled const_value.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agoi965/fs: Remove conditional mod when optimizing a SEL into a MOV.
Matt Turner [Wed, 11 Feb 2015 05:36:26 +0000 (21:36 -0800)]
i965/fs: Remove conditional mod when optimizing a SEL into a MOV.

Missed in commit ca675b73, but got right in the companion commit 3c28b2c0.

9 years agodarwin: build fix
Jeremy Huddleston Sequoia [Wed, 11 Feb 2015 06:21:47 +0000 (22:21 -0800)]
darwin: build fix

xfont.c:237:14: error: implicit declaration of function 'GetGLXDRIDrawable' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
   glxdraw = GetGLXDRIDrawable(CC->currentDpy, CC->currentDrawable);
             ^
Fixes regression from 291be28476ea60c6fb1eb2a882e2e25def5d3735

Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>
9 years agodarwin: build fix
Jeremy Huddleston Sequoia [Wed, 11 Feb 2015 04:32:02 +0000 (20:32 -0800)]
darwin: build fix

../../../src/mesa/main/compiler.h:47:10: fatal error: 'util/macros.h' file not found

Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>
9 years agoglsl: Optimize 1/exp(x) into exp(-x).
Matt Turner [Tue, 10 Feb 2015 20:31:37 +0000 (12:31 -0800)]
glsl: Optimize 1/exp(x) into exp(-x).

Lots of shaders divide by exp2(...) which we turn into a multiplication
by the reciprocal. We can avoid the reciprocal by simply negating exp2's
argument.

total instructions in shared programs: 5947154 -> 5946695 (-0.01%)
instructions in affected programs:     118661 -> 118202 (-0.39%)
helped:                                380

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agonir: Remove casts from void*.
Matt Turner [Tue, 10 Feb 2015 19:23:55 +0000 (11:23 -0800)]
nir: Remove casts from void*.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agonir: Replace assert(0) with unreachable().
Matt Turner [Tue, 10 Feb 2015 19:21:47 +0000 (11:21 -0800)]
nir: Replace assert(0) with unreachable().

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
9 years agonir: Remove unused has_indirect variable.
Matt Turner [Tue, 10 Feb 2015 19:20:13 +0000 (11:20 -0800)]
nir: Remove unused has_indirect variable.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/vec4: Emit MADs from (x + abs(y * z)).
Matt Turner [Sat, 31 Jan 2015 02:24:20 +0000 (18:24 -0800)]
i965/vec4: Emit MADs from (x + abs(y * z)).

Same as commit 3654b6d4 to the fs backend.

total instructions in shared programs: 5945788 -> 5945787 (-0.00%)
instructions in affected programs:     36 -> 35 (-2.78%)
helped:                                1

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/vec4: Emit MADs from (x + -(y * z)).
Matt Turner [Sat, 20 Dec 2014 05:35:56 +0000 (21:35 -0800)]
i965/vec4: Emit MADs from (x + -(y * z)).

Same as commit c4fab711 to the fs backend.

total instructions in shared programs: 5945998 -> 5945788 (-0.00%)
instructions in affected programs:     74665 -> 74455 (-0.28%)
helped:                                399
HURT:                                  180

It hurts some programs because we make no attempts in the vec4 backend
to avoid MADs if they have constant (or vector uniform) arguments.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/skl: Implement WaDisable1DDepthStencil
Neil Roberts [Mon, 2 Feb 2015 17:47:23 +0000 (17:47 +0000)]
i965/skl: Implement WaDisable1DDepthStencil

Skylake+ doesn't support setting a depth buffer to a 1D surface but it
does allow pretending it's a 2D texture with a height of 1 instead.

This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit
test (and also seems to avoid a subsequent GPU hang).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89037
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/gen7-8: Implement glMemoryBarrier().
Francisco Jerez [Sat, 23 Nov 2013 02:35:46 +0000 (18:35 -0800)]
i965/gen7-8: Implement glMemoryBarrier().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Generalize the update_null_renderbuffer_surface vtbl hook to non-renderbuffers.
Francisco Jerez [Tue, 10 Feb 2015 13:53:14 +0000 (15:53 +0200)]
i965: Generalize the update_null_renderbuffer_surface vtbl hook to non-renderbuffers.

Null surfaces are going to be useful to have something to point
unbound image units to, as the ARB_shader_image_load_store extension
requires us to behave deterministically in cases where some shader
tries to access an unbound image unit: Invalid stores and atomics are
supposed to be discarded and invalid loads are supposed to return
zero, which is precisely what the null surface does.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Allocate binding table space for shader images.
Francisco Jerez [Sat, 23 Nov 2013 00:08:12 +0000 (16:08 -0800)]
i965: Allocate binding table space for shader images.

v2: Bump the number of supported image uniforms to 32 (Ken).

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Don't tile 1D miptrees.
Francisco Jerez [Fri, 14 Nov 2014 18:30:46 +0000 (20:30 +0200)]
i965: Don't tile 1D miptrees.

It doesn't really improve locality of texture fetches, quite the
opposite it's a waste of memory bandwidth and space due to tile
alignment.

v2: Check mt->logical_height0 instead of mt->target (Ken).  Add short
    comment explaining why they shouldn't be tiled.

Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.
Francisco Jerez [Wed, 4 Feb 2015 16:37:46 +0000 (18:37 +0200)]
i965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.

It's expanded to several instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: Handle negated unsigned immediate values in constant propagation.
Francisco Jerez [Fri, 6 Feb 2015 12:38:20 +0000 (14:38 +0200)]
i965: Handle negated unsigned immediate values in constant propagation.

Negation of UD/UW sources behaves the same as for D/W sources, taking
the two's complement of the source, except for bitwise logical
operations on Gen8 and up which take the one's complement.  Fixes
crash in a GLSL shader with subtraction of two unsigned values.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Take into account non-zero reg_offset during register allocation.
Francisco Jerez [Tue, 3 Feb 2015 20:50:06 +0000 (22:50 +0200)]
i965/vec4: Take into account non-zero reg_offset during register allocation.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Add register classes up to MAX_VGRF_SIZE.
Francisco Jerez [Tue, 3 Feb 2015 18:34:39 +0000 (20:34 +0200)]
i965/vec4: Add register classes up to MAX_VGRF_SIZE.

In preparation for some send from GRF instructions that will require
larger payloads.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Init mlen for several send from GRF instructions.
Francisco Jerez [Tue, 3 Feb 2015 20:52:37 +0000 (22:52 +0200)]
i965/vec4: Init mlen for several send from GRF instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Don't infer MRF dependencies for send from GRF instructions.
Francisco Jerez [Tue, 3 Feb 2015 20:42:23 +0000 (22:42 +0200)]
i965/vec4: Don't infer MRF dependencies for send from GRF instructions.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Fix the scheduler to take into account reads and writes of multiple registers.
Francisco Jerez [Thu, 5 Feb 2015 20:39:33 +0000 (22:39 +0200)]
i965/vec4: Fix the scheduler to take into account reads and writes of multiple registers.

v2: Avoid nested ternary operators in vec4_instruction::regs_read(). (Matt)

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends from GRF.
Francisco Jerez [Thu, 5 Feb 2015 20:58:03 +0000 (22:58 +0200)]
i965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends from GRF.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Pass dst register to the vec4_instruction constructor.
Francisco Jerez [Tue, 3 Feb 2015 20:53:17 +0000 (22:53 +0200)]
i965/vec4: Pass dst register to the vec4_instruction constructor.

So regs_written gets initialized with a sensible value.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.
Francisco Jerez [Tue, 3 Feb 2015 13:31:46 +0000 (15:31 +0200)]
i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Implement equals() method for dst_reg too.
Francisco Jerez [Thu, 5 Feb 2015 20:40:07 +0000 (22:40 +0200)]
i965/vec4: Implement equals() method for dst_reg too.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.
Francisco Jerez [Tue, 3 Feb 2015 19:57:38 +0000 (21:57 +0200)]
i965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.

Scalar registers are required to have zero stride, fix the
regs_written calculation not to assume that the instruction writes
zero registers in that case.

v2: Rename CEILING() to DIV_ROUND_UP(). (Matt, Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Fix stack allocation of fs_inst and stop stealing src array provided on...
Francisco Jerez [Thu, 5 Feb 2015 23:14:51 +0000 (01:14 +0200)]
i965/fs: Fix stack allocation of fs_inst and stop stealing src array provided on construction.

Using 'ralloc*(this, ...)' is wrong if the object has automatic
storage or was allocated through any other means.  Use normal dynamic
memory instead.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Remove duplicate include of brw_shader.h
Francisco Jerez [Tue, 3 Feb 2015 13:52:37 +0000 (15:52 +0200)]
i965/fs: Remove duplicate include of brw_shader.h

The second one was inside an extern "C" block, luckily it was being
discarded by the preprocessor.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: Move up fs_inst::flag_subreg to backend_instruction.
Francisco Jerez [Thu, 5 Feb 2015 23:28:12 +0000 (01:28 +0200)]
i965: Move up fs_inst::flag_subreg to backend_instruction.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: Move up fs_inst::regs_written to backend_instruction.
Francisco Jerez [Thu, 5 Feb 2015 23:27:40 +0000 (01:27 +0200)]
i965: Move up fs_inst::regs_written to backend_instruction.

It will also be useful in the VEC4 back-end.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/vec4: Remove dependency of vec4_instruction on the visitor class.
Francisco Jerez [Thu, 5 Feb 2015 23:25:50 +0000 (01:25 +0200)]
i965/vec4: Remove dependency of vec4_instruction on the visitor class.

The only reason why you need a vec4_visitor to construct a
vec4_instruction is to initialize vec4_instruction::ir and
::annotation.  Instead set them from vec4_visitor::emit() just like
fs_visitor does.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965/fs: Remove dependency of fs_inst on the visitor class.
Francisco Jerez [Thu, 5 Feb 2015 23:24:17 +0000 (01:24 +0200)]
i965/fs: Remove dependency of fs_inst on the visitor class.

The fs_visitor argument of fs_inst::regs_read() wasn't used at all.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: Move IR object definitions to separate header files.
Francisco Jerez [Thu, 5 Feb 2015 23:11:18 +0000 (01:11 +0200)]
i965: Move IR object definitions to separate header files.

One should be able to manipulate i965 IR without pulling the whole
FS/VEC4 visitor classes -- Optimization passes and other
transformations would ideally be visitor-agnostic.  Among other issues
this avoids a circular dependency between the header file where such
visitor-agnostic code will be defined and the main FS/VEC4 header
where both IR (layer below) and visitor (layer above) happen to be
defined.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoi965: Factor out virtual GRF allocation to a separate object.
Francisco Jerez [Tue, 10 Feb 2015 13:51:34 +0000 (15:51 +0200)]
i965: Factor out virtual GRF allocation to a separate object.

Right now virtual GRF book-keeping and allocation is performed in each
visitor class separately (among other hundred different things),
leading to duplicated logic in each visitor and preventing layering as
it forces any code that manipulates i965 IR and needs to allocate
virtual registers to depend on the specific visitor that happens to be
used to translate from GLSL IR.

v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor).

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoglsl: Forbid calling the constructor of any opaque type.
Francisco Jerez [Thu, 4 Dec 2014 08:40:56 +0000 (10:40 +0200)]
glsl: Forbid calling the constructor of any opaque type.

The spec doesn't define any opaque type constructors.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agoglsl: Return correct number of coordinate components for cubemap array images.
Francisco Jerez [Wed, 19 Nov 2014 16:22:07 +0000 (18:22 +0200)]
glsl: Return correct number of coordinate components for cubemap array images.

Cubemap array images are unlike cubemap array samplers in that they don't need
an additional coordinate to index individual cubemaps in the array, instead
they behave like a 2D array of 6n layers, with n the number of cubemaps in the
array.  Take this exception into account.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
9 years agomesa: Bump MAX_IMAGE_UNIFORMS to 32.
Francisco Jerez [Mon, 9 Feb 2015 16:31:03 +0000 (18:31 +0200)]
mesa: Bump MAX_IMAGE_UNIFORMS to 32.

So the i965 driver can expose 32 image uniforms per shader stage.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agomesa: Rename the CEILING() macro to DIV_ROUND_UP().
Francisco Jerez [Tue, 10 Feb 2015 13:37:47 +0000 (15:37 +0200)]
mesa: Rename the CEILING() macro to DIV_ROUND_UP().

Some people have complained that code using the CEILING() macro is
difficult to understand because it's not immediately obvious what it
is supposed to do until you go and look up its definition.  Use a more
descriptive name that matches the similar utility macro in the Linux
kernel.

Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agonv50,nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediately
Tiziano Bacocco [Fri, 6 Feb 2015 18:03:41 +0000 (19:03 +0100)]
nv50,nvc0: Mark PIPE_QUERY_TIMESTAMP_DISJOINT as ready immediately

Without this when an application issues that query, it would try to
wait the result from the gpu, and since no query has been actually
issued, it will wait forever.

Signed-off-by: Tiziano Bacocco <tizbac2@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonv50/ir: Fold IMM into MAD
Roy Spliet [Fri, 6 Feb 2015 21:46:56 +0000 (22:46 +0100)]
nv50/ir: Fold IMM into MAD

Add a specific optimisation pass for NV50 to check whether SRC0 or SRC1 is
a MOV dst, IMM. If so: fold the IMM in and try to drop the MOV. Must be
done post-RA because it requires that SDST == SSRC2.

V2: improve readability and add comments to clarify decisions
V3: Remove redundant code... compiler already attempts to put the IMM in
SSRC1

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonv50/ir: Add emit support for MAD IMM format
Roy Spliet [Fri, 6 Feb 2015 21:46:55 +0000 (22:46 +0100)]
nv50/ir: Add emit support for MAD IMM format

But don't enable generation of it in the opProperties, because we can't
guarantee the SDST==SRC2 constraint until after register assignment. We'll
add a post-RA folding pass to utilise this.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonv50/ir: Add support for MAD 4-byte opcode
Roy Spliet [Fri, 6 Feb 2015 21:46:54 +0000 (22:46 +0100)]
nv50/ir: Add support for MAD 4-byte opcode

Add emission rules for negative and saturate flags for MAD 4-byte opcodes,
and get rid of some of the constraints. Obviously tested with a wide variety
of shaders.

V2: Document MAD as supported short form
V3: Split up IMM from short-form modifiers

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonv50/ir: change the way float face is returned
Ilia Mirkin [Mon, 5 Jan 2015 17:44:10 +0000 (12:44 -0500)]
nv50/ir: change the way float face is returned

The old way made it impossible for the optimizer to reason about what
was going on. The new way is the same number of instructions (the neg
gets folded into the cvt) but enables the optimizer to be cleverer if
comparing to a constant (most common case). [The optimizer is presently
not sufficiently clever to work this out, but it could relatively easily
be made to be. The old way would have required significant complexity to
work out.]

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonir: Mark nir_print_instr's instr pointer as const.
Kenneth Graunke [Mon, 9 Feb 2015 21:42:16 +0000 (13:42 -0800)]
nir: Mark nir_print_instr's instr pointer as const.

Printing instructions doesn't modify them, so we can mark the parameter
const.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Fix integer border color on Haswell.
Kenneth Graunke [Fri, 6 Feb 2015 11:39:20 +0000 (03:39 -0800)]
i965: Fix integer border color on Haswell.

+82 Piglits - 100% of border color tests now pass on Haswell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org
9 years agoi965: Use a gl_color_union for sampler border color.
Kenneth Graunke [Wed, 7 May 2014 05:56:17 +0000 (22:56 -0700)]
i965: Use a gl_color_union for sampler border color.

This should have no effect, but will make it easier to implement other
bug fixes.

v2: Eliminate "unsigned one" local; just use the value where necessary.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
9 years agoi965: Override swizzles for integer luminance formats.
Kenneth Graunke [Fri, 6 Feb 2015 10:06:27 +0000 (02:06 -0800)]
i965: Override swizzles for integer luminance formats.

The hardware's integer luminance formats are completely unusable;
currently we fall back to RGBA.  This means we need to override
the texture swizzle to obtain the XXX1 values expected for luminance
formats.

Fixes spec/EXT_texture_integer/texwrap formats bordercolor [swizzled]
on Broadwell - 100% of border color tests now pass on Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: mesa-stable@lists.freedesktop.org
9 years agoutil/u_atomic: Add new macro p_atomic_add
Carl Worth [Thu, 5 Feb 2015 23:36:59 +0000 (15:36 -0800)]
util/u_atomic: Add new macro p_atomic_add

This provides for atomic addition, which will be used by an upcoming
shader-cache patch. A simple test is added to "make check" as well.

Note: The various O/S functions differ on whether they return the
original value or the value after the addition, so I did not provide
an add_return() macro which would be sensitive to that difference.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
9 years agoutil/hash_table: Try to hit a double-insertion bug in the collision test
Jason Ekstrand [Thu, 5 Feb 2015 02:49:11 +0000 (18:49 -0800)]
util/hash_table: Try to hit a double-insertion bug in the collision test

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoutil/set: Do a full search when adding new items
Jason Ekstrand [Thu, 5 Feb 2015 02:46:23 +0000 (18:46 -0800)]
util/set: Do a full search when adding new items

Previously, the set_insert function would bail early if it found a deleted
slot that it could re-use.  However, this is a problem if the key being
inserted is already in the set but further down the list.  If this happens,
the element ends up getting inserted in the set twice.  This commit makes
it so that we walk over all of the possible entries for the given key and
then, if we don't find the key, place it in the available free entry we
found.

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agoutil/hash_table: Do a full search when adding new items
Jason Ekstrand [Thu, 5 Feb 2015 02:29:32 +0000 (18:29 -0800)]
util/hash_table: Do a full search when adding new items

Previously, the hash_table_insert function would bail early if it found a
deleted slot that it could re-use.  However, this is a problem if the key
being inserted is already in the hash table but further down the list.  If
this happens, the element ends up getting inserted in the hash table twice.
This commit makes it so that we walk over all of the possible entries for
the given key and then, if we don't find the key, place it in the available
free entry we found.

Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agomesa: Make renderbuffer FBO attachments not layered
James Legg [Sat, 7 Feb 2015 23:33:15 +0000 (23:33 +0000)]
mesa: Make renderbuffer FBO attachments not layered

For framebuffer completeness checks, consider renderbuffers as not
layered. Previously, they would have counted as layered if a layered
textured had previously been bound to the same attachment point. This
could cause framebuffer completeness checks to incorrectly fail with
GL_FRAMEBUFFER_INCOMPLETE_LAYER_TARGETS, even if no layered attachments
were present.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89026

9 years agoPost-branch version bump to 10.6.0-devel, add release notes template
Emil Velikov [Sat, 7 Feb 2015 19:12:20 +0000 (19:12 +0000)]
Post-branch version bump to 10.6.0-devel, add release notes template

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agogallium/hud: also try R8_UNORM format for font texture
Brian Paul [Wed, 4 Feb 2015 20:44:48 +0000 (13:44 -0700)]
gallium/hud: also try R8_UNORM format for font texture

Convert the code to try formats from an array rather than a bunch
of if/else cases.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agogallium/hud: flush stdout in print_help(), for Windows
Brian Paul [Wed, 4 Feb 2015 20:34:44 +0000 (13:34 -0700)]
gallium/hud: flush stdout in print_help(), for Windows

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
9 years agoi965: Add more stringent blitter assertions
Ben Widawsky [Tue, 23 Dec 2014 21:59:16 +0000 (13:59 -0800)]
i965: Add more stringent blitter assertions

Blits to or from a y-tiled surface must always be a multiple of the tile size.
From page 16 of the HSW PRM
(https://01.org/linuxgraphics/sites/default/files/documentation/intel-gfx-prm-osrc-hsw-memory-views.pdf#16)
"The pitch of a tiled enclosing region must be an integral number of tile
widths"

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Consolidate some of the intel_blit logic
Ben Widawsky [Tue, 23 Dec 2014 20:28:29 +0000 (12:28 -0800)]
i965: Consolidate some of the intel_blit logic

An upcoming patch is going to introduce some code here, and having this code
organized as the patch does makes it a bit easier to read later.

There should be no functional change here.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agost/dri: Make depth buffer optional for postprocessing
Park, Jeongmin [Sat, 7 Feb 2015 08:53:48 +0000 (17:53 +0900)]
st/dri: Make depth buffer optional for postprocessing

Since only pp_jimenezmlaa uses depth buffer, we can make it optional.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
9 years agopostprocess: Check for depth buffer in pp_jimenezmlaa
Park, Jeongmin [Sat, 7 Feb 2015 08:53:47 +0000 (17:53 +0900)]
postprocess: Check for depth buffer in pp_jimenezmlaa

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88962
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
9 years agoi965/vec4: Correct MUL destination hazard
Ben Widawsky [Wed, 3 Dec 2014 01:30:49 +0000 (17:30 -0800)]
i965/vec4: Correct MUL destination hazard

As it turns out, we were over-thinking the cause of the hang on
Cherryview. It's simply errata for Cherryview.

commit 88fea85f09e2252035bec66ab26c375b45b000f5
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Fri Nov 21 10:47:41 2014 -0800

    i965/vec4/gen8: Handle the MUL dest hazard exception

This is an explanation to why we never saw the hang on BDW.

NOTE: The problem the original patch was trying to fix does still exist. It will
have to be fixed at some point.

v2: Modify commit message, s/CHV/BDW

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agodocs: add news item and link release notes for mesa 10.4.4
Emil Velikov [Sat, 7 Feb 2015 00:51:08 +0000 (00:51 +0000)]
docs: add news item and link release notes for mesa 10.4.4

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agodocs: Add sha256 sums for the 10.4.4 release
Emil Velikov [Sat, 7 Feb 2015 00:47:18 +0000 (00:47 +0000)]
docs: Add sha256 sums for the 10.4.4 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 54da987baec25fbaf6975c93f197ddbfe65a303c)

9 years agoAdd release notes for the 10.4.4 release
Emil Velikov [Sat, 7 Feb 2015 00:17:09 +0000 (00:17 +0000)]
Add release notes for the 10.4.4 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 62eb27ac8bbd979796f50e253f6c786d7d791242)

9 years agonir: Fix broken fsat recognizer.
Eric Anholt [Fri, 30 Jan 2015 22:03:14 +0000 (14:03 -0800)]
nir: Fix broken fsat recognizer.

We've probably never seen this ridiculous pattern in the wild, so it
didn't matter.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agonir: Slightly simplify algebraic code generation by reusing a struct.
Eric Anholt [Wed, 28 Jan 2015 00:42:38 +0000 (16:42 -0800)]
nir: Slightly simplify algebraic code generation by reusing a struct.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agotgsi/ureg: Add missing some missing opcodes opcode_tmp.h
Eric Anholt [Mon, 10 Nov 2014 22:26:14 +0000 (14:26 -0800)]
tgsi/ureg: Add missing some missing opcodes opcode_tmp.h

I wanted all of these for NIR-to-TGSI.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
9 years agotgsi/ureg: Move ureg_dst_register() to the header.
Eric Anholt [Fri, 7 Nov 2014 20:35:58 +0000 (12:35 -0800)]
tgsi/ureg: Move ureg_dst_register() to the header.

I wanted to use it for nir-to-tgsi.  The equivalent ureg_src_register() is
also located here.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
9 years agogallium/u_tests: test a NULL buffer sampler view
Marek Olšák [Sun, 1 Feb 2015 15:28:26 +0000 (16:28 +0100)]
gallium/u_tests: test a NULL buffer sampler view

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
9 years agogallium/u_tests: test a NULL constant buffer
Marek Olšák [Sun, 1 Feb 2015 12:11:49 +0000 (13:11 +0100)]
gallium/u_tests: test a NULL constant buffer

This expects (0,0,0,0), though it can be changed to something else or allow
more than one set of values to be considered correct.

This is currently the radeonsi behavior.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
9 years agogallium/u_tests: test a NULL texture sampler view
Marek Olšák [Sun, 1 Feb 2015 12:08:53 +0000 (13:08 +0100)]
gallium/u_tests: test a NULL texture sampler view

v2: allow one of the two values

9 years agogallium/u_tests: restructure the only test, refactor out reusable code
Marek Olšák [Sun, 1 Feb 2015 12:05:14 +0000 (13:05 +0100)]
gallium/u_tests: restructure the only test, refactor out reusable code

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
9 years agogallium: run gallium tests if GALLIUM_TESTS=1 is set
Marek Olšák [Sun, 1 Feb 2015 11:59:27 +0000 (12:59 +0100)]
gallium: run gallium tests if GALLIUM_TESTS=1 is set

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
9 years agogallium/postprocessing: fix crash at context destruction
Marek Olšák [Thu, 5 Feb 2015 17:13:20 +0000 (18:13 +0100)]
gallium/postprocessing: fix crash at context destruction

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agor600g/sb: fix a bug in constants folding optimisation pass
Xavier Bouchoux [Wed, 28 Jan 2015 01:31:58 +0000 (02:31 +0100)]
r600g/sb: fix a bug in constants folding optimisation pass

    ADD     R6.y.1,    R5.w.1, ~1|3f800000
    ADD     R6.y.2,    |R6.y.1|, -0.0001|b8d1b717

was wrongly being converted to

    ADD     R6.y.1,    R5.w.1, ~1|3f800000
    ADD     R6.y.2,    R5.w.1, -1.0001|bf800347

because abs() modifier was ignored.

Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
9 years agor600g: fix abs() support on ALU 3 source operands instructions
Xavier Bouchoux [Wed, 28 Jan 2015 01:20:51 +0000 (02:20 +0100)]
r600g: fix abs() support on ALU 3 source operands instructions

Since alu does not support abs() modifier on source operands, spill
and apply the modifiers to a temp register when needed.

Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
9 years agor300g: small code cleanup (v2)
David Heidelberg [Sun, 28 Dec 2014 00:11:14 +0000 (01:11 +0100)]
r300g: small code cleanup (v2)

v2: incorporated changes from Marek Olšák

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: David Heidelberg <david@ixit.cz>