st/mesa: new st_DrawAtlasBitmaps() function for drawing bitmap text

This basically saves the current pipeline state, sets up state for
rendering, constructs a set of textured quads, renders, then restores
the previous pipeline state.

It shouldn't be hard to implement a similar function for non-gallium
drives.  With some code refactoring, the vertex definition code could
probably be shared.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: implement a display list / glBitmap texture atlas

This improves the performance of applications which use glXUseXFont()
or wglUseFontBitmaps() and glCallLists() to draw bitmap text.

Basically, we collect all the glBitmap images from the display lists
and put them into a texture atlas.  To render the bitmaps for a
glCallLists() command, we render a set of textured quads where each
quad is textured with one bitmap image.  Actually, the rendering part
has to be done by the Mesa driver or Mesa/gallium state tracker.

Note that GLUT demos that use glutBitmapCharacter() don't benefit
from this.

v2, per Nicolai Hähnle:
- check the max tex rect size is at least 1024.
- add comment in dd.h that texture_rectangle is required.
- in _mesa_DeleteLists(), try to delete the atlas before the list(s)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: apply DepthMode swizzle to stencil texturing as well

Gallium doesn't present these as GL_RED-style. A swizzle is necessary to
present the proper data in the unused components.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965/skl: Update Skylake renderer strings

Also adds some of the Iris/Pro parts which we previously didn't have named.

v2: 0x192d is gt3, not gt4
Adding some 'e' tags for eDRAM parts

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Michał Winiarski <michal.winiarski@intel.com>

i965/skl: Add two missing device IDs

The Iris part is left unbranded because we did not have these with original SKL.

v2: 0x192d is gt3, not gt4

v3: Forgot to update the temporary brand string when I did v2.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Michał Winiarski <michal.winiarski@intel.com>

mesa: allow multisampled format info to be returned on GLES 3.1

The restriction on multisampled integer texture formats only applies to
GLES 3.0, so don't apply it to GLES 3.1 contexts. This fixes a slew of

dEQP-GLES31.functional.state_query.internal_format.*

tests, which now all pass.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965: Extract push constant state to a new file

Every stage has a corresponding 3DSTATE_CONSTANT_XS packet, so having
the code to create and emit push constant buffers in genX_vs_state.c
is a little strange.  Moving it to a separate file seems more logical.

v2 [Ken]: Rebase on master, explain motivation in the commit message.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Make emit_minmax return an instruction*.

And use it in brw_fs_nir.cpp.

i965: Lower min/max after optimization on Gen4/5.

Gen4/5's SEL instruction cannot use conditional modifiers, so min/max
are implemented as CMP + SEL. Handling that after optimization lets us
CSE more.

On Ironlake:

   total instructions in shared programs: 6426035 -> 6422753 (-0.05%)
   instructions in affected programs: 326604 -> 323322 (-1.00%)
   helped: 1411

   total cycles in shared programs: 129184700 -> 129101586 (-0.06%)
   cycles in affected programs: 18950290 -> 18867176 (-0.44%)
   helped: 2419
   HURT: 328

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/vec4: Initialize force_writemask_all in vec4_builder().

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

radeon/llvm: Add TargetLibraryInfo to the pass manager

This will prevent optimization passes from introducing unsupported
library calls.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeon/llvm: Set the target triple on the module

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallivm: Add helpers for creating and destroying TargetLibraryInfo

This functionality is not exposed via the LLVM C API.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nvc0: invalidate all buffers when switching pipe contexts

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: fix up result_src.type when doing i2u/u2i conversions

Even though it's a no-op, it's important to keep track of the type so
that we can pick the properly-signed op later on.

This fixes dEQP-GLES3.functional.shaders.precision.uint.highp_div_fragment,
which ended up using IDIV instead of UDIV.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org

st/mesa: use cso_set_viewport_dims() in try_pbo_upload_common()

Note that this results in a different transformation for the viewport's
Z axis (depth range), but that doesn't matter for this case.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965/gen7: Use predicated rendering for indirect compute

On gen7 (Ivy Bridge, Haswell), we will get a GPU hang if an indirect
dispatch is used, but one of the dimensions is 0.

Therefore we use predicated rendering on the GPGPU_WALKER command to
handle this case.

Fixes piglit test: spec/arb_compute_shader/zero-dispatch-size

From the ARB_compute_shader spec, under DispatchCompute:

"If the work group count in any dimension is zero, no work groups are
 dispatched."

And then for DispatchComputeIndirect:

... "is equivalent (assuming no errors are generated) to calling
DispatchCompute with <num_groups_x>, <num_groups_y> and
<num_groups_z>" ...

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94100
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno: expose time-elapsed query

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: implement time-elapsed query

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: better occlusion/sample counting

This seems to give more reliable results.  More similar to what we do on
a3xx, although I think it breaks the a3xx theory that the four sets of
results map to each MRT (since we appear to still only have four sets on
a4xx).  The divide-by-two is a bit odd, but seems to be needed for some
reason.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/query: fix refcnt'ing issue

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/query: some queries don't have ->begin_query()

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/query: align counter snapshot locations

Some hw queries need their sample memory locations to have certain
alignment.  At the moment that isn't an issue, since the only hw query
is occlusion, so all samples have the same size.  But when others are
added with different sample sizes, this starts to be a problem.

All current and immediately upcoming hw queries simply need their
sample address aligned to their size, so let's use that for now.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/query: add optional enable hook

Add enable hook for hw query providers.  Some will need to configure
perfctr selector registers, which we want to do at the start of the
submit.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: query max gpu freq

This will be needed to support converting from cycle counts to time for
performance related queries (initially time-elapsed, but there are some
additional performance counters that could be wired up).

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Mostly to pull in perf ctrs.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix new gcc6 errors

src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c: In function ‘emit_tex’:
src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c:1368:26: warning: unused variable ‘const_off’ [-Wunused-variable]
  struct ir3_instruction *const_off[4];
                          ^~~~~~~~~
unused since:

commit 8750299a420af76cebd3067f6f603eacde06ae06
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date:   Tue Feb 9 14:51:28 2016 -0800

    nir: Remove the const_offset from nir_tex_instr

Signed-off-by: Rob Clark <robdclark@gmail.com>

nv50/ir: we can't do the add to mad conversion when the mul saturates

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: optimize neg(and(set, 1)) to set

helps shaders in saints row IV, bioshock infinite and shadow warrior

total instructions in shared programs : 1914931 -> 1903900 (-0.58%)
total gprs used in shared programs    : 247920 -> 247785 (-0.05%)
total local used in shared programs   : 5673 -> 5673 (0.00%)
total bytes used in shared programs   : 17558272 -> 17457320 (-0.57%)

                local        gpr       inst      bytes
    helped           0         137         719         719
      hurt           0          12           0           0

v2: remove this opt for OP_SLCT and check against float for OP_SET
v3: simplified the code

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: fix quadop emission in the presence of predication

When there's a predicate, it just goes onto the sources list. If the
quadop only has a single regular source, we will end up thinking that
the predicate is the second source. Check explicitly for the predSrc so
that we don't accidentally emit the wrong thing.

This fixes a bunch of dEQP-GLES3.functional.shaders.derivate.* tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nv50,nvc0: enable/disable seamless cubemap texturing as requested

In a situation where the seamless setting isn't available on a
per-texture basis (G200+ Teslas, and all Fermis), assume that all
samplers will have it identically set, and enable accordingly.

This fixes arb_seamless_cubemap piglit test on Fermi and Tesla.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: add missing ETC2 entries to format_map

Noticed by Ilia when I was trying to figure out why some app was failing
to use ETC2.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: enable compute support on GK110:GM200 with an envvar

Without this NVF0_COMPUTE environment variable, compute support is
initialized by default and this is not what we want for now because
it might break 3D. It will be enabled by default once we are sure it
won't break anything.

Please note that compute support on GM200+ is not enabled yet because
it needs to be double-checked.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: add compute support for GM107

Fortunately, compute support on GM107 is very close to GK110, except
the GK110_COMPUTE.UNK02C4 which is invalid and should not be used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: fix compute state initialization on GK110+

Because our firmware doesn't support the GK110_COMPUTE.FIRMWARE[0x6]
method the GPU hangs when it is used. Removing it fix the issue and
allow to launch compute shaders on GK110+.

Tested on GK208 and GM107.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: remove duplicate interpolation_string() function

We already have one in the IR code that can be used everywhere its
needed in the AST code so remove the one from the AST.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

glsl: remove unused helper

Seems to have become unused when i965 moved to NIR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

glsl: set user defined varyings to smooth by default in ES

This is usually handled by the backends in order to handle the
various interactions with the gl_*Color built-ins.

The problem is this means linking will fail if one side on the
interface adds the smooth qualifier to the varying and the other
side just uses the default even though they match.

This fixes various deqp tests. The spec is not clear what to for
desktop GL so leave it as is for now.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92743

gm107/ir: add ATOM CAS emission

This fixes the following dEQP test and the other compswap variants.

dEQP-GLES31.functional.ssbo.atomic.compswap.highp_int

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: do not init limits when compute shaders are not supported

When the number of uniform blocks is less than 12,
ARB_uniform_buffer_object can't be enabled and the maximum GL version
is not even 3.1...

This fixes a regression introduced in 7c79c1e (st/mesa: add compute
shader state) if the maximum number of uniform blocks allowed for
compute shaders is less than 12. This happens on Kepler but this might
also affect other Gallium drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reported-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Tested-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

mesa: Don't call driver when there is no compute work

The ARB_compute_shader spec says:

  "If the work group count in any dimension is zero, no work groups
   are dispatched."

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965: Set compute shader shared memory max to 64k

See Ivy Bridge PRM, Volume 2, Part 2, 1.8.4 INTERFACE_DESCRIPTOR_DATA:

DWORD 5, bits 20:16: "This field indicates how much shared local
memory the thread group requires. The amount is specified in 4k
blocks, but only powers of 2 are allowed: 0, 4k, 8k, 16k, 32k and 64k
per half-slice."

For Haswell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA:

DWORD 5, bits 20:16: With text identical to the Ivy Bridge PRM.

For Broadwell, see Volume 2d, INTERFACE_DESCRIPTOR_DATA:

DWORD 6, bits 20:16: With text identical to the Ivy Bridge PRM.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

st/mesa: use new CSO_BITS_ALL_SHADERS

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

cso: add CSO_BITS_ALL_SHADERS

For saving/restoring all shader stages.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: simplify st->ctx, ctx->st usage in a various places

st/mesa: use _mesa_geometric_width/height() in glDrawPixels code

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: rename attr variable in st_DrawTex()

Rename to 'tex_attr' to be a bit more clear.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: use 'cso' instead of 'st->cso_context' in st_DrawTex()

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: fix whitespace and add comment in st_DrawTex()

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: used _mesa_num_tex_faces() in st_finalize_texture()

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

cso: make most of the cso_save/restore_x() functions static

Users of the CSO save/restore facility all use the new
cso_save/restore_state() functions instead.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

postprocess: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallium/hud: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallium/util: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: use cso_save/restore_state() in st_cb_texture.c

This simplifies the error handling code too.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: use new cso_save/restore_state() functions

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

cso: add new cso_save/restore_state() functions

cso_save_state() takes a bitmask of state items to save.  Calling
cso_restore_state() restores those states.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

cso: remove comment

There's a similar comment just a few lines before.

st/mesa: use new cso_set_viewport_dims() helper

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

cso: add new cso_set_viewport_dims() helper

To simplify some viewport setting code in the state tracker.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: use 'cso' local var instead of st->cso_context

Just a little cleaner.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: consolidate quad drawing code

The glClear, glBitmap and glDrawPixels code now use a new st_draw_quad()
helper function.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: overhaul vertex setup for clearing, glDrawPixels, glBitmap

Define a new st_util_vertex structure which is a bit smaller (9 floats
versus the previous 12 floats per vertex).  Clean up the glClear,
glDrawPixels and glBitmap code that sets up the vertex data and does the
drawing so it's all very similar.  This can lead to more consolidation.

v2: add assertion that vertex buffer slot == 0 to catch possible future
change in cso_get_aux_vertex_buffer_slot() behavior.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

st/mesa: include u_draw.h, not u_draw_quad.h in st_draw.c

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

configure: Bail out on llvm-config component error

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Handle removal of LLVMAddTargetData in SVN revision 260919

LLVM removed LLVMAddTargetData for the 3.9 release in r260919.  For the two
places in mesa where this is called, only enable the lines when compiling
for less then 3.9.

For the radeon driver, I'm not sure how to check if any other LLVM calls need
to be adjusted.  I think since the target data used is extracted from the
LLVMModule, it isn't necessary to pass it back to LLVM again.

The code does compile, and at least for radeonsi does run OpenGL games.

[ Michel Dänzer: Move #if closer to LLVMAddTargetData in lp_bld_init.c,
  and add HAVE_LLVM < 0x0309 guards around now unused occurrences of TD
  and data_layout ]

Signed-off-by: Matthew Dawson <matthew@mjdsystems.ca>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>

i965: Expose logic telling if non-msrt mcs is supported

Alos use the opportunity to mark inputs constant. (Context has to be
given as read-write to intel_miptree_supports_non_msrt_fast_clear()
to support debug output).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965/gen9: Refactor msrt mcs initialization

This will be re-used to initialize auxiliary buffers in lossless
compression case.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Add a few assertions on lossless compression

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Add a flag telling color resolve pass to ignore CCS_E

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Add resolve option for lossless compression

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression (intel_miptree_is_lossless_compressed()).

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Allow fast clear to be used with lossless compression

v2 (Ben): Use combination of msaa_layout and number of samples
          instead of introducing explicit type for lossless
          compression.
v3 (Ben): Squash with "i965: Resolve color buffer also in
          lossless compression case" and clarify simple
          non-compressed fast clear case.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

i965: Add helper for detecting lossless compression

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>

Revert "i965: Restore vbo after color resolve during brw_try_draw_prims()"

This got pushed accidentally in the first place but wasn't reverted
as it didn't regress piglit but instead fixed one newly introduced
test exercising a corner in case in i965 driver. However, saving and
restoring vertex buffer context is complicated and requires more
thought.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94150

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Tapani Palli <tapani.palli@intel.com>

nvc0: initial support for GM20x GPUs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: implement support for maxwell texture headers

Adds support for the new TIC layout that's present on Maxwell GPUs,
heavily based on the code for the existing layout.

This code is required for GM20x support.  While GM10x supports the older
layout still, this commit switches it to use the updated version instead.

Piglit testing shows zero regressions on GM107.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: import maxwell texture header definitions from rnndb

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50-: split tic format specification

We previously stored texture format information as it would appear in
the TIC.

We're about to support the new TIC layout that appeared with Maxwell,
so it makes more sense to store the data in a split-out format.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50-: remove nv50_texture.xml.h

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: switch nvc0_tex.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: switch nvc0_surface.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: switch nv50_tex.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: switch nv50_surface.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: switch nv50_state.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50-: switch nv50_formats.c to updated g80_texture.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: import updated g80_texture.xml.h from rnndb

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50-: remove nv50_defs.xml.h

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50-: switch nv50_formats.c to updated g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50-: improved macros to handle format specification

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50-: separate vertex formats from surface format descriptions

We've previously had identical naming between vertex and texture
formats, so it mostly made sense to define these together.

However, upcoming patches are going to transition the driver over to
using updated texture header definitions using NVIDIA's naming, and this
will no longer be the case.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: remove unnecessary includes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: switch nvc0_tex.c to updated g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: switch nvc0_surface.c to updated g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: remove unnecessary include

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: switch nv50_transfer.c to g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: switch nv50_tex.c to updated g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: switch nv50_surface.c to updated g80_defs.xml.h

Verified (binary diff) to produce identical code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: import updated g80_defs.xml.h from rnndb

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: count shader images in MaxCombinedShaderOutputResources

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: enable GL image extensions when backend supports them

This enables ARB_shader_image_load_store and ARB_shader_image_size when
the backend claims support for these. It will also implicitly enable the
image component of ARB_shader_texture_image_samples.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>