yosys.git
5 years agoread_aiger to work with symbol table
Eddie Hung [Fri, 22 Feb 2019 01:01:07 +0000 (17:01 -0800)]
read_aiger to work with symbol table

5 years agoRevert "abc9 to write_xaiger -symbols, not -map"
Eddie Hung [Thu, 21 Feb 2019 22:58:40 +0000 (14:58 -0800)]
Revert "abc9 to write_xaiger -symbols, not -map"

This reverts commit 04429f8152ae64de050580ec20db60ac6dc1c0e1.

5 years agoRemove irrelevant citations
Eddie Hung [Thu, 21 Feb 2019 22:41:11 +0000 (14:41 -0800)]
Remove irrelevant citations

5 years agoAdd attribution
Eddie Hung [Thu, 21 Feb 2019 22:40:13 +0000 (14:40 -0800)]
Add attribution

5 years agoabc9 to not select anything extra, and pop selection after final clean
Eddie Hung [Thu, 21 Feb 2019 22:38:52 +0000 (14:38 -0800)]
abc9 to not select anything extra, and pop selection after final clean

5 years agoabc9 to write_xaiger -symbols, not -map
Eddie Hung [Thu, 21 Feb 2019 22:28:36 +0000 (14:28 -0800)]
abc9 to write_xaiger -symbols, not -map

5 years agoMerge branch 'read_aiger' into xaig
Eddie Hung [Thu, 21 Feb 2019 22:27:32 +0000 (14:27 -0800)]
Merge branch 'read_aiger' into xaig

5 years agoMerge branch 'read_aiger' of https://github.com/eddiehung/yosys into read_aiger
Eddie Hung [Thu, 21 Feb 2019 22:17:48 +0000 (14:17 -0800)]
Merge branch 'read_aiger' of https://github.com/eddiehung/yosys into read_aiger

5 years agoMerge branch 'read_aiger' into xaig
Eddie Hung [Thu, 21 Feb 2019 22:14:28 +0000 (14:14 -0800)]
Merge branch 'read_aiger' into xaig

5 years agoabc9 to use &mfs
Eddie Hung [Thu, 21 Feb 2019 21:16:24 +0000 (13:16 -0800)]
abc9 to use &mfs

5 years agoRevert "tests/simple to also do LUT synth"
Eddie Hung [Thu, 21 Feb 2019 21:15:45 +0000 (13:15 -0800)]
Revert "tests/simple to also do LUT synth"

This reverts commit 5994382a20a0b7e890d22d032eecb39b61e0b3ce.

5 years agoMerge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Thu, 21 Feb 2019 19:23:00 +0000 (11:23 -0800)]
Merge remote-tracking branch 'origin/master' into xaig

5 years agotests/simple to also do LUT synth
Eddie Hung [Thu, 21 Feb 2019 19:16:57 +0000 (11:16 -0800)]
tests/simple to also do LUT synth

5 years agoWorking simple_abc9 tests
Eddie Hung [Thu, 21 Feb 2019 19:16:25 +0000 (11:16 -0800)]
Working simple_abc9 tests

5 years agoabc9 to only disconnect output ports of AND and NOT gates
Eddie Hung [Thu, 21 Feb 2019 19:15:47 +0000 (11:15 -0800)]
abc9 to only disconnect output ports of AND and NOT gates

5 years agowrite_xaiger to use original bit for co, not sigmap()-ed bit
Eddie Hung [Thu, 21 Feb 2019 19:15:25 +0000 (11:15 -0800)]
write_xaiger to use original bit for co, not sigmap()-ed bit

5 years agoAdd abc9.v testcase to simple_abc9
Eddie Hung [Thu, 21 Feb 2019 18:37:45 +0000 (10:37 -0800)]
Add abc9.v testcase to simple_abc9

5 years agoHotfix for 4c82ddf
Clifford Wolf [Thu, 21 Feb 2019 18:27:23 +0000 (19:27 +0100)]
Hotfix for 4c82ddf

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #822 from litghost/expand_setundef
Clifford Wolf [Thu, 21 Feb 2019 18:24:16 +0000 (19:24 +0100)]
Merge pull request #822 from litghost/expand_setundef

Add -params mode to force undef parameters in selected cells.

5 years agoAdd -params mode to force undef parameters in selected cells.
Keith Rothman [Thu, 21 Feb 2019 18:16:38 +0000 (10:16 -0800)]
Add -params mode to force undef parameters in selected cells.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
5 years agoMerge pull request #818 from YosysHQ/clifford/dffsrfix
Clifford Wolf [Thu, 21 Feb 2019 17:58:44 +0000 (18:58 +0100)]
Merge pull request #818 from YosysHQ/clifford/dffsrfix

Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

5 years agoMerge pull request #786 from YosysHQ/pmgen
Clifford Wolf [Thu, 21 Feb 2019 17:56:01 +0000 (18:56 +0100)]
Merge pull request #786 from YosysHQ/pmgen

Pattern Matcher Generator and iCE40 DSP Mapper

5 years agoFix typo in passes/pmgen/README.md
Clifford Wolf [Thu, 21 Feb 2019 17:50:02 +0000 (18:50 +0100)]
Fix typo in passes/pmgen/README.md

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge pull request #821 from eddiehung/dff_init
Clifford Wolf [Thu, 21 Feb 2019 17:46:58 +0000 (18:46 +0100)]
Merge pull request #821 from eddiehung/dff_init

Revert "Add -B option to autotest.sh to append to backend_opts"

5 years agoMerge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig
Eddie Hung [Thu, 21 Feb 2019 17:31:17 +0000 (09:31 -0800)]
Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig

5 years agoRevert "Add -B option to autotest.sh to append to backend_opts"
Eddie Hung [Thu, 21 Feb 2019 17:22:29 +0000 (09:22 -0800)]
Revert "Add -B option to autotest.sh to append to backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.

5 years agoFix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816
Clifford Wolf [Thu, 21 Feb 2019 12:48:23 +0000 (13:48 +0100)]
Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoBugfix in ice40_dsp
Clifford Wolf [Thu, 21 Feb 2019 12:28:46 +0000 (13:28 +0100)]
Bugfix in ice40_dsp

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoABC -> ABC9
Eddie Hung [Thu, 21 Feb 2019 01:36:57 +0000 (17:36 -0800)]
ABC -> ABC9

5 years agoabc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_
Eddie Hung [Thu, 21 Feb 2019 01:33:35 +0000 (17:33 -0800)]
abc9 to disconnect mapped_mods POs correctly, and do not count $_NOT_

5 years agoread_aiger to not do -purge for clean
Eddie Hung [Thu, 21 Feb 2019 01:33:04 +0000 (17:33 -0800)]
read_aiger to not do -purge for clean

5 years agoMerge pull request #817 from eddiehung/dff_init
Eddie Hung [Thu, 21 Feb 2019 01:26:56 +0000 (17:26 -0800)]
Merge pull request #817 from eddiehung/dff_init

Cleanup #805

5 years agolut/not/and suffix to be ${lut,not,and}
Eddie Hung [Thu, 21 Feb 2019 00:30:30 +0000 (16:30 -0800)]
lut/not/and suffix to be ${lut,not,and}

5 years agosimple_abc9 tests to now preserve memories
Eddie Hung [Thu, 21 Feb 2019 00:19:01 +0000 (16:19 -0800)]
simple_abc9 tests to now preserve memories

5 years agoread_aiger to also rename 0 index lut when wideports
Eddie Hung [Thu, 21 Feb 2019 00:17:22 +0000 (16:17 -0800)]
read_aiger to also rename 0 index lut when wideports

5 years agoRemove swap file
Eddie Hung [Thu, 21 Feb 2019 00:17:01 +0000 (16:17 -0800)]
Remove swap file

5 years agoRemove simple_defparam tests
Eddie Hung [Wed, 20 Feb 2019 23:45:45 +0000 (15:45 -0800)]
Remove simple_defparam tests

5 years agowrite_aiger: fix CI/CO and symbols
Eddie Hung [Wed, 20 Feb 2019 23:35:32 +0000 (15:35 -0800)]
write_aiger: fix CI/CO and symbols

5 years agoMove tests/techmap/abc9 to simple_abc9
Eddie Hung [Wed, 20 Feb 2019 23:34:59 +0000 (15:34 -0800)]
Move tests/techmap/abc9 to simple_abc9

5 years agoAdd tests/simple_abc9
Eddie Hung [Wed, 20 Feb 2019 23:31:35 +0000 (15:31 -0800)]
Add tests/simple_abc9

5 years agoabc9 to cope with multiple modules
Eddie Hung [Wed, 20 Feb 2019 20:56:15 +0000 (12:56 -0800)]
abc9 to cope with multiple modules

5 years agoabc9 to use & syntax for -fast, and name fixes
Eddie Hung [Wed, 20 Feb 2019 20:40:17 +0000 (12:40 -0800)]
abc9 to use & syntax for -fast, and name fixes

5 years agoread_aiger: new naming fixes
Eddie Hung [Wed, 20 Feb 2019 20:39:51 +0000 (12:39 -0800)]
read_aiger: new naming fixes

5 years agoread_aiger to name wires with internal name, less likely to clash
Eddie Hung [Wed, 20 Feb 2019 19:22:56 +0000 (11:22 -0800)]
read_aiger to name wires with internal name, less likely to clash

5 years agowrite_xaiger to not write latches, CO/PO fixes
Eddie Hung [Wed, 20 Feb 2019 19:09:13 +0000 (11:09 -0800)]
write_xaiger to not write latches, CO/PO fixes

5 years agosynth to take -abc9 argument
Eddie Hung [Wed, 20 Feb 2019 19:08:49 +0000 (11:08 -0800)]
synth to take -abc9 argument

5 years agoAdd ice40 test_dsp_map test case generator
Clifford Wolf [Wed, 20 Feb 2019 16:18:59 +0000 (17:18 +0100)]
Add ice40 test_dsp_map test case generator

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd "synth_ice40 -dsp"
Clifford Wolf [Wed, 20 Feb 2019 15:42:27 +0000 (16:42 +0100)]
Add "synth_ice40 -dsp"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd FF support to wreduce
Clifford Wolf [Wed, 20 Feb 2019 15:36:42 +0000 (16:36 +0100)]
Add FF support to wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove iCE40 SB_MAC16 model
Clifford Wolf [Wed, 20 Feb 2019 11:55:20 +0000 (12:55 +0100)]
Improve iCE40 SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoDetect and reject cases that do not map well to iCE40 DSPs (yet)
Clifford Wolf [Wed, 20 Feb 2019 10:18:19 +0000 (11:18 +0100)]
Detect and reject cases that do not map well to iCE40 DSPs (yet)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoabc9 to cope with indexed wires when creating $lut from $_NOT_
Eddie Hung [Wed, 20 Feb 2019 00:06:03 +0000 (16:06 -0800)]
abc9 to cope with indexed wires when creating $lut from $_NOT_

5 years agoAdd aiger tests to make tests
Eddie Hung [Tue, 19 Feb 2019 23:25:47 +0000 (15:25 -0800)]
Add aiger tests to make tests

5 years agoAdd a quick abc9 test
Eddie Hung [Tue, 19 Feb 2019 23:25:03 +0000 (15:25 -0800)]
Add a quick abc9 test

5 years agoSame for ascii AIGERs too
Eddie Hung [Tue, 19 Feb 2019 23:15:50 +0000 (15:15 -0800)]
Same for ascii AIGERs too

5 years agoread_aiger to cope with non-unique POs
Eddie Hung [Tue, 19 Feb 2019 23:14:08 +0000 (15:14 -0800)]
read_aiger to cope with non-unique POs

5 years agoMerge branch 'master' into xaig
Eddie Hung [Tue, 19 Feb 2019 22:20:04 +0000 (14:20 -0800)]
Merge branch 'master' into xaig

5 years agoMerge branch 'master' into read_aiger
Eddie Hung [Tue, 19 Feb 2019 20:36:10 +0000 (12:36 -0800)]
Merge branch 'master' into read_aiger

5 years agoMerge branch 'master' into read_aiger
Eddie Hung [Tue, 19 Feb 2019 20:33:22 +0000 (12:33 -0800)]
Merge branch 'master' into read_aiger

5 years agoMerge pull request #805 from eddiehung/dff_init
Eddie Hung [Tue, 19 Feb 2019 20:32:40 +0000 (12:32 -0800)]
Merge pull request #805 from eddiehung/dff_init

write_verilog to write initial statement for initial flop state

5 years agoabc9 to replace $_NOT_ with $lut
Eddie Hung [Tue, 19 Feb 2019 20:30:20 +0000 (12:30 -0800)]
abc9 to replace $_NOT_ with $lut

5 years agoread_aiger to create sane $lut names, and rename when renaming driving wire
Eddie Hung [Tue, 19 Feb 2019 20:27:50 +0000 (12:27 -0800)]
read_aiger to create sane $lut names, and rename when renaming driving wire

5 years agoAdd comment
Eddie Hung [Tue, 19 Feb 2019 18:24:55 +0000 (10:24 -0800)]
Add comment

5 years agoGet rid of boost dep, fix the FIXMEs for Win32?
Eddie Hung [Tue, 19 Feb 2019 18:19:53 +0000 (10:19 -0800)]
Get rid of boost dep, fix the FIXMEs for Win32?

5 years agoFix for using POSIX basename
Eddie Hung [Tue, 19 Feb 2019 17:02:37 +0000 (09:02 -0800)]
Fix for using POSIX basename

5 years agoAdd first draft of functional SB_MAC16 model
Clifford Wolf [Tue, 19 Feb 2019 12:42:21 +0000 (13:42 +0100)]
Add first draft of functional SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMissing OSX headers?
Eddie Hung [Mon, 18 Feb 2019 04:59:53 +0000 (20:59 -0800)]
Missing OSX headers?

5 years agoRevert "Missing headers for Xcode?"
Eddie Hung [Mon, 18 Feb 2019 04:59:15 +0000 (20:59 -0800)]
Revert "Missing headers for Xcode?"

This reverts commit c23e3f07517d4818d9ab1b532250353492cf50c2.

5 years agoMerge branch 'dff_init' into read_aiger
Eddie Hung [Mon, 18 Feb 2019 04:49:56 +0000 (20:49 -0800)]
Merge branch 'dff_init' into read_aiger

5 years agoInstead of INIT param on cells, use initial statement with hier ref as
Eddie Hung [Sun, 17 Feb 2019 20:18:12 +0000 (12:18 -0800)]
Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf

5 years agoRevert "Add INIT parameter to all ff/latch cells"
Eddie Hung [Sun, 17 Feb 2019 20:11:52 +0000 (12:11 -0800)]
Revert "Add INIT parameter to all ff/latch cells"

This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.

5 years agoread_aiger to ignore line after ands for ascii, not binary
Eddie Hung [Sun, 17 Feb 2019 20:07:14 +0000 (12:07 -0800)]
read_aiger to ignore line after ands for ascii, not binary

5 years agoOne more merge conflict
Eddie Hung [Sun, 17 Feb 2019 19:50:55 +0000 (11:50 -0800)]
One more merge conflict

5 years agoMerge branch 'dff_init' into read_aiger
Eddie Hung [Sun, 17 Feb 2019 19:49:13 +0000 (11:49 -0800)]
Merge branch 'dff_init' into read_aiger

5 years agoMerge https://github.com/YosysHQ/yosys into dff_init
Eddie Hung [Sun, 17 Feb 2019 19:49:06 +0000 (11:49 -0800)]
Merge https://github.com/YosysHQ/yosys into dff_init

5 years agoMerge https://github.com/YosysHQ/yosys into read_aiger
Eddie Hung [Sun, 17 Feb 2019 19:44:01 +0000 (11:44 -0800)]
Merge https://github.com/YosysHQ/yosys into read_aiger

5 years agoAdd actual DSP inference to ice40_dsp pass
Clifford Wolf [Sun, 17 Feb 2019 14:35:48 +0000 (15:35 +0100)]
Add actual DSP inference to ice40_dsp pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoMerge branch 'master' of github.com:YosysHQ/yosys into pmgen
Clifford Wolf [Sun, 17 Feb 2019 11:10:19 +0000 (12:10 +0100)]
Merge branch 'master' of github.com:YosysHQ/yosys into pmgen

5 years agoMerge pull request #811 from ucb-bar/firrtlfixes
Clifford Wolf [Sun, 17 Feb 2019 10:39:14 +0000 (11:39 +0100)]
Merge pull request #811 from ucb-bar/firrtlfixes

Update cells supported for verilog to FIRRTL conversion.

5 years agoGet rid of debugging stuff in abc9
Eddie Hung [Sun, 17 Feb 2019 06:25:22 +0000 (22:25 -0800)]
Get rid of debugging stuff in abc9

5 years agoIn read_xaiger, do not construct ConstEval for every LUT
Eddie Hung [Sun, 17 Feb 2019 06:22:29 +0000 (22:22 -0800)]
In read_xaiger, do not construct ConstEval for every LUT

5 years agoCleanup
Eddie Hung [Sun, 17 Feb 2019 06:22:17 +0000 (22:22 -0800)]
Cleanup

5 years agoread_aiger to ignore output = input of same wire; also create new output for differen...
Eddie Hung [Sun, 17 Feb 2019 05:53:03 +0000 (21:53 -0800)]
read_aiger to ignore output = input of same wire; also create new output for different wire

5 years agoCleanup
Eddie Hung [Sun, 17 Feb 2019 05:09:48 +0000 (21:09 -0800)]
Cleanup

5 years agowrite_xaiger to support non-bit cell connections, and cope with COs for -O
Eddie Hung [Sun, 17 Feb 2019 05:00:39 +0000 (21:00 -0800)]
write_xaiger to support non-bit cell connections, and cope with COs for -O

5 years agoabc9 to write_aiger with -O option, and ignore dummy outputs
Eddie Hung [Sun, 17 Feb 2019 04:09:40 +0000 (20:09 -0800)]
abc9 to write_aiger with -O option, and ignore dummy outputs

5 years agowrite_aiger -O to write dummy output as __dummy_o__
Eddie Hung [Sun, 17 Feb 2019 04:08:59 +0000 (20:08 -0800)]
write_aiger -O to write dummy output as __dummy_o__

5 years agoabc9 to handle comb loops, cope with constant outputs, disconnect using new wire
Eddie Hung [Sat, 16 Feb 2019 21:47:38 +0000 (13:47 -0800)]
abc9 to handle comb loops, cope with constant outputs, disconnect using new wire

5 years agoread_aiger to disable log_debug
Eddie Hung [Sat, 16 Feb 2019 21:45:51 +0000 (13:45 -0800)]
read_aiger to disable log_debug

5 years agoexpose command to not skip 'internal' wires beginning with '$'
Eddie Hung [Sat, 16 Feb 2019 21:45:17 +0000 (13:45 -0800)]
expose command to not skip 'internal' wires beginning with '$'

5 years agoread_xaiger() to use f.read() not readsome()
Eddie Hung [Sat, 16 Feb 2019 16:58:25 +0000 (08:58 -0800)]
read_xaiger() to use f.read() not readsome()

5 years agoabc9 to cope with non-wideports, count cells properly
Eddie Hung [Sat, 16 Feb 2019 16:53:06 +0000 (08:53 -0800)]
abc9 to cope with non-wideports, count cells properly

5 years agoTidy up write_xaiger
Eddie Hung [Sat, 16 Feb 2019 16:48:33 +0000 (08:48 -0800)]
Tidy up write_xaiger

5 years agowrite_aiger() to perform CI/CO post-processing and fix symbols
Eddie Hung [Sat, 16 Feb 2019 16:46:25 +0000 (08:46 -0800)]
write_aiger() to perform CI/CO post-processing and fix symbols

5 years agoread_aiger() to cope with constant outputs, mixed wideports, do cleaning
Eddie Hung [Sat, 16 Feb 2019 16:44:11 +0000 (08:44 -0800)]
read_aiger() to cope with constant outputs, mixed wideports, do cleaning

5 years agoMove lookup inside if
Eddie Hung [Fri, 15 Feb 2019 23:23:26 +0000 (15:23 -0800)]
Move lookup inside if

5 years agoFixes needed for DFF circuits
Eddie Hung [Fri, 15 Feb 2019 23:22:18 +0000 (15:22 -0800)]
Fixes needed for DFF circuits

5 years agoRefactor
Eddie Hung [Fri, 15 Feb 2019 21:00:13 +0000 (13:00 -0800)]
Refactor

5 years agoCope with width != 1 when re-mapping cells
Eddie Hung [Fri, 15 Feb 2019 20:55:52 +0000 (12:55 -0800)]
Cope with width != 1 when re-mapping cells

5 years agoRemoved unused variables, functions.
Jim Lawson [Fri, 15 Feb 2019 20:00:28 +0000 (12:00 -0800)]
Removed unused variables, functions.