Tim Newsome [Fri, 9 Jun 2017 17:00:36 +0000 (10:00 -0700)]
Return success on writes to abstractauto
This bug was exposed by newer OpenOCD which actually checks the result.
Tim Newsome [Thu, 8 Jun 2017 20:31:04 +0000 (13:31 -0700)]
Merge pull request #110 from riscv/debug_rom_build
`make clean && make` works again in debug_rom
Tim Newsome [Thu, 8 Jun 2017 20:28:48 +0000 (13:28 -0700)]
Merge pull request #111 from riscv/dtm_reset_error
Reset to "success" instead of "error."
Tim Newsome [Thu, 8 Jun 2017 20:05:01 +0000 (13:05 -0700)]
Reset to "success" instead of "error."
OpenOCD actually checks this initial value now, and there's no reason
for it to indicate error.
Tim Newsome [Thu, 8 Jun 2017 19:58:11 +0000 (12:58 -0700)]
`make clean && make` works again in debug_rom
Andrew Waterman [Wed, 7 Jun 2017 21:17:58 +0000 (14:17 -0700)]
Forbid S-mode execution from user memory
https://github.com/riscv/riscv-isa-manual/commit/
285c81746fe664060b62ae0584865dbfa9f42e1a
Palmer Dabbelt [Mon, 5 Jun 2017 19:57:58 +0000 (12:57 -0700)]
Merge pull request #108 from riscv/dtc-error
Configure should fail if device-tree-compiler is not installed
Andrew Waterman [Mon, 5 Jun 2017 19:55:26 +0000 (12:55 -0700)]
Configure should fail if device-tree-compiler is not installed
Fixes #107
Andrew Waterman [Thu, 25 May 2017 09:19:46 +0000 (02:19 -0700)]
minNum -> minimumNumber
Palmer Dabbelt [Tue, 23 May 2017 15:47:43 +0000 (08:47 -0700)]
Merge pull request #104 from riscv/disable-werror
Disable -Werror when building
Palmer Dabbelt [Tue, 23 May 2017 15:33:20 +0000 (08:33 -0700)]
Disable -Werror when building
This has a tendency to blow up on other platforms.
Palmer Dabbelt [Wed, 17 May 2017 20:07:47 +0000 (13:07 -0700)]
Merge remote-tracking branch 'origin/priv-1.10'
Palmer Dabbelt [Tue, 16 May 2017 16:33:40 +0000 (09:33 -0700)]
Merge remote-tracking branch 'origin/debug-0.13' into priv-1.10
Palmer Dabbelt [Tue, 16 May 2017 01:33:27 +0000 (18:33 -0700)]
Better error message when doing DMI operations and we're busy
Megan Wachs [Mon, 15 May 2017 17:06:08 +0000 (10:06 -0700)]
debug: whitespace errors
Megan Wachs [Mon, 15 May 2017 16:53:42 +0000 (09:53 -0700)]
Merge branch 'debug-0.13' into HEAD
Andrew Waterman [Sun, 14 May 2017 05:37:22 +0000 (22:37 -0700)]
Make C.LI/C.LUI trapping behavior match spec
Andrew Waterman [Fri, 5 May 2017 23:27:08 +0000 (16:27 -0700)]
UXL=SXL=MXL
https://github.com/riscv/riscv-isa-manual/commit/
326bec83de23f4d2daf24cfed6b5251748cad632
Andrew Waterman [Fri, 5 May 2017 21:39:26 +0000 (14:39 -0700)]
Trap superpage PTEs when PPN LSBs are set
Kito Cheng [Wed, 3 May 2017 09:58:54 +0000 (17:58 +0800)]
Add missing include for devices.h
- https://github.com/riscv/riscv-tools/issues/69
Andrew Waterman [Mon, 1 May 2017 23:44:47 +0000 (16:44 -0700)]
Fix segfault when accessing bad memory addresses
Andrew Waterman [Mon, 1 May 2017 21:44:42 +0000 (14:44 -0700)]
Set default entry point from ELF
Andrew Waterman [Mon, 1 May 2017 06:45:27 +0000 (23:45 -0700)]
Add option to set start pc
Andrew Waterman [Mon, 1 May 2017 05:03:15 +0000 (22:03 -0700)]
Support more flexible main memory allocation
Andrew Waterman [Mon, 1 May 2017 00:37:06 +0000 (17:37 -0700)]
Store both host & target address in soft TLB
Palmer Dabbelt [Wed, 26 Apr 2017 21:22:00 +0000 (14:22 -0700)]
Merge pull request #96 from riscv/ndmreset
Updates to match the latest debug spec
Palmer Dabbelt [Wed, 26 Apr 2017 16:14:07 +0000 (09:14 -0700)]
Remove a debugging printf
Palmer Dabbelt [Wed, 26 Apr 2017 16:13:49 +0000 (09:13 -0700)]
Don't spin on the remote bitbang reads
Palmer Dabbelt [Wed, 26 Apr 2017 16:13:19 +0000 (09:13 -0700)]
Handle abstractcs.busy
Palmer Dabbelt [Wed, 19 Apr 2017 23:59:10 +0000 (16:59 -0700)]
Have ndmreset reset the processor
Andrew Waterman [Tue, 25 Apr 2017 18:40:59 +0000 (11:40 -0700)]
FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X
Andrew Waterman [Tue, 25 Apr 2017 18:40:39 +0000 (11:40 -0700)]
Remove hret instruction
Palmer Dabbelt [Mon, 24 Apr 2017 15:15:04 +0000 (08:15 -0700)]
Merge pull request #94 from riscv/commitlog
Fix builds with "--enable-commitlog"
Palmer Dabbelt [Wed, 19 Apr 2017 22:48:42 +0000 (15:48 -0700)]
Fix builds with "--enable-commitlog"
Megan Wachs [Tue, 18 Apr 2017 21:34:51 +0000 (14:34 -0700)]
debug: move remote_bitbang into riscv
Megan Wachs [Tue, 18 Apr 2017 21:34:21 +0000 (14:34 -0700)]
debug: Remove duplicate remote_bitbang file
Megan Wachs [Tue, 18 Apr 2017 21:04:57 +0000 (14:04 -0700)]
debug: Able to successfully examine a single hart.
Megan Wachs [Tue, 18 Apr 2017 20:47:10 +0000 (13:47 -0700)]
debug: Use Debug-Module specific constants instead of global defines.
Megan Wachs [Tue, 18 Apr 2017 18:44:00 +0000 (11:44 -0700)]
debug: Add fence and fence.i to ensure Debug RAM is ready.
Megan Wachs [Tue, 18 Apr 2017 18:34:31 +0000 (11:34 -0700)]
debug: Checkpoint which somewhat works with OpenOCD v13, but still has some bugs.
Megan Wachs [Tue, 18 Apr 2017 04:21:35 +0000 (21:21 -0700)]
debug: move the debug_rom defines to a seperate file
Megan Wachs [Tue, 18 Apr 2017 02:45:42 +0000 (19:45 -0700)]
debug: Use more unique debug ROM names
Megan Wachs [Tue, 18 Apr 2017 02:36:01 +0000 (19:36 -0700)]
debug: Use a more practical debug ROM
Megan Wachs [Tue, 18 Apr 2017 02:28:49 +0000 (19:28 -0700)]
debug: Move things around, but addresses now conflict with ROM.
Megan Wachs [Mon, 17 Apr 2017 22:19:29 +0000 (15:19 -0700)]
debug: consider COMMAND.transfer bit, and implment HARTINFO
Megan Wachs [Mon, 17 Apr 2017 21:11:43 +0000 (14:11 -0700)]
debug: Compiles again with new debug_defines.h file, but not tested.
Megan Wachs [Mon, 17 Apr 2017 18:31:31 +0000 (11:31 -0700)]
debug: bump the debug_defines to match spec
Megan Wachs [Mon, 17 Apr 2017 17:59:38 +0000 (10:59 -0700)]
Merge remote-tracking branch 'origin/priv-1.10' into HEAD
Andrew Waterman [Tue, 11 Apr 2017 00:35:24 +0000 (17:35 -0700)]
Implement new FP encoding
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
Andrew Waterman [Sat, 8 Apr 2017 00:57:59 +0000 (17:57 -0700)]
Implement vectored interrupt proposal
https://github.com/riscv/riscv-isa-manual/commit/
4dcaa944ba40e074d25516a157fc37f7491b71cc
Andrew Waterman [Thu, 6 Apr 2017 03:37:01 +0000 (20:37 -0700)]
Add --enable-misaligned option for misaligned ld/st support
Resolves #93
Yunsup Lee [Sat, 1 Apr 2017 02:14:19 +0000 (19:14 -0700)]
update encoding.h to get PMP updates
Andrew Waterman [Sat, 1 Apr 2017 02:11:52 +0000 (19:11 -0700)]
Update LICENSE copyright date
Wesley W. Terpstra [Thu, 30 Mar 2017 07:02:49 +0000 (00:02 -0700)]
fdt: move interrupt controller into its own node
Andrew Waterman [Tue, 28 Mar 2017 04:43:48 +0000 (21:43 -0700)]
Set badaddr=0 on illegal instruction traps
Andrew Waterman [Tue, 28 Mar 2017 04:21:57 +0000 (21:21 -0700)]
On EBREAK, set badaddr to pc
Andrew Waterman [Mon, 27 Mar 2017 21:30:22 +0000 (14:30 -0700)]
Separate page faults from physical memory access exceptions
Andrew Waterman [Sat, 25 Mar 2017 01:10:41 +0000 (18:10 -0700)]
Default to 2 GiB of memory
Andrew Waterman [Thu, 23 Mar 2017 20:24:10 +0000 (13:24 -0700)]
Require little-endian host
Wesley W. Terpstra [Wed, 22 Mar 2017 20:57:56 +0000 (13:57 -0700)]
riscv: replace rtc device with a real clint implementation
Wesley W. Terpstra [Wed, 22 Mar 2017 03:53:09 +0000 (20:53 -0700)]
sim: declare cores as interrupt-controllers for clint
Wesley W. Terpstra [Tue, 21 Mar 2017 23:47:13 +0000 (16:47 -0700)]
bootrom: set a0 to hartid and a1 to dtb before boot
Wesley W. Terpstra [Tue, 21 Mar 2017 23:44:43 +0000 (16:44 -0700)]
configstring: rename variables to dts
Wesley W. Terpstra [Tue, 21 Mar 2017 23:40:01 +0000 (16:40 -0700)]
riscv: remove dependency on num_cores
Wesley W. Terpstra [Tue, 21 Mar 2017 23:06:49 +0000 (16:06 -0700)]
bootrom: include compiled dtb
Wesley W. Terpstra [Sat, 4 Mar 2017 03:02:03 +0000 (19:02 -0800)]
sim: create DTS instead of config string
Wesley W. Terpstra [Sat, 4 Mar 2017 02:51:37 +0000 (18:51 -0800)]
sim: define emulated CPU clock rate to be 1GHz
Wesley W. Terpstra [Sat, 4 Mar 2017 02:50:37 +0000 (18:50 -0800)]
autoconf: put location of 'dtc' into config.h
Palmer Dabbelt [Tue, 21 Mar 2017 20:11:53 +0000 (13:11 -0700)]
spec bump
Andrew Waterman [Mon, 20 Mar 2017 07:48:16 +0000 (00:48 -0700)]
PUM -> SUM; expose MXR to S-mode
Andrew Waterman [Thu, 16 Mar 2017 19:36:32 +0000 (12:36 -0700)]
Simplify interrupt-stack discipline
https://github.com/riscv/riscv-isa-manual/commit/
f2ed45b1791bb602657adc2ea9ab5fc409c62542
Andrew Waterman [Mon, 13 Mar 2017 21:48:52 +0000 (14:48 -0700)]
Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
Andrew Waterman [Tue, 7 Mar 2017 09:58:41 +0000 (01:58 -0800)]
Don't overload illegal instruction trap in interactive code
Andrew Waterman [Mon, 27 Feb 2017 00:13:17 +0000 (16:13 -0800)]
Sv57 and Sv64 are not spec'd yet
Andrew Waterman [Sat, 25 Feb 2017 23:28:27 +0000 (15:28 -0800)]
New counter enable scheme
https://github.com/riscv/riscv-isa-manual/issues/10
Tim Newsome [Sat, 25 Feb 2017 18:17:14 +0000 (10:17 -0800)]
Update bits to latest spec.
Tim Newsome [Thu, 23 Feb 2017 20:12:25 +0000 (12:12 -0800)]
Implement halt request.
Also clean up some vestigial code.
Tim Newsome [Wed, 22 Feb 2017 04:22:10 +0000 (20:22 -0800)]
Improve debug performance.
It's still pitiful, but less so. (5KB/s download speed.)
The tweaks involve switching to the other context as soon as it might be
helpful. The two contexts are executing code, and handling JTAG TAP
input.
Tim Newsome [Wed, 22 Feb 2017 03:32:24 +0000 (19:32 -0800)]
Don't waste time spinning in place in debug mode
Andrew Waterman [Tue, 21 Feb 2017 02:48:35 +0000 (18:48 -0800)]
serialize simulator on wfi
This improves simulator perf when a thread is idle, or waiting on HTIF.
Andrew Waterman [Tue, 21 Feb 2017 01:17:17 +0000 (17:17 -0800)]
Take M-mode interrupts over S-mode interrupts
Andrew Waterman [Tue, 21 Feb 2017 01:16:58 +0000 (17:16 -0800)]
permit MMIO loads to MSIP bit
Andrew Waterman [Sun, 19 Feb 2017 01:24:04 +0000 (17:24 -0800)]
Make HW setting of PTE A/D bits optional (by configure arg)
https://github.com/riscv/riscv-isa-manual/issues/14
Andrew Waterman [Sat, 18 Feb 2017 11:03:10 +0000 (03:03 -0800)]
Spike uarch needs TLB flush after SPTBR write
Tim Newsome [Sat, 18 Feb 2017 02:50:44 +0000 (18:50 -0800)]
Compress log output of jump-to-self loops.
This helps hugely when reading "spike -l" output when debugging is going
on.
Tim Newsome [Thu, 16 Feb 2017 22:15:44 +0000 (14:15 -0800)]
Remove noisy debugs.
This version was able to download code, and run to a breakpoint.
Tim Newsome [Thu, 16 Feb 2017 04:41:06 +0000 (20:41 -0800)]
Set cmderr when data is accessed while busy.
Tim Newsome [Thu, 16 Feb 2017 03:05:20 +0000 (19:05 -0800)]
Implement autoexec. DMI op 2 is just write now.
Now passing MemTest{8,16,32,64}
Tim Newsome [Wed, 15 Feb 2017 23:45:20 +0000 (15:45 -0800)]
Implement resume (untested).
Andrew Waterman [Wed, 15 Feb 2017 11:06:34 +0000 (03:06 -0800)]
sfence.vm -> sfence.vma
Tim Newsome [Tue, 14 Feb 2017 05:29:26 +0000 (21:29 -0800)]
Implement program buffer preexec/postexec.
I only tested preexec.
Tim Newsome [Mon, 13 Feb 2017 19:13:04 +0000 (11:13 -0800)]
dbus -> dmi
Tim Newsome [Mon, 13 Feb 2017 17:53:23 +0000 (09:53 -0800)]
Abstract register read mostly working.
Fails with not supported for 128-bit.
Fails with exception (on rv32) with 64-bit.
Succeeds (on rv32) with 32-bit.
Tim Newsome [Sun, 12 Feb 2017 18:20:37 +0000 (10:20 -0800)]
Fix stack overflow and support --rbb-port=0
Tim Newsome [Sat, 11 Feb 2017 03:08:16 +0000 (19:08 -0800)]
Entering debug mode now jumps to "dynamic rom"
Tim Newsome [Fri, 10 Feb 2017 19:31:30 +0000 (11:31 -0800)]
Implement hartstatus field.
Tim Newsome [Fri, 10 Feb 2017 04:50:14 +0000 (20:50 -0800)]
Remove gdbserver support.
Maybe some day we can bring it back, implementing direct access into
registers and memory so it would be fast. That would be the way to
usefully debug code running in spike, as opposed to the way that mirrors
the actual debug design as it might be implemented in hardware.
Tim Newsome [Thu, 9 Feb 2017 04:40:52 +0000 (20:40 -0800)]
Add writable ibuf and data registers.
Tim Newsome [Thu, 9 Feb 2017 03:47:57 +0000 (19:47 -0800)]
Serve up a correct dmcontrol register.
Andrew Waterman [Wed, 8 Feb 2017 22:16:08 +0000 (14:16 -0800)]
Encode VM type in sptbr, not mstatus
https://github.com/riscv/riscv-isa-manual/issues/4
Also, refactor gdbserver code to not duplicate VM decoding logic.