bugzilla-daemon [Sun, 24 May 2020 18:33:28 +0000 (18:33 +0000)]
[libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline
bugzilla-daemon [Sun, 24 May 2020 18:26:59 +0000 (18:26 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 18:25:00 +0000 (18:25 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sun, 24 May 2020 18:24:28 +0000 (18:24 +0000)]
[libre-riscv-dev] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine
bugzilla-daemon [Sun, 24 May 2020 18:21:43 +0000 (18:21 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Sun, 24 May 2020 18:16:39 +0000 (18:16 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sun, 24 May 2020 18:13:01 +0000 (18:13 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 17:57:50 +0000 (17:57 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 16:45:13 +0000 (16:45 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 15:33:16 +0000 (15:33 +0000)]
[libre-riscv-dev] [Bug 346] New: simplified test link between compunits and regfile
Luke Kenneth Casson Leighton [Sun, 24 May 2020 15:30:16 +0000 (16:30 +0100)]
[libre-riscv-dev] idea for testing pipelines
bugzilla-daemon [Sun, 24 May 2020 15:07:49 +0000 (15:07 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 14:55:52 +0000 (14:55 +0000)]
[libre-riscv-dev] [Bug 345] New: define POWER9 regfiles
bugzilla-daemon [Sun, 24 May 2020 14:44:32 +0000 (14:44 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 14:37:24 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 14:27:44 +0000 (14:27 +0000)]
[libre-riscv-dev] [Bug 344] New: missing mtmsr and mfsprd
Luke Kenneth Casson Leighton [Sun, 24 May 2020 14:17:00 +0000 (15:17 +0100)]
[libre-riscv-dev] daily kan-ban update 24may2020
bugzilla-daemon [Sun, 24 May 2020 14:00:28 +0000 (14:00 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 13:46:48 +0000 (13:46 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 13:11:48 +0000 (13:11 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
bugzilla-daemon [Sun, 24 May 2020 12:11:31 +0000 (12:11 +0000)]
[libre-riscv-dev] [Bug 337] Convention for register outputs in *OutputData structures is to use "Data"
bugzilla-daemon [Sun, 24 May 2020 03:43:22 +0000 (03:43 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 24 May 2020 03:41:42 +0000 (03:41 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 24 May 2020 03:33:37 +0000 (03:33 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 03:33:37 +0000 (03:33 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Sun, 24 May 2020 03:33:20 +0000 (03:33 +0000)]
[libre-riscv-dev] [Bug 343] New: compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Sun, 24 May 2020 01:46:13 +0000 (01:46 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Sun, 24 May 2020 01:01:28 +0000 (02:01 +0100)]
[libre-riscv-dev] Fwd: [OpenPOWER-HDL-Cores] POWER9 ISA opcode usage statistics
bugzilla-daemon [Sat, 23 May 2020 22:58:18 +0000 (22:58 +0000)]
[libre-riscv-dev] [Bug 341] unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)
bugzilla-daemon [Sat, 23 May 2020 23:17:09 +0000 (23:17 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sat, 23 May 2020 23:10:34 +0000 (23:10 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Sat, 23 May 2020 23:01:58 +0000 (00:01 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Cole Poirier [Sat, 23 May 2020 22:59:34 +0000 (15:59 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
bugzilla-daemon [Sat, 23 May 2020 22:58:18 +0000 (22:58 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sat, 23 May 2020 22:57:47 +0000 (22:57 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sat, 23 May 2020 22:57:30 +0000 (22:57 +0000)]
[libre-riscv-dev] [Bug 342] New: formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sat, 23 May 2020 22:52:45 +0000 (22:52 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 23 May 2020 22:52:45 +0000 (22:52 +0000)]
[libre-riscv-dev] [Bug 341] unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)
bugzilla-daemon [Sat, 23 May 2020 22:50:53 +0000 (22:50 +0000)]
[libre-riscv-dev] [Bug 341] New: unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:39:43 +0000 (23:39 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:36:57 +0000 (23:36 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
bugzilla-daemon [Sat, 23 May 2020 22:35:15 +0000 (22:35 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
Cole Poirier [Sat, 23 May 2020 22:32:49 +0000 (15:32 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:27:42 +0000 (23:27 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:23:19 +0000 (23:23 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Cole Poirier [Sat, 23 May 2020 22:23:22 +0000 (15:23 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Cole Poirier [Sat, 23 May 2020 22:20:46 +0000 (15:20 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:18:08 +0000 (23:18 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:17:16 +0000 (23:17 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:16:41 +0000 (23:16 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:16:10 +0000 (23:16 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:15:37 +0000 (23:15 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 22:14:37 +0000 (23:14 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Cesar Strauss [Sat, 23 May 2020 22:08:20 +0000 (19:08 -0300)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Cole Poirier [Sat, 23 May 2020 21:38:59 +0000 (14:38 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Cole Poirier [Sat, 23 May 2020 21:21:59 +0000 (14:21 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
bugzilla-daemon [Sat, 23 May 2020 21:01:34 +0000 (21:01 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
Luke Kenneth Casson Leighton [Sat, 23 May 2020 20:59:54 +0000 (21:59 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 20:57:39 +0000 (21:57 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
bugzilla-daemon [Sat, 23 May 2020 20:52:31 +0000 (20:52 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Michael Nolan [Sat, 23 May 2020 20:36:06 +0000 (16:36 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
bugzilla-daemon [Sat, 23 May 2020 20:30:18 +0000 (20:30 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
Cole Poirier [Sat, 23 May 2020 20:15:14 +0000 (13:15 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
bugzilla-daemon [Sat, 23 May 2020 19:39:57 +0000 (19:39 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 23 May 2020 19:16:28 +0000 (19:16 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 23 May 2020 19:09:27 +0000 (19:09 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 23 May 2020 18:43:28 +0000 (18:43 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
Luke Kenneth Casson Leighton [Sat, 23 May 2020 18:23:05 +0000 (19:23 +0100)]
[libre-riscv-dev] Function Units "patch-up" linking to Comp Unit code
Cole Poirier [Sat, 23 May 2020 18:16:27 +0000 (11:16 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 22may2020
bugzilla-daemon [Sat, 23 May 2020 15:23:16 +0000 (15:23 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Sat, 23 May 2020 15:17:16 +0000 (15:17 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Sat, 23 May 2020 15:15:02 +0000 (16:15 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Tobias Platen [Sat, 23 May 2020 14:56:20 +0000 (16:56 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 14:29:56 +0000 (15:29 +0100)]
[libre-riscv-dev] daily kan-ban update 23may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 14:21:27 +0000 (15:21 +0100)]
Re: [libre-riscv-dev] Priority Encoder for Cesar
Cesar Strauss [Sat, 23 May 2020 14:12:57 +0000 (11:12 -0300)]
[libre-riscv-dev] Priority Encoder for Cesar
bugzilla-daemon [Sat, 23 May 2020 13:40:18 +0000 (13:40 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Sat, 23 May 2020 13:28:54 +0000 (13:28 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Sat, 23 May 2020 13:07:12 +0000 (13:07 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sat, 23 May 2020 12:51:01 +0000 (12:51 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Sat, 23 May 2020 12:08:02 +0000 (13:08 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 22may2020
Cesar Strauss [Sat, 23 May 2020 11:53:18 +0000 (08:53 -0300)]
Re: [libre-riscv-dev] daily kan-ban update 22may2020
Luke Kenneth Casson Leighton [Sat, 23 May 2020 11:03:31 +0000 (12:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 22may2020
bugzilla-daemon [Sat, 23 May 2020 10:59:17 +0000 (10:59 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Sat, 23 May 2020 10:36:06 +0000 (10:36 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
Cesar Strauss [Sat, 23 May 2020 10:24:15 +0000 (07:24 -0300)]
Re: [libre-riscv-dev] daily kan-ban update 22may2020
bugzilla-daemon [Sat, 23 May 2020 03:06:19 +0000 (03:06 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:46:31 +0000 (03:46 +0100)]
Re: [libre-riscv-dev] dns entries for talos server & server maintenance
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:41:33 +0000 (03:41 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 22may2020
Cesar Strauss [Sat, 23 May 2020 01:56:25 +0000 (22:56 -0300)]
Re: [libre-riscv-dev] daily kan-ban update 22may2020
bugzilla-daemon [Sat, 23 May 2020 01:29:34 +0000 (01:29 +0000)]
[libre-riscv-dev] [Bug 313] Create Branch Pipeline for POWER9
bugzilla-daemon [Sat, 23 May 2020 01:25:48 +0000 (01:25 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
bugzilla-daemon [Sat, 23 May 2020 01:21:18 +0000 (01:21 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
bugzilla-daemon [Sat, 23 May 2020 01:17:11 +0000 (01:17 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
Jacob Lifshay [Sat, 23 May 2020 01:08:45 +0000 (18:08 -0700)]
Re: [libre-riscv-dev] dns entries for talos server & server maintenance
Luke Kenneth Casson Leighton [Fri, 22 May 2020 23:06:12 +0000 (00:06 +0100)]
Re: [libre-riscv-dev] dns entries for talos server & server maintenance
Luke Kenneth Casson Leighton [Fri, 22 May 2020 23:01:46 +0000 (00:01 +0100)]
Re: [libre-riscv-dev] dns entries for talos server & server maintenance
bugzilla-daemon [Fri, 22 May 2020 22:58:29 +0000 (22:58 +0000)]
[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline
Luke Kenneth Casson Leighton [Fri, 22 May 2020 22:54:49 +0000 (23:54 +0100)]
Re: [libre-riscv-dev] dns entries for talos server & server maintenance
Jacob Lifshay [Fri, 22 May 2020 21:21:08 +0000 (14:21 -0700)]
[libre-riscv-dev] dns entries for talos server & server maintenance
projects / libre-riscv-dev.git / log