mesa.git
6 years agopipe-loader: Free driver_name in error path
Jan Vesely [Tue, 8 May 2018 03:40:47 +0000 (23:40 -0400)]
pipe-loader: Free driver_name in error path

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agoglsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug
Brian Paul [Tue, 8 May 2018 14:24:21 +0000 (08:24 -0600)]
glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug

Change the size of the bitset from 128 bits to 96.  This works around an
apparent GCC 5.4 bug in which bad SSE code is generated, leading to a
crash in ast_type_qualifier::validate_in_qualifier() (ast_type.cpp:654).

This can be repro'd with the Piglit test tests/spec/glsl-1.50/execution/
varying-struct-basic-gs-fs.shader_test

Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=105497
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965: Dump validation list on INTEL_DEBUG=bat,submit.
Kenneth Graunke [Tue, 10 Apr 2018 08:19:55 +0000 (01:19 -0700)]
i965: Dump validation list on INTEL_DEBUG=bat,submit.

This is really useful when debugging any sort of buffer management
issues, so just printing it during INTEL_DEBUG=bat,submit seems
reasonable.  With bat, we're already spamming so much output that
it doesn't really hurt.  With submit, it's still easy to grep for
the older information, and the new information is nice too.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
6 years agoi965/miptree: Remove redundant fields from intel_miptree_aux_buffer
Jason Ekstrand [Fri, 4 May 2018 23:49:47 +0000 (16:49 -0700)]
i965/miptree: Remove redundant fields from intel_miptree_aux_buffer

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz
Jason Ekstrand [Sat, 5 May 2018 05:57:09 +0000 (22:57 -0700)]
i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz

Now that we're using ISL, a good chunk of brw_emit_depthstencil is
pointless checks which ISL will do for us anyway.  Since we only have
one manual depth buffer emit function, move the useful bits into it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Move brw_emit_depth_stencil_hiz higher up in the file
Jason Ekstrand [Sat, 5 May 2018 05:46:49 +0000 (22:46 -0700)]
i965: Move brw_emit_depth_stencil_hiz higher up in the file

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Use ISL for emitting depth/stencil/hiz state on gen6+
Jason Ekstrand [Sat, 5 May 2018 05:32:24 +0000 (22:32 -0700)]
i965: Use ISL for emitting depth/stencil/hiz state on gen6+

We leave gen4-5 alone because the ISL code hasn't really been well-
tested on gen4-5 or with combined depth-stencil because we don't use
BLORP for depth operations on gen4-5.  Also, the gen4-5 code has to deal
with intratile offsets for LOD hacks and ISL doesn't handle those yet.
We could make ISL handle gen4-5 capable or we could just not bother.

Among other things, this should make future platform enabling easier
because it means we don't have to update multiple (or hand-rolled!)
depth stencil emit paths.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Use the brw_depthbuffer atom on all gens
Jason Ekstrand [Sat, 5 May 2018 05:41:19 +0000 (22:41 -0700)]
i965: Use the brw_depthbuffer atom on all gens

The only reason why we had two atoms was that the one we used for gen7+
depended on _NEW_DEPTH and _NEW_STENCIL as well as _NEW_BUFFERS.  Since
this is no longer true, we can combine them into one atom.  We do add a
dependence on BRW_NEW_AUX_STATE but that should never get set on gen4-5
so adding it is a no-op for those platforms.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Always set depth/stencil write enables on gen7+
Jason Ekstrand [Mon, 7 May 2018 17:57:49 +0000 (10:57 -0700)]
i965: Always set depth/stencil write enables on gen7+

The hardware will AND these fields with the corresponding fields in
DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off
based on state bits.  This removes our reliance on the _NEW_DEPTH and
_NEW_STENCIL state bits and better matches what ISL does.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Re-order depth/stencil/hiz/clear packets to match ISL
Jason Ekstrand [Sat, 5 May 2018 19:35:01 +0000 (12:35 -0700)]
i965: Re-order depth/stencil/hiz/clear packets to match ISL

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE
Jason Ekstrand [Sat, 5 May 2018 19:48:54 +0000 (12:48 -0700)]
i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE

Certain things can change the aux usage or fast clear color of a depth
surface and we want to re-emit if that happens.  For instance, if you do
a fast depth clear of an already clear depth surface, we will just set
the clear color and not do anything else.  In that case, we could fail
to re-emit 3DSTATE_CLEAR_PARAMS and not get the new fast-clear color.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: devinfo: fix assertion on devices with odd number of EUs
Lionel Landwerlin [Mon, 23 Apr 2018 16:52:37 +0000 (17:52 +0100)]
intel: devinfo: fix assertion on devices with odd number of EUs

I forgot to change the assert in the second helper function in a
previous change.

This hit the assert() on a Broadwell platform with 1 slice, 3
subslices but all EUs disabled in subslice 1 & 2.

Fixes: c1900f5b0fb ("intel: devinfo: add helper functions to fill fusing masks values")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agovulkan/wsi: Only use LINEAR modifier for prime if supported.
Bas Nieuwenhuizen [Sat, 5 May 2018 13:34:44 +0000 (15:34 +0200)]
vulkan/wsi: Only use LINEAR modifier for prime if supported.

This was setting the LINEAR modifier if neither the
X server nor the driver supported modifiers.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106180
Fixes: c80c08e226 "vulkan/wsi/x11: Add support for DRI3 v1.2"
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Tested-by: Abel Garcia Dorta <mercuriete@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoeg/compute: Drop reference to kernel_param bo in destructor
Jan Vesely [Tue, 8 May 2018 02:54:09 +0000 (22:54 -0400)]
eg/compute: Drop reference to kernel_param bo in destructor

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agor600: Cleanup constant buffers on context destruction
Jan Vesely [Tue, 8 May 2018 02:52:19 +0000 (22:52 -0400)]
r600: Cleanup constant buffers on context destruction

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa/formatquery: remove online compression check on is_resource_supported
Alejandro Piñeiro [Fri, 4 May 2018 14:44:44 +0000 (16:44 +0200)]
mesa/formatquery: remove online compression check on is_resource_supported

is_resource_supported returns if the combination of
target/internalformat is supported in at least one operation. Online
compression is only mandatory for glTexImage2D. Some formats doesn't
support online compression, but can be used in any case, with
glCompressed*D methods.

Without this commit, ETC2 internalformats were returning FALSE, even
for the drivers supporting it. So any other query (like
TEXTURE_COMPRESSED) was returning FALSE/NONE instead of the proper
value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agointel/genxml: Assert that genxml field start and ends are sane.
Kenneth Graunke [Mon, 7 May 2018 18:14:42 +0000 (11:14 -0700)]
intel/genxml: Assert that genxml field start and ends are sane.

Chris recently fixed a bunch of genxml end < start bugs, as well as
booleans that are wider than a bit.  These are way too easy to write, so
asserting that the fields are sane is a good plan.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/genxml: Fix some more fake booleans in genxml.
Kenneth Graunke [Mon, 7 May 2018 18:40:24 +0000 (11:40 -0700)]
intel/genxml: Fix some more fake booleans in genxml.

None of these are actually booleans.  Tile Parameter is a tiling mode
enum.  Display pipes take plane numbers.  Predicate Enable has some
operations (and the default value of 6 was particular bogus).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/genxml: Make assert in gen_pack_header print a message.
Kenneth Graunke [Mon, 7 May 2018 18:23:27 +0000 (11:23 -0700)]
intel/genxml: Make assert in gen_pack_header print a message.

Python's assert can take both a condition and a string, which will cause
it to print the string if the assertion trips.  (You can't use parens as
that creates a tuple.)  Doing "condition and string" works in C, but
doesn't have the desired effect in Python.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965: Don't leak blorp on Gen4-5.
Kenneth Graunke [Mon, 23 Apr 2018 17:40:04 +0000 (10:40 -0700)]
i965: Don't leak blorp on Gen4-5.

We used to only initialize BLORP on Gen6+.  When we added it on Gen4-5,
we forgot to destroy it unconditionally.

Fixes: 752d7af77a52898cebf5597def4fdd38b1d6303e (i965: Add blorp support for gen4-5)
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agonir: Transform discard_if(true) into discard
Matt Turner [Fri, 27 Apr 2018 04:25:42 +0000 (21:25 -0700)]
nir: Transform discard_if(true) into discard

Noticed while reviewing Tim Arceri's NIR inlining series.

Without his series:

instructions in affected programs: 16 -> 14 (-12.50%)
helped: 2

With his series:

instructions in affected programs: 196 -> 174 (-11.22%)
helped: 22

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoeg/compute: Drop reference on code_bo in destructor.
Jan Vesely [Fri, 4 May 2018 03:55:00 +0000 (23:55 -0400)]
eg/compute: Drop reference on code_bo in destructor.

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoconfigure.ac/meson.build: Fix -latomic test
Nicolas Boichat [Thu, 5 Apr 2018 01:33:09 +0000 (09:33 +0800)]
configure.ac/meson.build: Fix -latomic test

When compiling with LLVM 6.0 on x86 (32-bit) for Android, the test
fails to detect that -latomic is actually required, as the atomic
call is inlined.

In the code itself (src/util/disk_cache.c), we see this pattern:
p_atomic_add(cache->size, - (uint64_t)size);
where cache->size is an uint64_t *, and results in the following
link time error without -latomic:
src/util/disk_cache.c:628: error: undefined reference to '__atomic_fetch_add_8'

Fix the configure/meson test to replicate this pattern, which then
correctly realizes the need for -latomic.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
6 years agoanv: remove unused field anv_queue::pool
Scott D Phillips [Wed, 2 May 2018 16:01:03 +0000 (09:01 -0700)]
anv: remove unused field anv_queue::pool

The last use of the field was removed in 2015's ("48a87f4ba06
anv/queue: Get rid of the serial")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965: Set initial kflags on BO creation.
Kenneth Graunke [Thu, 3 May 2018 07:37:37 +0000 (00:37 -0700)]
i965: Set initial kflags on BO creation.

This simplifies kflag initialization, by creating a bufmgr-wide setting
for initial kflags, and just applying it whenever we create a new BO.

This also properly allows 48-bit addresses for imported BOs (via prime
or flink), which I had missed in my earlier 48-bit support series.

This will be useful when adding softpin support, as we'll want to add
EXEC_OBJECT_PINNED to initial_kflags as well.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
6 years agodocs: update calendar, add news and link release notes to 18.0.3
Juan A. Suarez Romero [Mon, 7 May 2018 11:25:54 +0000 (11:25 +0000)]
docs: update calendar, add news and link release notes to 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
6 years agodocs: add sha256 checksums for 18.0.3
Juan A. Suarez Romero [Mon, 7 May 2018 11:18:19 +0000 (11:18 +0000)]
docs: add sha256 checksums for 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit ae12c5e990a06099340c9467ee1a02354420812d)

6 years agodocs: add sha256 checksums for 18.0.3
Juan A. Suarez Romero [Mon, 7 May 2018 10:19:36 +0000 (10:19 +0000)]
docs: add sha256 checksums for 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 6dc2658fd66c18239ad33cb1ffbdfc22b0d9e51e)

6 years agointel/genxml: Fix a few invalid field widths
Chris Wilson [Sat, 5 May 2018 18:36:25 +0000 (19:36 +0100)]
intel/genxml: Fix a few invalid field widths

A couple of typos found by inspecting field.end - field.start, revealed
a few wide integers declared as bool and some that ended before they
started.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agoswr/rast: Fix include for createInstructionCombiningPass with llvm-7.0.
Vinson Lee [Sun, 29 Apr 2018 06:28:08 +0000 (23:28 -0700)]
swr/rast: Fix include for createInstructionCombiningPass with llvm-7.0.

Fix build error after llvm-7.0.0svn r330669 ("InstCombine: Fix layering
by not including Scalar.h in InstCombine").

  CXX      rasterizer/jitter/libmesaswr_la-blend_jit.lo
rasterizer/jitter/blend_jit.cpp:816:20: error: use of undeclared identifier 'createInstructionCombiningPass'; did you mean 'createInstructionSimplifierPass'?
        passes.add(createInstructionCombiningPass());
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   createInstructionSimplifierPass

Suggested-by: George Kyriazis <george.kyriazis@intel.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
6 years agoclover: Add explicit virtual destructor to argument class
Jan Vesely [Fri, 4 May 2018 15:43:38 +0000 (11:43 -0400)]
clover: Add explicit virtual destructor to argument class

It is needed to destroy the v vector in scalar_argument
Fixes memory leaks on parameter set/bind.

v2: Drop redundant sclara_argument destructor

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
6 years agoanv/device: expose shaderInt16 support in gen8+
Iago Toral Quiroga [Fri, 4 May 2018 09:35:55 +0000 (11:35 +0200)]
anv/device: expose shaderInt16 support in gen8+

This rollbacks the revert of this patch introduced with
commit 7cf284f18e6774c810ed6db17b98e597bf96f8a5.

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965/compiler: handle conversion to smaller type in the lowering pass for that
Iago Toral Quiroga [Fri, 4 May 2018 09:33:07 +0000 (11:33 +0200)]
i965/compiler: handle conversion to smaller type in the lowering pass for that

This rollbacks the revert of this same patch introduced in
commit 7b9c15628aae8729118b648f5f473e6ac926b99b.

And also squahes the following patch to prevent a piglit regression caused
by this change:

intel/compiler: Fix lower_conversions for 8-bit types.
Author: Jose Maria Casanova Crespo <jmcasanova@igalia.com>

For 8-bit types the execution type is word. A byte raw MOV has 16-bit
execution type and 8-bit destination and it shouldn't be considered
a conversion case. So there is no need to change alignment and enter
in lower_conversions for these instructions.

Fixes a regresion in the piglit test "glsl-fs-shader-stencil-export"
that is introduced with this patch from the Vulkan shaderInt16 series:
'i965/compiler: handle conversion to smaller type in the lowering
pass for that'. The problem is caused because there is already a case
in the driver that injects Byte instructions like this:

mov(8)          g127<1>UB       g2<32,8,4>UB

And the aforementioned pass was not accounting for the special
handling of the execution size of Byte instructions. This patch
fixes this.

v2: (Jason Ekstrand)
   - Simplify is_byte_raw_mov, include reference to PRM and not
   consider B <-> UB conversions as raw movs.

v3: (Matt Turner)
   - Indentation style fixes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: handle 16-bit to 64-bit conversions in BSW platforms
Iago Toral Quiroga [Fri, 4 May 2018 07:55:55 +0000 (09:55 +0200)]
intel/compiler: handle 16-bit to 64-bit conversions in BSW platforms

These are subject to the general restriction that anything that is converted
to 64-bit needs to be aligned to 64-bit.  We had this already in place for
32-bit to 64-bit conversions, so this patch generalizes the implementation
to take effect on any conversion to 64-bit from a source smaller than
64-bit.

Fixes assembly validation errors in the following CTS tests in BSW:
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_int64
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint16_to_uint64
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_uint64

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/genxml: recognize 0x, 0o and 0b when setting default value
Caio Marcelo de Oliveira Filho [Wed, 2 May 2018 21:48:57 +0000 (14:48 -0700)]
intel/genxml: recognize 0x, 0o and 0b when setting default value

Remove the need of converting values that are documented in
hexadecimal. This patch would allow writing

    <field name="3D Command Sub Opcode" ... default="0x1B"/>

instead of

    <field name="3D Command Sub Opcode" ... default="27"/>

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agor200: Enable NV_fog_distance
Ian Romanick [Sun, 18 Jun 2017 01:56:13 +0000 (18:56 -0700)]
r200: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Enable NV_fog_distance
Ian Romanick [Sat, 17 Jun 2017 02:15:56 +0000 (19:15 -0700)]
i965: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoffvertex: Don't try to read output registers in fog calculation
Ian Romanick [Sat, 17 Jun 2017 02:02:48 +0000 (19:02 -0700)]
ffvertex: Don't try to read output registers in fog calculation

Gallium drivers use _mesa_remove_output_reads() via st_program to lower
output reads away.  It seems better to just generate the right thing in
the first place.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)
Ian Romanick [Sat, 17 Jun 2017 01:48:22 +0000 (18:48 -0700)]
mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

Found by inspection, so I made a piglit test too.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomesa: Silence an unused parameter warning
Ian Romanick [Mon, 22 May 2017 22:21:00 +0000 (15:21 -0700)]
mesa: Silence an unused parameter warning

main/framebuffer.c: In function ‘update_color_draw_buffers’:
main/framebuffer.c:629:46: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb)
                                              ^~~

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomesa/main/readpix: Correct handling of packed floating point values
Gert Wollny [Fri, 27 Apr 2018 16:04:01 +0000 (18:04 +0200)]
mesa/main/readpix: Correct handling of packed floating point values

Make sure that clamping in the pixel transfer operations is enabled/disabled
for packed floating point values just like it is done for single normal and
half precision floating point values.

This fixes a series of CTS tests with virgl that use r11f_g11f_b10f
buffers as target, and where virglrenderer reads these surfaces back
using the format GL_UNSIGNED_INT_10F_11F_11F_REV.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoutil/set: add a set_clear function
Scott D Phillips [Wed, 2 May 2018 16:01:02 +0000 (09:01 -0700)]
util/set: add a set_clear function

Clear a set back to the state of having zero entries.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoegl: add EGL_BAD_MATCH error case for surfaceless and android
Tapani Pälli [Fri, 4 May 2018 05:28:50 +0000 (08:28 +0300)]
egl: add EGL_BAD_MATCH error case for surfaceless and android

Just like is done for other backends when suitable config is not
found (added in fd4eba4929).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
6 years agoamd/common: use llvm.amdgcn.wqm for explicit derivatives
Nicolai Hähnle [Tue, 1 May 2018 09:06:18 +0000 (11:06 +0200)]
amd/common: use llvm.amdgcn.wqm for explicit derivatives

To comply with an upcoming change in LLVM, see
https://reviews.llvm.org/D46051

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agonv50/ir: fix printing of pixld
Rhys Perry [Thu, 3 May 2018 17:02:14 +0000 (18:02 +0100)]
nv50/ir: fix printing of pixld

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agost/va: Support YUV formats in vaCreateSurfaces
Drew Davenport [Fri, 27 Apr 2018 15:34:58 +0000 (09:34 -0600)]
st/va: Support YUV formats in vaCreateSurfaces

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
6 years agoRevert "anv/device: expose shaderInt16 support in gen8+"
Mark Janes [Thu, 3 May 2018 21:28:22 +0000 (14:28 -0700)]
Revert "anv/device: expose shaderInt16 support in gen8+"

This reverts commit 0ba0ac815e078185c1f408ec7078fd1efac1a634.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
6 years agoRevert "i965/compiler: handle conversion to smaller type in the lowering pass for...
Mark Janes [Thu, 3 May 2018 21:28:00 +0000 (14:28 -0700)]
Revert "i965/compiler: handle conversion to smaller type in the lowering pass for that"

This reverts commit 96b51537908cd2aace85f54b437eeb72e6346b7e.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
6 years agoswr/rast: Fix WriteBitcodeToFile usage with llvm-7.0.
Vinson Lee [Tue, 1 May 2018 06:57:23 +0000 (23:57 -0700)]
swr/rast: Fix WriteBitcodeToFile usage with llvm-7.0.

Fix build error after llvm-7.0svn r325155 ("Pass a reference to a module
to the bitcode writer.").

  CXX      rasterizer/jitter/libmesaswr_la-JitManager.lo
rasterizer/jitter/JitManager.cpp:548:30: error: reference to type 'const llvm::Module' could not bind to an lvalue of type 'const llvm::Module *'
    llvm::WriteBitcodeToFile(M, bitcodeStream);
                             ^

Suggested-by: George Kyriazis <george.kyriazis@intel.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
6 years agoegl/x11: Send invalidate to driver on copy_region path in swap_buffer
Deepak Rawat [Tue, 24 Apr 2018 18:50:59 +0000 (11:50 -0700)]
egl/x11: Send invalidate to driver on copy_region path in swap_buffer

Similar to swap_available path send invalidate to the driver because
egl/X11 is not watching for for server's invalidate events. The
dri2_copy_region path is trigerred when server supports DRI2 version
minor 1.

Tested with piglit egl tests for regression.

V2: Move invalidate from dri2_copy_region to swap_buffer common.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Deepak Rawat <drawat@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
6 years agoegl: check if colorspace/surface type is supported
Juan A. Suarez Romero [Wed, 2 May 2018 16:20:16 +0000 (16:20 +0000)]
egl: check if colorspace/surface type is supported

According to EGL 1.4 spec, section 3.5.1 ("Creating On-Screen Rendering
Surfaces"), if config does not support the colorspace or alpha format
attributes specified in attrib_list (as defined for
eglCreateWindowSurface), an EGL_BAD_MATCH error is generated.

This fixes dEQP-EGL.functional.wide_color.*_888_colorspace_srgb (still
not merged,
https://android-review.googlesource.com/c/platform/external/deqp/+/667322),
which is crashing when trying to create a windows surface with RGB888
configuration and sRGB colorspace.

v2: Handle the fix in other backends (Tapani)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
6 years agoanv/device: expose shaderInt16 support in gen8+
Iago Toral Quiroga [Fri, 2 Mar 2018 09:58:58 +0000 (10:58 +0100)]
anv/device: expose shaderInt16 support in gen8+

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoanv/pipeline: support SpvCapabilityInt16 in gen8+
Iago Toral Quiroga [Fri, 2 Mar 2018 10:12:38 +0000 (11:12 +0100)]
anv/pipeline: support SpvCapabilityInt16 in gen8+

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agocompiler/spirv: add implementation to check for SpvCapabilityInt16 support
Iago Toral Quiroga [Fri, 2 Mar 2018 10:08:52 +0000 (11:08 +0100)]
compiler/spirv: add implementation to check for SpvCapabilityInt16 support

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: implement 16-bit pack/unpack opcodes
Iago Toral Quiroga [Tue, 17 Apr 2018 08:23:47 +0000 (10:23 +0200)]
intel/compiler: implement 16-bit pack/unpack opcodes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agocompiler/spirv: implement 16-bit bitcasts
Iago Toral Quiroga [Tue, 17 Apr 2018 08:22:43 +0000 (10:22 +0200)]
compiler/spirv: implement 16-bit bitcasts

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agocompiler/lower_64bit_packing: rename the pass to be more generic
Iago Toral Quiroga [Fri, 27 Apr 2018 07:28:48 +0000 (09:28 +0200)]
compiler/lower_64bit_packing: rename the pass to be more generic

It can do 32-bit packing too now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agonir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.
Iago Toral Quiroga [Tue, 17 Apr 2018 08:09:03 +0000 (10:09 +0200)]
nir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.

With 16-bit support we can now do 32-bit packing, a follow-up patch will
rename the pass to something more generic.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agonir: add opcodes for 16-bit packing and unpacking
Iago Toral Quiroga [Tue, 17 Apr 2018 08:07:40 +0000 (10:07 +0200)]
nir: add opcodes for 16-bit packing and unpacking

Noitice that we don't need 'split' versions of the 64-bit to / from
16-bit opcodes which we require during pack lowering to implement these
operations. This is because these operations can be expressed as a
collection of 32-bit from / to 16-bit and 64-bit to / from 32-bit
operations, so we don't need new opcodes specifically for them.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: fix 16-bit comparisons
Iago Toral Quiroga [Thu, 19 Apr 2018 08:06:43 +0000 (10:06 +0200)]
intel/compiler: fix 16-bit comparisons

NIR assumes that booleans are always 32-bit, but Intel hardware produces
16-bit booleans for 16-bit comparisons. This means that we need to convert
the 16-bit result to 32-bit.

In the future we want to add an optimization pass to clean this up and
hopefully remove the conversions.

v2 (Jason): use the type of the source for the temporary and use
            brw_reg_type_from_bit_size for the conversion to 32-bit.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: lower some 16-bit integer operations to 32-bit
Iago Toral Quiroga [Thu, 26 Apr 2018 08:07:56 +0000 (10:07 +0200)]
intel/compiler: lower some 16-bit integer operations to 32-bit

These are not supported in hardware for 16-bit integers.

We do the lowering pass after the optimization loop to ensure that we
lower ALU operations injected by algebraic optimizations too.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agocompiler/nir: add a lowering pass to convert the bit size of ALU operations
Iago Toral Quiroga [Thu, 26 Apr 2018 08:02:04 +0000 (10:02 +0200)]
compiler/nir: add a lowering pass to convert the bit size of ALU operations

Not all bit-sizes may be supported natively in hardware for all operations.
This pass allows drivers to lower such operations to a bit-size that is
actually supported and then converts the result back to the original
bit-size.

Compiler backends control which operations and wich bit-sizes require
the lowering through a callback function.

v2: generalize this pass and make it available in NIR core (Rob, Jason)
v3: remove some temporaries and reduce nesting in instruction loop using
    a continue statement (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: support negate and abs of half float immediates
Jose Maria Casanova Crespo [Thu, 3 May 2018 00:18:37 +0000 (02:18 +0200)]
intel/compiler: support negate and abs of half float immediates

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: fix brw_imm_w for negative 16-bit integers
Jose Maria Casanova Crespo [Wed, 2 May 2018 23:38:47 +0000 (01:38 +0200)]
intel/compiler: fix brw_imm_w for negative 16-bit integers

16-bit immediates need to replicate the 16-bit immediate value
in both words of the 32-bit value. This needs to be careful
to avoid sign-extension, which the previous implementation was
not handling properly.

For example, with the previous implementation, storing the value
-3 would generate imm.d = 0xfffffffd due to signed integer sign
extension, which is not correct. Instead, we should cast to
uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd.

We only had a couple of cases hitting this path in the driver
until now, one with value -1, which would work since all bits are
one in this case, and another with value -2 in brw_clip_tri(),
which would hit the aforementioned issue (this case only affects
gen4 although we are not aware of whether this was causing an
actual bug somewhere).

v2: Make explicit uint32_t casting for left shift (Jason Ekstrand)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org>
6 years agointel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate
Jose Maria Casanova Crespo [Wed, 2 May 2018 23:44:11 +0000 (01:44 +0200)]
intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate

From Intel Skylake PRM, vol 07, "Immediate" section (page 768):

"For a word, unsigned word, or half-float immediate data,
software must replicate the same 16-bit immediate value to both
the lower word and the high word of the 32-bit immediate field
in a GEN instruction."

This fixes the int16/uint16 negate and abs immediates that weren't
taking into account the replication in lower and upper words.

v2: Integer cases are different to Float cases. (Jason Ekstrand)
    Included reference to PRM (Jose Maria Casanova)
v3: Make explicit uint32_t casting for left shift (Jason Ekstrand)
    Split half float implementation. (Jason Ekstrand)
    Fix brw_abs_immediate (Jose Maria Casanova)

Cc: "18.0 18.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: implement nir_instr_type_load_const for 16-bit constants
Jose Maria Casanova Crespo [Tue, 10 Apr 2018 08:02:29 +0000 (10:02 +0200)]
intel/compiler: implement nir_instr_type_load_const for 16-bit constants

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: implement conversions from 16-bit int/float to bool
Iago Toral Quiroga [Wed, 7 Mar 2018 10:12:18 +0000 (11:12 +0100)]
intel/compiler: implement conversions from 16-bit int/float to bool

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: implement conversion between float/int 16-bit types
Iago Toral Quiroga [Tue, 6 Mar 2018 12:35:49 +0000 (13:35 +0100)]
intel/compiler: implement conversion between float/int 16-bit types

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965/compiler: handle conversion to smaller type in the lowering pass for that
Iago Toral Quiroga [Tue, 6 Mar 2018 11:14:05 +0000 (12:14 +0100)]
i965/compiler: handle conversion to smaller type in the lowering pass for that

The lowering pass was specialized to act on 64-bit to 32-bit conversions only,
but the implementation is valid for other cases.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: fix isign for 16-bit integers
Iago Toral Quiroga [Tue, 6 Mar 2018 07:57:26 +0000 (08:57 +0100)]
intel/compiler: fix isign for 16-bit integers

We need to use 16-bit constants with 16-bit instructions,
otherwise we get the following validation error:

"Destination stride must be equal to the ratio of the sizes of
 the execution data type to the destination type"

Because the execution data type is 4B due to the 32-bit integer
constant.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965: Always try to create a logical context
Chris Wilson [Fri, 15 Dec 2017 13:42:25 +0000 (13:42 +0000)]
i965: Always try to create a logical context

Always enable use of HW logical contexts to preserve GPU state between
batches when the kernel supports such constructs, continuing to enforce
the required support for gen6+.

At runtime, this effectively removes the BRW_NEW_CONTEXT flag (and the
upload of invariant state) from the start of every batch for any kernel
supporting contexts. So long as the older atoms are correctly listening
to the right flag (NEW_CONTEXT rather than NEW_BATCH) this should
eliminate a few redundant state uploads for the older platforms.

No piglits were harmed on ctg and ilk, both with and without logical
contexts.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agospirv: Apply OriginUpperLeft to FragCoord
Neil Roberts [Wed, 2 May 2018 16:10:00 +0000 (18:10 +0200)]
spirv: Apply OriginUpperLeft to FragCoord

This behaviour was changed in 1e5b09f42f694687ac. The commit message
for that says it is just a “tidy up” so my assumption is that the
behaviour change was a mistake. It’s a little hard to decipher looking
at the diff, but the previous code before that patch was:

  if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition)
     nir_var->data.origin_upper_left = b->origin_upper_left;

  if (builtin == SpvBuiltInFragCoord)
     nir_var->data.pixel_center_integer = b->pixel_center_integer;

After the patch the code was:

  case SpvBuiltInSamplePosition:
     nir_var->data.origin_upper_left = b->origin_upper_left;
     /* fallthrough */
  case SpvBuiltInFragCoord:
     nir_var->data.pixel_center_integer = b->pixel_center_integer;
     break;

Before the patch origin_upper_left affected both builtins and
pixel_center_integer only affected FragCoord. After the patch
origin_upper_left only affects SamplePosition and pixel_center_integer
affects both variables.

This patch tries to restore the previous behaviour by changing the
code to:

  case SpvBuiltInFragCoord:
     nir_var->data.pixel_center_integer = b->pixel_center_integer;
     /* fallthrough */
  case SpvBuiltInSamplePosition:
     nir_var->data.origin_upper_left = b->origin_upper_left;
     break;

This change will be important for ARB_gl_spirv which is meant to
support OriginLowerLeft.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Fixes: 1e5b09f42f694687ac "spirv: Tidy some repeated if checks..."
6 years agospirv: convert some operands for bitwise shift and bitwise ops to uint32
Samuel Iglesias Gonsálvez [Wed, 25 Apr 2018 09:55:49 +0000 (11:55 +0200)]
spirv: convert some operands for bitwise shift and bitwise ops to uint32

SPIR-V allows to define the shift, offset and count operands for
shift and bitfield opcodes with a bit-size different than 32 bits,
but in NIR the opcodes have that limitation. As agreed in the
mailing list, this patch adds a conversion to 32 bits to fix this.

For more info, see:

https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html

v2:
- src_bit_size will have zero value for variable bit-size operands (Jason).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agomesa: enable geom shaders in OpenGL 3.2 Compat profile
Timothy Arceri [Wed, 2 May 2018 09:55:59 +0000 (19:55 +1000)]
mesa: enable geom shaders in OpenGL 3.2 Compat profile

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agoradv: UseEnumerateInstanceVersion for the default version.
Bas Nieuwenhuizen [Tue, 1 May 2018 20:46:41 +0000 (22:46 +0200)]
radv: UseEnumerateInstanceVersion for the default version.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: Don't check the incoming apiVersion on CreateInstance.
Bas Nieuwenhuizen [Tue, 1 May 2018 20:44:42 +0000 (22:44 +0200)]
radv: Don't check the incoming apiVersion on CreateInstance.

This fixes

dEQP-VK.api.device_init.create_instance_invalid_api_version

CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: Allow vkEnumerateInstanceVersion ProcAddr without instance.
Bas Nieuwenhuizen [Tue, 1 May 2018 16:02:45 +0000 (18:02 +0200)]
radv: Allow vkEnumerateInstanceVersion ProcAddr without instance.

Apparently the somewhere between 1.1.70 and 1.1.73 the loader started
depending on this. The loader then creates a 1.0 instance, which gets
into funny situation because we have a 1.1 device.

No idea how to do line wrapping in Mako though, my random guesses
did not work.

CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel: aubinator: add an option to limit the number of decoded VBO lines
Lionel Landwerlin [Wed, 2 May 2018 17:40:28 +0000 (18:40 +0100)]
intel: aubinator: add an option to limit the number of decoded VBO lines

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: decoder: limit to the number decoded lines from VBO
Lionel Landwerlin [Wed, 2 May 2018 17:39:20 +0000 (18:39 +0100)]
intel: decoder: limit to the number decoded lines from VBO

By default we set no limit, but the debug batch decoder in i965 sets
it to 100.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoanv: Advertise variableMultisampleRate
Jason Ekstrand [Thu, 8 Feb 2018 17:03:03 +0000 (09:03 -0800)]
anv: Advertise variableMultisampleRate

Initially, I didn't understand this feature.  Turns out that all it
means is that you can switch multisample rates in the middle of a
zero-attachment subpass.  We've been able to do this since forever.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
6 years agonir: add missing dependency in meson.build
Rob Clark [Wed, 2 May 2018 16:43:50 +0000 (12:43 -0400)]
nir: add missing dependency in meson.build

nir_builder_opcodes.h also depends on nir_intrinsics.py for generating
the system-value builders.

Reported-by: Christoph Haag <haagch@frickel.club>
Reported-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoradv: fix multisample image copies
Matthew Nicholls [Wed, 2 May 2018 12:03:52 +0000 (14:03 +0200)]
radv: fix multisample image copies

Previously before fb077b0728, the LOD parameter was being used in place of the
sample index, which would only copy the first sample to all samples in the
destination image. After that multisample image copies wouldn't copy anything
from my observations.

This fixes some copy_and_blit CTS tests.

v3.1: - set lod to 0 for nir_txf_ms (Samuel)
v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel)
    - updated commit description (Samuel)

Fix this properly by copying each sample in a separate radv_CmdDraw and using a
pipeline with the correct rasterizationSamples for the destination image.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agointel: Fix 3DSTATE_CONSTANT buffer decoding.
Kenneth Graunke [Wed, 2 May 2018 16:43:27 +0000 (09:43 -0700)]
intel: Fix 3DSTATE_CONSTANT buffer decoding.

First, this was iterating over the 3DSTATE_CONSTANT_* instruction
but trying to process fields of the 3DSTATE_CONSTANT_BODY substructure.

Secondly, the fields have been called Buffer[0] and Read Length[0],
for a while now, and we were not handling the subscripts correctly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agointel: fix aubinator include
Lionel Landwerlin [Wed, 2 May 2018 16:51:03 +0000 (17:51 +0100)]
intel: fix aubinator include

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7c22c150c40b3 ("intel: Move batch decoder/disassembler from tools/ to common/")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Reuse batch decoder infrastructure rather than open coding it.
Kenneth Graunke [Wed, 2 May 2018 00:16:06 +0000 (17:16 -0700)]
i965: Reuse batch decoder infrastructure rather than open coding it.

With the new callback, Jason's newer batch decoder infrastructure
should be able to do just as well as the old open coded INTEL_DEBUG=bat
handling, with much less code.  If there are any limitations, we'd like
to improve the common code rather than doing one-off hacks here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agointel: Give the batch decoder a callback to ask about state size.
Kenneth Graunke [Wed, 2 May 2018 04:49:17 +0000 (21:49 -0700)]
intel: Give the batch decoder a callback to ask about state size.

Given an arbitrary batch, we don't always know what the size of certain
things are, such as how many entries are in a binding table.  But it's
easy for the driver to track that information, so with a simple callback
we can calculate this correctly for INTEL_DEBUG=bat.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agointel: Move batch decoder/disassembler from tools/ to common/
Kenneth Graunke [Wed, 2 May 2018 00:27:08 +0000 (17:27 -0700)]
intel: Move batch decoder/disassembler from tools/ to common/

Making these part of libintel_common allows us to use them in the DRI
driver.  The standalone tool binaries already link against the common
library, too, so it's no harder for them.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agoi965: Allocate shadow batches to explicitly be the BO size.
Kenneth Graunke [Fri, 13 Apr 2018 22:35:56 +0000 (15:35 -0700)]
i965: Allocate shadow batches to explicitly be the BO size.

This unfortunately makes it malloc/realloc on every new batch, rather
than once at startup.  But it ensures that the shadow buffer's size will
absolutely match the BO size.  Otherwise, as we tune BATCH_SZ/STATE_SZ
or bufmgr cache bucket sizes, we may get a BO size that's rounded up,
and fail to allocate the shadow buffer large enough.

This doesn't fix any bugs today, as BATCH_SZ/STATE_SZ are the size of
a cache bucket, but it's better to be safe than sorry.

Reported-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agointel: batch-decoder: iterate VERTEX_BUFFER_STATE fields
Lionel Landwerlin [Tue, 1 May 2018 23:17:19 +0000 (00:17 +0100)]
intel: batch-decoder: iterate VERTEX_BUFFER_STATE fields

The gen_field_iterator only iterates the fields of a given gen_group.
If we want to iterate the fields of another gen_group contained as
field, we need to do it manually.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: decoder: fix starting dword of struct fields
Lionel Landwerlin [Tue, 1 May 2018 23:13:39 +0000 (00:13 +0100)]
intel: decoder: fix starting dword of struct fields

Struct fields might span several dwords, but iter_dword is incremented
up to the last dword of the current field before we print out the
struct's fields. We can't use iter_dword for computing the offset into
the pointer of data to decode.

v2: Fix displayed offset number (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: decoder: document when fields should be used
Lionel Landwerlin [Tue, 1 May 2018 21:18:11 +0000 (22:18 +0100)]
intel: decoder: document when fields should be used

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: decoder: identify groups with fixed length
Lionel Landwerlin [Tue, 1 May 2018 21:14:12 +0000 (22:14 +0100)]
intel: decoder: identify groups with fixed length

<register> & <struct> elements always have fixed length. The
get_length() method implies that we're dealing with an instruction in
which the length is encoded into the variable data but the field
iterator uses it without checking what kind of gen_group it is dealing
with.

Let's make get_length() report the correct length regardless of the
gen_group (register, struct or instruction).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: decoder: make the field iterator use more natural
Lionel Landwerlin [Tue, 1 May 2018 21:12:56 +0000 (22:12 +0100)]
intel: decoder: make the field iterator use more natural

while (iter_next()) { ... }

instead of

do { ... } while (iter_next());

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agonv50: Extract needed value bits without shifting them before calling bitcount
Vlad Golovkin [Mon, 16 Apr 2018 20:50:24 +0000 (23:50 +0300)]
nv50: Extract needed value bits without shifting them before calling bitcount

This can save one instruction since bitcount doesn't care about specific
bits' positions.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
6 years agointel: activate the gl_BaseVertex lowering
Antia Puentes [Sat, 28 Apr 2018 12:09:22 +0000 (14:09 +0200)]
intel: activate the gl_BaseVertex lowering

Surplus code related to the basevertex is removed.

The Vertex Elements contain now:
* VE 1: <firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is_indexed_draw, 0, 0>

Also fixes unreachable message.

Fixes OpenGL CTS tests:
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters

Fixes Piglit tests:
* arb_shader_draw_parameters-drawid-indirect baseinstance
* arb_shader_draw_parameters-basevertex

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678

6 years agocompiler/nir: Add conditional lowering for gl_BaseVertex
Antia Puentes [Sat, 28 Apr 2018 12:09:21 +0000 (14:09 +0200)]
compiler/nir: Add conditional lowering for gl_BaseVertex

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel: emit is_indexed_draw in the same VE than gl_DrawID
Antia Puentes [Sat, 28 Apr 2018 12:09:20 +0000 (14:09 +0200)]
intel: emit is_indexed_draw in the same VE than gl_DrawID

The Vertex Elements are now:
* VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is-indexed-draw, 0, 0>

VE1 is it kept as it was before, VE2 additionally contains the new
system value.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: Add uses_is_indexed_draw flag
Antia Puentes [Sat, 28 Apr 2018 12:09:19 +0000 (14:09 +0200)]
intel/compiler: Add uses_is_indexed_draw flag

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agocompiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsics
Antia Puentes [Sat, 28 Apr 2018 12:09:18 +0000 (14:09 +0200)]
compiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsics

This VS system value contains if the draw command used to start the
rendering was an indexed draw command or a non-indexed one
(~0/0 respectively). Useful to calculate the gl_BaseVertex as:
(SYSTEM_VALUE_IS_INDEXED_DRAW & SYSTEM_VALUE_FIRST_VERTEX).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoradv: enable out-of-order rasterization by default
Samuel Pitoiset [Tue, 24 Apr 2018 15:06:19 +0000 (17:06 +0200)]
radv: enable out-of-order rasterization by default

As the implementation is conservative, we can now enable it
by default. It can be disabled with RADV_DEBUG=nooutoforder.

Don't expect much more than 1% of improvements, but the gain
seems consistent.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>