Andreas Sandberg [Fri, 15 Feb 2013 22:40:10 +0000 (17:40 -0500)]
dev: Use the correct return type for disk offsets
Replace the use of off_t in the various DiskImage related classes with
std::streampos. off_t is a signed 32 bit integer on most 32-bit
systems, whereas std::streampos is normally a 64 bit integer on most
modern systems. Furthermore, std::streampos is the type used by
tellg() and seekg() in the standard library, so it should have been
used in the first place. This patch makes it possible to use disk
images larger than 2 GiB on 32 bit systems with a modern C++ standard
library.
Geoffrey Blake [Fri, 15 Feb 2013 22:40:10 +0000 (17:40 -0500)]
cpu: Avoid duplicate entries in tracking structures for writes to misc regs
setMiscReg currently makes a new entry for each write to a misc reg without
checking for duplicates, this can cause a triggering of the assert if an
instruction get replayed and writes to the same misc regs multiple times.
This fix prevents duplicate entries and instead updates the value.
Geoffrey Blake [Fri, 15 Feb 2013 22:40:10 +0000 (17:40 -0500)]
cpu: Fix rename mis-handling serializing instructions when resource constrained
The rename can mis-handle serializing instructions (i.e. strex) if it gets
into a resource constrained situation and the serializing instruction has
to be placed on the skid buffer to handle blocking. In this situation the
instruction informs the pipeline it is serializing and logs that the next
instruction must be serialized, but since we are blocking the pipeline
defers this action to place the serializing instruction and
incoming instructions into the skid buffer. When resuming from blocking,
rename will pull the serializing instruction from the skid buffer and
the current logic will see this as the "next" instruction that has to
be serialized and because of flags set on the serializing instruction,
it passes through the pipeline stage as normal and resets rename to
non-serializing. This causes instructions to follow the serializing inst
incorrectly and eventually leads to an error in the pipeline. To fix this
rename should check first if it has to block before checking for serializing
instructions.
Chris Emmons [Fri, 15 Feb 2013 22:40:10 +0000 (17:40 -0500)]
ARM: Postpones creation of framebuffer output file until it is actually used.
This delay prevents a potential conflict with the HDLCD if both are in the same
system even if only one is enabled.
Andreas Hansson [Fri, 15 Feb 2013 22:40:10 +0000 (17:40 -0500)]
mem: Tighten up cache constness and scoping
This patch merely adopts a more strict use of const for the cache
member functions and variables, and also moves a large portion of the
member functions from public to protected.
Sascha Bischoff [Fri, 15 Feb 2013 22:40:10 +0000 (17:40 -0500)]
base: Add warn() and inform() to m5.utils for use from python
This patch adds two fuctions to m5.util, warn and inform, which mirror those
found in the C++ side of gem5. These are added in addition to the already
existing m5.util.panic and m5.util.fatal which already mirror the C++
functionality. This ensures that warning and information messages generated
by python are in the same format as those generated by C++.
Occurrences of
print "Warning: %s..." % name
have been replaced with
warn("%s...", name)
Matt Horsnell [Fri, 15 Feb 2013 22:40:09 +0000 (17:40 -0500)]
o3: fix tick used for renaming and issue with range selection
Fixes the tick used from rename:
- previously this gathered the tick on leaving rename which was always 1 less
than the dispatch. This conflated the decode ticks when back pressure built
in the pipeline.
- now picks up tick on entry.
Added --store_completions flag:
- will additionally display the store completion tail in the viewer.
- this highlights periods when large numbers of stores are outstanding (>16 LSQ
blocking)
Allows selection by tick range (previously this caused an infinite loop)
Andreas Sandberg [Thu, 25 Oct 2012 13:08:29 +0000 (14:08 +0100)]
arm: Don't export private GIC methods
Andreas Sandberg [Thu, 25 Oct 2012 13:05:24 +0000 (14:05 +0100)]
arm: Create a GIC base class and make the PL390 derive from it
This patch moves the GIC interface to a separate base class and makes
all interrupt devices use that base class instead of a pointer to the
PL390 implementation. This allows us to have multiple GIC
implementations. Future implementations will allow in-kernel GIC
implementations when using hardware virtualization.
--HG--
rename : src/dev/arm/gic.cc => src/dev/arm/gic_pl390.cc
rename : src/dev/arm/gic.hh => src/dev/arm/gic_pl390.hh
Andreas Sandberg [Fri, 15 Feb 2013 22:40:09 +0000 (17:40 -0500)]
sim: Add a system-global option to bypass caches
Virtualized CPUs and the fastmem mode of the atomic CPU require direct
access to physical memory. We currently require caches to be disabled
when using them to prevent chaos. This is not ideal when switching
between hardware virutalized CPUs and other CPU models as it would
require a configuration change on each switch. This changeset
introduces a new version of the atomic memory mode,
'atomic_noncaching', where memory accesses are inserted into the
memory system as atomic accesses, but bypass caches.
To make memory mode tests cleaner, the following methods are added to
the System class:
* isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'.
* isTimingMode() -- True if the memory mode is 'timing'.
* bypassCaches() -- True if caches should be bypassed.
The old getMemoryMode() and setMemoryMode() methods should never be
used from the C++ world anymore.
Andreas Sandberg [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
cpu: Refactor memory system checks
CPUs need to test that the memory system is in the right mode in two
places, when the CPU is initialized (unless it's switched out) and on
a drainResume(). This led to some code duplication in the CPU
models. This changeset introduces the verifyMemoryMode() method which
is called by BaseCPU::init() if the CPU isn't switched out. The
individual CPU models are responsible for calling this method when
resuming from a drain as this code is CPU model specific.
Andreas Sandberg [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
config: Remove O3 dependencies
The default cache configuration script currently import the O3_ARM_v7a
model configuration, which depends on the O3 CPU. This breaks if gem5
has been compiled without O3 support. This changeset removes the
dependency by only importing the model if it is requested by the
user. As a bonus, it actually removes some code duplication in the
configuration scripts.
Andreas Sandberg [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
config: Move CPU handover logic to m5.switchCpus()
CPU switching consists of the following steps:
1. Drain the system
2. Switch out old CPUs (cpu.switchOut())
3. Change the system timing mode to the mode the new CPUs require
4. Flush caches if switching to hardware virtualization
5. Inform new CPUs of the handover (cpu.takeOverFrom())
6. Resume the system
m5.switchCpus() previously only did step 2 & 5. Since information
about the new processors' memory system requirements is now exposed,
do all of the steps above.
This patch adds automatic memory system switching and flush (if
needed) to switchCpus(). Additionally, it adds optional draining to
switchCpus(). This has the following implications:
* changeToTiming and changeToAtomic are no longer needed, so they have
been removed.
* changeMemoryMode is only used internally, so it is has been renamed
to be private.
* switchCpus requires a reference to the system containing the CPUs as
its first parameter.
WARNING: This changeset breaks compatibility with existing
configuration scripts since it changes the signature of
m5.switchCpus().
Andreas Sandberg [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
config: Cleanup CPU configuration
The CPUs supported by the configuration scripts used to be
hard-coded. This was not ideal for several reasons. For example, the
configuration scripts depend on all CPU models even though only a
subset might have been compiled.
This changeset adds a new module to the configuration scripts that
automatically discovers the available CPU models from the compiled
SimObjects. As a nice bonus, the use of introspection allows us to
automatically generate a list of available CPU models suitable for
printing. This list is augmented with the Python doc string from the
underlying class if available.
Andreas Sandberg [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
Checker CPUs currently don't inherit from the CheckerCPU in the Python
object hierarchy. This has two consequences:
* It makes CPU model discovery from the Python world somewhat
complicated as there is no way of testing if a CPU is a checker.
* Parameters are duplicated in the checker configuration
specification.
This changeset makes all checker CPUs inherit from the base checker
CPU class.
Andreas Sandberg [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
cpu: Add CPU metadata om the Python classes
The configuration scripts currently hard-code the requirements of each
CPU. This is clearly not optimal as it makes writing new configuration
scripts painful and adding new CPU models requires existing scripts to
be updated. This patch adds the following class methods to the base
CPU and all relevant CPUs:
* memory_mode -- Return a string describing the current memory mode
(invalid/atomic/timing).
* require_caches -- Does the CPU model require caches?
* support_take_over -- Does the CPU support CPU handover?
Ali Saidi [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
arm: fix some fp comparisons that worked by accident.
The explict tests in the follwing fp comparison operations were
incorrect as they checked for only signaling NaNs and not quite-NaNs
as well. When compiled with gcc, the comparison generates a fp exception
that causes the FE_INVALID flag to be set and we check for it, so even
though the check was incorrect, the correct exception was set. With clang
this behavior seems to not occur. The checks are updated to test for nans and
the behavior is now correct with both clang and gcc.
Ali Saidi [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
cpu: include set in o3/commit_impl.
While the majority of compilers seemed to pickup set from else where,
one version of gcc 4.7 complains, so explictly add it.
Ali Saidi [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
ARM: Fix an issue with clang generating wrong code.
Clang generated executables would enter the if condition when it wasn't
supposted to, resulting in the wrong simulated behavior.
Implementing the operation this way is a bit faster anyway.
Ali Saidi [Fri, 15 Feb 2013 22:40:08 +0000 (17:40 -0500)]
cpu: fix case with o3 cpu blocking and unblocking decode in cycle
Fix a case in the O3 CPU where the decode stage blocks and unblocks in a
single cycle sending both signals to fetch which causes an assert or worse.
The previous check could never work before since the status was set to Blocked
before a test for the status being Unblocking was executed.
Ali Saidi [Fri, 15 Feb 2013 22:40:07 +0000 (17:40 -0500)]
cpu: Fix a livelock in the o3 cpu.
Check if an instruction just enabled interrupts and we've previously had an
interrupt pending that was not handled because interrupts were subsequently
disabled before the pipeline reached a place to handle the interrupt. In that
case squash now to make sure the interrupt is handled.
Andreas Sandberg [Sun, 10 Feb 2013 12:23:58 +0000 (13:23 +0100)]
base: Add support for newer versions of IPython
IPython is used for the interactive gem5 shell if it exists. IPython
made API changes in version 0.11. This patch adds support for IPython
version 0.11 and above.
--HG--
extra : rebase_source :
5388d0919adb58d97f49a1a637db48cba61283a3
Andreas Hansson [Thu, 14 Feb 2013 17:24:51 +0000 (12:24 -0500)]
Ruby: Fix compilation errors on gcc 4.7 and clang 3.2
This patch fixes a few (recently added) errors that prevented gem5 from
compiling on more recent versions of gcc and clang.
Nilay Vaish [Mon, 11 Feb 2013 03:43:23 +0000 (21:43 -0600)]
regressions: update stats due to changes to ruby
Nilay Vaish [Mon, 11 Feb 2013 03:43:18 +0000 (21:43 -0600)]
ruby: MI protocol: add a missing transition
The transition for state MII and event Store was found missing during testing.
The transition is being added. The controller will not stall the Store request
in state MII
Nilay Vaish [Mon, 11 Feb 2013 03:43:17 +0000 (21:43 -0600)]
ruby: enable multiple clock domains
This patch allows ruby to have multiple clock domains. As I understand
with this patch, controllers can have different frequencies. The entire
network needs to run at a single frequency.
The idea is that with in an object, time is treated in terms of cycles.
But the messages that are passed from one entity to another should contain
the time in Ticks. As of now, this is only true for the message buffers,
but not for the links in the network. As I understand the code, all the
entities in different networks (simple, garnet-fixed, garnet-flexible) should
be clocked at the same frequency.
Another problem is that the directory controller has to operate at the same
frequency as the ruby system. This is because the memory controller does
not make use of the Message Buffer, and instead implements a buffer of its
own. So, it has no idea of the frequency at which the directory controller
is operating and uses ruby system's frequency for scheduling events.
Nilay Vaish [Mon, 11 Feb 2013 03:43:10 +0000 (21:43 -0600)]
ruby: replace Time with Cycles (final patch in the series)
This patch is as of now the final patch in the series of patches that replace
Time with Cycles.This patch further replaces Time with Cycles in Sequencer,
Profiler, different protocols and related entities.
Though Time has not been completely removed, the places where it is in use
seem benign as of now.
Nilay Vaish [Mon, 11 Feb 2013 03:43:09 +0000 (21:43 -0600)]
ruby: replace Time with Cycles in garnet fixed and flexible
Nilay Vaish [Mon, 11 Feb 2013 03:43:08 +0000 (21:43 -0600)]
ruby: replace Time with Tick in replacement policy classes
Nilay Vaish [Mon, 11 Feb 2013 03:43:07 +0000 (21:43 -0600)]
ruby: convert block size, memory size to unsigned
Nilay Vaish [Mon, 11 Feb 2013 03:26:26 +0000 (21:26 -0600)]
ruby: replace Time with Cycles in MessageBuffer
Nilay Vaish [Mon, 11 Feb 2013 03:26:25 +0000 (21:26 -0600)]
ruby: replace Time with Cycles in Memory Controller
Nilay Vaish [Mon, 11 Feb 2013 03:26:25 +0000 (21:26 -0600)]
ruby: Replace Time with Cycles in SequencerMessage
Nilay Vaish [Mon, 11 Feb 2013 03:26:24 +0000 (21:26 -0600)]
ruby: replace Time with Cycles in Message class
Concomitant changes are being committed as well, including the io operator<<
for the Cycles class.
Nilay Vaish [Mon, 11 Feb 2013 03:26:24 +0000 (21:26 -0600)]
ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.
Nilay Vaish [Mon, 11 Feb 2013 03:26:23 +0000 (21:26 -0600)]
base: add some mathematical operators to Cycles class
Nilay Vaish [Mon, 11 Feb 2013 03:26:22 +0000 (21:26 -0600)]
ruby: modifies histogram add() function
This patch modifies the Histogram class' add() function so that it can add
linear histograms as well. The function assumes that the left end point of
the ranges of the two histograms are the same. It also assumes that when
the ranges of the two histogram are changed to accomodate an element not in
the range, the factor used in changing the range is same for both the
histograms.
This function is then used in removing one of the calls to the global
profiler*. The histograms for recording the delays incurred in processing
different requests are now maintained by the controllers. The profiler
adds these histograms when it needs to print the stats.
Nilay Vaish [Mon, 11 Feb 2013 03:26:22 +0000 (21:26 -0600)]
ruby: record fully busy cycle with in the controller
This patch does several things. First, the counter for fully busy cycles for a
controller is now kept with in the controller, instead of being part of the profiler.
Second, the topology class no longer keeps an array of controllers which was only
used for printing stats. Instead, ruby system will now ask each controller to print
the stats. Thirdly, the statistical variable for recording how many different types
were created is being moved in to the controller from the profiler. Note that for
printing, the profiler will collate results from different controllers.
Andreas Sandberg [Sun, 10 Feb 2013 12:23:56 +0000 (13:23 +0100)]
base: Fix broken IPython argument handling
Prior to this changeset, we used to clear sys.argv before entering the
IPython shell. This caused some versions of IPython to crash because
they assume argv[0] to exist. The correct way of overriding the
arguments passed to IPython is to set the argv keyword argument when
initializing the shell.
Andreas Sandberg [Sun, 10 Feb 2013 12:23:54 +0000 (13:23 +0100)]
config: Don't call sys.exit in interactive mode in run()
The run() method in Simulation.py used to call sys.exit() when the
simulator exits. This is undesirable when user has requested the
simulator to be run in interactive mode since it causes the simulator
to exit rather than entering the interactive Python environment.
Nilay Vaish [Fri, 1 Feb 2013 03:26:29 +0000 (21:26 -0600)]
sim: remove unused struct priority_compare
Nilay Vaish [Thu, 31 Jan 2013 15:44:20 +0000 (09:44 -0600)]
ruby: correct computation of number of bits required for address
The number of bits required for an address was set to floorLog2(memory size).
This is correct under the assumption that the memory size is a power of 2,
which is not always true. Hence, floorLog2 is being replaced with ceilLog2.
Andreas Hansson [Thu, 31 Jan 2013 12:49:18 +0000 (07:49 -0500)]
mem: Add comments for the DRAM address decoding
This patch adds more verbose comments to explain the two different
address mapping schemes of the DRAM controller.
Andreas Hansson [Thu, 31 Jan 2013 12:49:16 +0000 (07:49 -0500)]
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Andreas Hansson [Thu, 31 Jan 2013 12:49:14 +0000 (07:49 -0500)]
mem: Add DDR3 and LPDDR2 DRAM controller configurations
This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.
The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
Ani Udipi [Thu, 31 Jan 2013 12:49:14 +0000 (07:49 -0500)]
mem: Add tTAW and tFAW to the SimpleDRAM model
This patch adds two additional scheduling constraints to the DRAM
controller model, to constrain the activation rate. The two metrics
are determine the size of the activation window in terms of the number
of activates and the minimum time required for that number of
activates. This maps to current DDRx, LPDDRx and WIOx standards that
have either tFAW (4 activate window) or tTAW (2 activate window)
scheduling constraints.
Andreas Hansson [Thu, 31 Jan 2013 12:49:13 +0000 (07:49 -0500)]
mem: Separate out the different cases for DRAM bus busy time
This patch changes how the data bus busy time is calculated such that
it is delayed to the actual scheduling time of the request as opposed
to being done as soon as possible.
This patch changes a bunch of statistics, and the stats update is
bundled together with the introruction of tFAW/tTAW and the named DRAM
configurations like DDR3 and LPDDR2.
Anthony Gutierrez [Tue, 29 Jan 2013 01:19:42 +0000 (20:19 -0500)]
cache: remove drainManager because it's not used
the cache drainManager is set but never cleared, this is because
the cache itself does not need to be drained and thus never
triggers a signalDrainDone(). because the drainManager variable
is not used properly and does not appear to be necessary it has
been removed with this patch.
Nilay Vaish [Mon, 28 Jan 2013 14:24:40 +0000 (08:24 -0600)]
Andreas Hansson [Mon, 28 Jan 2013 12:44:26 +0000 (07:44 -0500)]
stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3
This patch bumps the stats for 20.parser for ARM o3-timing to reflect
a namechange of the branch predictor.
Nilay Vaish [Mon, 28 Jan 2013 12:14:18 +0000 (06:14 -0600)]
ruby: remove get_time()
This patch replaces get_time() in *.sm files with curCycle() which
is now possible since controllers are clocked objects.
Nilay Vaish [Mon, 28 Jan 2013 12:11:42 +0000 (06:11 -0600)]
ruby: remove call to curCycle in panic()
The panic() function already prints the current tick value. This call to
curCycle() is as such redundant. Since we are trying to move towards multiple
clock domains, this call will print misleading time.
Nilay Vaish [Thu, 24 Jan 2013 18:29:00 +0000 (12:29 -0600)]
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
branch predictor: move out of o3 and inorder cpus
This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.
This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.
--HG--
rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc
rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh
rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh
rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
Andrea Pellegrini [Tue, 22 Jan 2013 06:13:28 +0000 (00:13 -0600)]
o3 cpu: fix zero reg problem
There was an issue w/ the rename logic, which would assign a previous physical
register to the ZeroReg architectural register in x86. This issue was giving
problems for instructions squashed in threads w/ ID different from 0,
sometimes allowing non-mispredicted instructions to obtain a value different
from zero when reading the zeroReg.
Nilay Vaish [Tue, 22 Jan 2013 06:10:10 +0000 (00:10 -0600)]
x86, cpu: corrects
270c9a75e91f, take over decoder on cpu switch
The changes made by the changeset
270c9a75e91f do not work well with switching
of cpus. The problem is that decoder for the old thread context holds state
that is not taken over by the new decoder.
This patch adds a takeOverFrom() function to Decoder class in each ISA. Except
for x86, functions in other ISAs are blank. For x86, the function copies state
from the old decoder to the new decoder.
Andreas Hansson [Mon, 21 Jan 2013 14:20:18 +0000 (09:20 -0500)]
scons: Disable protobuf if pkg-config and CheckLib fails
This patch changes the use of pkg-config such that protobuf is still
evaluated with CheckLib even if it fails. This is to allow setups
where libprotobuf is available, but not configured through
protobuf. Moreover, if CheckLib fails to use libprotobuf then all the
tracing is disabled, but scons is allowed to continue with a warning.
Joel Hestness [Sat, 19 Jan 2013 21:14:54 +0000 (15:14 -0600)]
O3 IEW: Make incrWb and decrWb clearer
Move the increment/decrement of wbOutstanding outside of the comparison
in incrWb and decrWb in the IEW. This also fixes a compiler bug with gcc
4.4.7, which incorrectly optimizes "-- ==" as "-=".
Nilay Vaish [Thu, 17 Jan 2013 19:10:12 +0000 (13:10 -0600)]
ruby: remove calls to g_system_ptr->getTime()
This patch further removes calls to g_system_ptr->getTime() where ever other
clocked objects are available for providing current time.
Nilay Vaish [Tue, 15 Jan 2013 13:43:23 +0000 (07:43 -0600)]
x86 regressions: updates due to new instructions and cpuid
Nilay Vaish [Tue, 15 Jan 2013 13:43:21 +0000 (07:43 -0600)]
x86 cpuid: enable clflush
Note that clflush is only being enabled. It is not implemented
in actual. A warning is printed if the cpu encounters a clflush
instruction. We need to enable this instruction in cpuid since
JRE 1.7 tests for it.
Nilay Vaish [Tue, 15 Jan 2013 13:43:21 +0000 (07:43 -0600)]
x86: implements fsin, fcos instructions
Nilay Vaish [Tue, 15 Jan 2013 13:43:20 +0000 (07:43 -0600)]
x86: implements emms instruction
Nilay Vaish [Tue, 15 Jan 2013 13:43:19 +0000 (07:43 -0600)]
x86: implement fabs, fchs instructions
Nilay Vaish [Mon, 14 Jan 2013 16:20:16 +0000 (10:20 -0600)]
regressions: update stats due to changes in ruby obj hierarchy
Malek Musleh [Mon, 14 Jan 2013 16:05:14 +0000 (10:05 -0600)]
config: move ruby objects under ruby_system in obj hierarchy
This patch moves the contollers to be children of the ruby_system instead of
'system' under the python object hierarchy. This is so that these objects
can inherit some of the ruby_system's parameter values without resorting to
calling a global system pointer during run-time.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Malek Musleh [Mon, 14 Jan 2013 16:05:12 +0000 (10:05 -0600)]
ruby sequencer: converts cycles to ticks in deadlock panic()
This patch converts the panic() print outs in the Sequencer::wakeup()
call from ruby cycles to Ticks(). This makes it easier to debug deadlocks
with the ProtocolTrace flag so the issue time indicated in the panic message
can be quickly searched for.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Mon, 14 Jan 2013 16:05:10 +0000 (10:05 -0600)]
Ruby: remove reference to g_system_ptr from class Message
This patch was initiated so as to remove reference to g_system_ptr,
the pointer to Ruby System that is used for getting the current time.
That simple change actual requires changing a lot many things in slicc and
garnet. All these changes are related to how time is handled.
In most of the places, g_system_ptr has been replaced by another clock
object. The changes have been done under the assumption that all the
components in the memory system are on the same clock frequency, but the
actual clocks might be distributed.
Nilay Vaish [Mon, 14 Jan 2013 16:04:21 +0000 (10:04 -0600)]
Ruby: use ClockedObject in Consumer class
Many Ruby structures inherit from the Consumer, which is used for scheduling
events. The Consumer used to relay on an Event Manager for scheduling events
and on g_system_ptr for time. With this patch, the Consumer will now use a
ClockedObject to schedule events and to query for current time. This resulted
in several structures being converted from SimObjects to ClockedObjects. Also,
the MessageBuffer class now requires a pointer to a ClockedObject so as to
query for time.
Andreas Hansson [Mon, 14 Jan 2013 15:23:56 +0000 (10:23 -0500)]
scons: Address clang 3.2 compilation error
This patch fixes a compilation error encountered using clang 3.2 on OSX.
Andreas Hansson [Mon, 14 Jan 2013 15:23:54 +0000 (10:23 -0500)]
stats: Bump failing x86 regression stats
This patch bumps the stats of mcf and twolf for the o3 CPU such that
the regressions pass.
Nilay Vaish [Sun, 13 Jan 2013 04:11:16 +0000 (22:11 -0600)]
base simple cpu: removes commented out code about cache ops
Nilay Vaish [Sun, 13 Jan 2013 04:09:48 +0000 (22:09 -0600)]
x86: Changes to decoder, corrects 9376
The changes made by the changeset 9376 were not quite correct. The patch made
changes to the code which resulted in decoder not getting initialized correctly
when the state was restored from a checkpoint.
This patch adds a startup function to each ISA object. For x86, this function
sets the required state in the decoder. For other ISAs, the function is empty
right now.
Ali Saidi [Tue, 8 Jan 2013 22:12:22 +0000 (17:12 -0500)]
config: Fix issue with changeset:
a4739b6f799d.
Ali Saidi [Tue, 8 Jan 2013 13:54:16 +0000 (08:54 -0500)]
stats: update stats for previous six changes
Lluís Vilanova [Tue, 8 Jan 2013 13:54:13 +0000 (08:54 -0500)]
util: add writefile to m5 util program for x86
Lluís Vilanova [Tue, 8 Jan 2013 13:54:12 +0000 (08:54 -0500)]
util: add m5_fail op.
Used as a command in full-system scripts helps the user ensure the benchmarks have finished successfully.
For example, one can use:
/path/to/benchmark args || /sbin/m5 fail 1
and thus ensure gem5 will exit with an error if the benchmark fails.
Tao Zhang [Tue, 8 Jan 2013 13:54:11 +0000 (08:54 -0500)]
sim: Fix early termination in multi-core simulation under SE mode.
When "-I" (maximum instruction number) and "-F" (fastforward instruction
number) are applied together, gem5 immediately exits after the cpu switching.
The reason is that multiple exit events may be generated in the same cycle by
Atomic CPU and inserted to mainEventQueue. However, mainEventQueue can only
serve one exit event in one cycle. Therefore, the rest exit events are left in
mainEventQueue without being descheduled or deleted, which causes gem5 exits
immediately after the system resumes by cpu switching.
Mitch Hayenga [Tue, 8 Jan 2013 13:54:07 +0000 (08:54 -0500)]
arm: add access syscall for ARM SE mode
This patch adds the "access" syscall for ARM SE as required by some spec2006
benchmarks.
Mitch Hayenga [Tue, 8 Jan 2013 13:54:07 +0000 (08:54 -0500)]
mem: Make LL/SC locks fine grained
The current implementation in gem5 just keeps a list of locks per cacheline.
Due to this, a store to a non-overlapping portion of the cacheline can cause an
LL/SC pair to fail. This patch simply adds an address range to the lock
structure, so that the lock is only invalidated if the store overlaps the lock
range.
Mitch Hayenga [Tue, 8 Jan 2013 13:54:06 +0000 (08:54 -0500)]
mem: Fix use-after-free bug
Running with valgrind I noticed a use after free originating from
simple_mem.cc. It looks like this is a known issue and this additional call
site was missed in an earlier patch.
Andreas Sandberg [Mon, 7 Jan 2013 21:56:39 +0000 (16:56 -0500)]
dev: Fix infinite recursion in DMA devices
The DMA device sometimes calls the process() method on a completion
event directly instead of scheduling it on the current tick. This
breaks some devices that assume that the completion handler won't be
called until the current event handler has returned. Specifically, it
causes infinite recursion in the IdeDisk component because it does not
advance its chunk generator until after a dmaRead()/dmaWrite() has
returned. This changeset removes this mico-optimization and schedules
the event in the current tick instead. This way the semantics event
handling stay the same even when the delay is 0.
Andreas Sandberg [Mon, 7 Jan 2013 21:56:37 +0000 (16:56 -0500)]
util: Fix stack corruption in the m5 util
The number of arguments specified when calling parse_int_args() in
do_exit() is incorrect. This leads to stack corruption since it causes
writes past the end of the ints array.
Sascha Bischoff [Mon, 7 Jan 2013 21:56:36 +0000 (16:56 -0500)]
stats: Fix swig wrapping for Tick in stats
Tick was not correctly wrapped for the stats system, and therefore it was not
possible to configure the stats dumping from the python scripts without
defining Ticks as long long. This patch fixes the wrapping of Tick by copying
the typemap of uint64_t to Tick.
Ali Saidi [Mon, 7 Jan 2013 18:05:54 +0000 (13:05 -0500)]
stats: update stats for previous changes.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:52 +0000 (13:05 -0500)]
cpu: Unify the serialization code for all of the CPU models
Cleanup the serialization code for the simple CPUs and the O3 CPU. The
CPU-specific code has been replaced with a (un)serializeThread that
serializes the thread state / context of a specific thread. Assuming
that the thread state class uses the CPU-specific thread state uses
the base thread state serialization code, this allows us to restore a
checkpoint with any of the CPU models.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:52 +0000 (13:05 -0500)]
tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:48 +0000 (13:05 -0500)]
cpu: Flush TLBs on switchOut()
This changeset inserts a TLB flush in BaseCPU::switchOut to prevent
stale translations when doing repeated switching. Additionally, the
TLB flushing functionality is exported to the Python to make debugging
of switching/checkpointing easier.
A simulation script will typically use the TLB flushing functionality
to generate a reference trace. The following sequence can be used to
simulate a handover (this depends on how drain is implemented, but is
generally the case) between identically configured CPU models:
m5.drain(test_sys)
[ cpu.flushTLBs() for cpu in test_sys.cpu ]
m5.resume(test_sys)
The generated trace should normally be identical to a trace generated
when switching between identically configured CPU models or
checkpointing and resuming.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:47 +0000 (13:05 -0500)]
mem: Fix guest corruption when caches handle uncacheable accesses
When the classic gem5 cache sees an uncacheable memory access, it used
to ignore it or silently drop the cache line in case of a
write. Normally, there shouldn't be any data in the cache belonging to
an uncacheable address range. However, since some architecture models
don't implement cache maintenance instructions, there might be some
dirty data in the cache that is discarded when this happens. The
reason it has mostly worked before is because such cache lines were
most likely evicted by normal memory activity before a TLB flush was
requested by the OS.
Previously, the cache model would invalidate cache lines when they
were accessed by an uncacheable write. This changeset alters this
behavior so all uncacheable memory accesses cause a cache flush with
an associated writeback if necessary. This is implemented by reusing
the cache flushing machinery used when draining the cache, which
implies that writebacks are performed using functional accesses.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Rewrite O3 draining to avoid stopping in microcode
Previously, the O3 CPU could stop in the middle of a microcode
sequence. This patch makes sure that the pipeline stops when it has
committed a normal instruction or exited from a microcode
sequence. Additionally, it makes sure that the pipeline has no
instructions in flight when it is drained, which should make draining
more robust.
Draining is controlled in the commit stage, which checks if the next
PC after a committed instruction is in microcode. If this isn't the
case, it requests a squash of all instructions after that the
instruction that just committed and immediately signals a drain stall
to the fetch stage. The CPU then continues to execute until the
pipeline and all associated buffers are empty.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Make sure that a drained atomic CPU isn't executing ucode
Currently, the atomic CPU can be in the middle of a microcode sequence
when it is drained. This leads to two problems:
* When switching to a hardware virtualized CPU, we obviously can't
execute gem5 microcode.
* Since curMacroStaticInst is populated when executing microcode,
repeated switching between CPUs executing microcode leads to
incorrect execution.
After applying this patch, the CPU will be on a proper instruction
boundary, which means that it is safe to switch to any CPU model
(including hardware virtualized ones). This changeset fixes a bug
where the multiple switches to the same atomic CPU sometimes corrupts
the target state because of dangling pointers to the currently
executing microinstruction.
Note: This changeset moves tick event descheduling from switchOut() to
drain(), which makes timing consistent between just draining a system
and draining /and/ switching between two atomic CPUs. This makes
debugging quite a lot easier (execution traces get the same timing),
but the latency of the last instruction before a drain will not be
accounted for correctly (it will always be 1 cycle).
Note 2: This changeset removes so_state variable, the locked variable,
and the tickEvent from checkpoints since none of them contain state
that needs to be preserved across checkpoints. The so_state is made
redundant because we don't use the drain state variable anymore, the
lock variable should never be set when the system is drained, and the
tick event isn't scheduled.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Make sure that a drained timing CPU isn't executing ucode
Currently, the timing CPU can be in the middle of a microcode sequence
or multicycle (stayAtPC is true) instruction when it is drained. This
leads to two problems:
* When switching to a hardware virtualized CPU, we obviously can't
execute gem5 microcode.
* If stayAtPC is true we might execute half of an instruction twice
when restoring a checkpoint or switching CPUs, which leads to an
incorrect execution.
After applying this patch, the CPU will be on a proper instruction
boundary, which means that it is safe to switch to any CPU model
(including hardware virtualized ones). This changeset also fixes a bug
where the timing CPU sometimes switches out with while stayAtPC is
true, which corrupts the target state after a CPU switch or
checkpoint.
Note: This changeset removes the so_state variable from checkpoints
since the drain state isn't used anymore.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Fix broken thread context handover
The thread context handover code used to break when multiple handovers
were performed during the same quiesce period. Previously, the thread
contexts would assign the TC pointer in the old quiesce event to the
new TC. This obviously broke in cases where multiple switches were
performed within the same quiesce period, in which case the TC pointer
in the quiesce event would point to an old CPU.
The new implementation deschedules pending quiesce events in the old
TC and schedules a new quiesce event in the new TC. The code has been
refactored to remove most of the code duplication.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:46 +0000 (13:05 -0500)]
cpu: Fix O3 LSQ debug dumping constness and formatting
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
arm: Invalidate cached TLB configuration in drainResume
Currently, we invalidate the cached miscregs in
TLB::unserialize(). The intended use of the drainResume() method is to
invalidate cached state and prepare the system to resume after a CPU
handover or (un)serialization. This patch moves the TLB miscregs
invalidation code to the drainResume() method to avoid surprising
behavior.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
arm: Fix draining of the pagetable walker when squashing
Since the page table walker only checks if a drain has completed in
doL1DescriptorWrapper() and doL2DescriptorWrapper(), it sometimes
looses track of a drain request if there is a squash. This changeset
adds a completeDrain() call after squashing requests in the pending
queue, which fixes this issue.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
cpu: Fix broken squashAfter implementation in O3 CPU
Commit can currently both commit and squash in the same cycle. This
confuses other stages since the signals coming from the commit stage
can only signal either a squash or a commit in a cycle. This changeset
changes the behavior of squashAfter so that it commits all
instructions, including the instruction that requested the squash, in
the first cycle and then starts to squash in the next cycle.
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
o3 cpu: Remove unused variables
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
tests: Update the ignore regexps to reflect the M5->gem5 name change
Andreas Sandberg [Mon, 7 Jan 2013 18:05:45 +0000 (13:05 -0500)]
sim: Remove unused variables