yosys.git
5 years agoImprove pattern matcher to match subsets of $dffe? cells
Eddie Hung [Thu, 18 Jul 2019 21:08:18 +0000 (14:08 -0700)]
Improve pattern matcher to match subsets of $dffe? cells

5 years agoImprove A/B reg packing
Eddie Hung [Thu, 18 Jul 2019 20:30:35 +0000 (13:30 -0700)]
Improve A/B reg packing

5 years agoDo not autoremove A/B registers since they might have other consumers
Eddie Hung [Thu, 18 Jul 2019 20:22:22 +0000 (13:22 -0700)]
Do not autoremove A/B registers since they might have other consumers

5 years agoFix xilinx_dsp index cast
Eddie Hung [Thu, 18 Jul 2019 20:18:04 +0000 (13:18 -0700)]
Fix xilinx_dsp index cast

5 years agoFix signed multiplier decomposition
Eddie Hung [Thu, 18 Jul 2019 20:11:26 +0000 (13:11 -0700)]
Fix signed multiplier decomposition

5 years agoUse single DSP_SIGNEDONLY macro
Eddie Hung [Thu, 18 Jul 2019 20:09:55 +0000 (13:09 -0700)]
Use single DSP_SIGNEDONLY macro

5 years agoWorking for unsigned
Eddie Hung [Thu, 18 Jul 2019 17:53:18 +0000 (10:53 -0700)]
Working for unsigned

5 years agoCleanup
Eddie Hung [Thu, 18 Jul 2019 16:20:48 +0000 (09:20 -0700)]
Cleanup

5 years agoWrong wildcard symbol
Eddie Hung [Thu, 18 Jul 2019 15:14:58 +0000 (08:14 -0700)]
Wrong wildcard symbol

5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung [Thu, 18 Jul 2019 15:11:33 +0000 (08:11 -0700)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agomul2dsp: Lower partial products always have unsigned inputs
David Shah [Thu, 18 Jul 2019 10:33:37 +0000 (11:33 +0100)]
mul2dsp: Lower partial products always have unsigned inputs

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMake all operands signed
Eddie Hung [Wed, 17 Jul 2019 21:25:40 +0000 (14:25 -0700)]
Make all operands signed

5 years agoUpdate comment
Eddie Hung [Wed, 17 Jul 2019 20:26:17 +0000 (13:26 -0700)]
Update comment

5 years agoPattern matcher to check pool of bits, not exactly
Eddie Hung [Wed, 17 Jul 2019 19:45:25 +0000 (12:45 -0700)]
Pattern matcher to check pool of bits, not exactly

5 years agoFix mul2dsp signedness
Eddie Hung [Wed, 17 Jul 2019 19:44:52 +0000 (12:44 -0700)]
Fix mul2dsp signedness

5 years agoA_SIGNED == B_SIGNED so flip both
Eddie Hung [Wed, 17 Jul 2019 18:34:18 +0000 (11:34 -0700)]
A_SIGNED == B_SIGNED so flip both

5 years agoSigSpec::remove_const() to return SigSpec&
Eddie Hung [Wed, 17 Jul 2019 17:44:11 +0000 (10:44 -0700)]
SigSpec::remove_const() to return SigSpec&

5 years agoAdd DSP_{A,B}_SIGNEDONLY macro
Eddie Hung [Tue, 16 Jul 2019 22:55:13 +0000 (15:55 -0700)]
Add DSP_{A,B}_SIGNEDONLY macro

5 years agoSignedness
Eddie Hung [Tue, 16 Jul 2019 22:54:27 +0000 (15:54 -0700)]
Signedness

5 years agoSigned extension
Eddie Hung [Tue, 16 Jul 2019 22:54:07 +0000 (15:54 -0700)]
Signed extension

5 years agoRevert drop down to 24x16 multipliers for all
Eddie Hung [Tue, 16 Jul 2019 21:30:25 +0000 (14:30 -0700)]
Revert drop down to 24x16 multipliers for all

5 years agoMerge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Eddie Hung [Tue, 16 Jul 2019 21:18:36 +0000 (14:18 -0700)]
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

5 years agoAdd support {A,B,P}REG packing
Eddie Hung [Tue, 16 Jul 2019 21:06:32 +0000 (14:06 -0700)]
Add support {A,B,P}REG packing

5 years agoSigSpec::extract to allow negative length
Eddie Hung [Tue, 16 Jul 2019 21:06:07 +0000 (14:06 -0700)]
SigSpec::extract to allow negative length

5 years agoAdd support for {A,B,P}REG in DSP48E1
Eddie Hung [Tue, 16 Jul 2019 21:05:50 +0000 (14:05 -0700)]
Add support for {A,B,P}REG in DSP48E1

5 years agoxilinx: Add correct signed behaviour to DSP48E1 model
David Shah [Tue, 16 Jul 2019 16:53:08 +0000 (17:53 +0100)]
xilinx: Add correct signed behaviour to DSP48E1 model

Signed-off-by: David Shah <dave@ds0.me>
5 years agoxilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)
David Shah [Tue, 16 Jul 2019 15:46:41 +0000 (16:46 +0100)]
xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 signed)

Signed-off-by: David Shah <dave@ds0.me>
5 years agomul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH
David Shah [Tue, 16 Jul 2019 15:44:40 +0000 (16:44 +0100)]
mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH

Signed-off-by: David Shah <dave@ds0.me>
5 years agomul2dsp: Fix indentation
David Shah [Tue, 16 Jul 2019 15:19:32 +0000 (16:19 +0100)]
mul2dsp: Fix indentation

Signed-off-by: David Shah <dave@ds0.me>
5 years agoDo not swap if equals
Eddie Hung [Mon, 15 Jul 2019 23:52:37 +0000 (16:52 -0700)]
Do not swap if equals

5 years agoSigSpec::extend_u0() to return *this
Eddie Hung [Mon, 15 Jul 2019 23:23:12 +0000 (16:23 -0700)]
SigSpec::extend_u0() to return *this

5 years agoOops forgot these files
Eddie Hung [Mon, 15 Jul 2019 22:03:15 +0000 (15:03 -0700)]
Oops forgot these files

5 years agoAdd xilinx_dsp for register packing
Eddie Hung [Mon, 15 Jul 2019 21:46:31 +0000 (14:46 -0700)]
Add xilinx_dsp for register packing

5 years agoOUT port to Y in generic DSP
Eddie Hung [Mon, 15 Jul 2019 21:45:47 +0000 (14:45 -0700)]
OUT port to Y in generic DSP

5 years agoMove DSP mapping back out to dsp_map.v
Eddie Hung [Mon, 15 Jul 2019 21:18:44 +0000 (14:18 -0700)]
Move DSP mapping back out to dsp_map.v

5 years agoOnly swap if B_WIDTH > A_WIDTH
Eddie Hung [Mon, 15 Jul 2019 18:24:11 +0000 (11:24 -0700)]
Only swap if B_WIDTH > A_WIDTH

5 years agoTidy up
Eddie Hung [Mon, 15 Jul 2019 18:19:54 +0000 (11:19 -0700)]
Tidy up

5 years agoMove DSP48E1 model out of cells_xtra, initial multiply one in cells_sim
Eddie Hung [Mon, 15 Jul 2019 18:13:22 +0000 (11:13 -0700)]
Move DSP48E1 model out of cells_xtra, initial multiply one in cells_sim

5 years agoMerge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Mon, 15 Jul 2019 16:49:41 +0000 (09:49 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp

5 years agoMerge pull request #1194 from cr1901/miss-semi
Eddie Hung [Sun, 14 Jul 2019 20:36:34 +0000 (13:36 -0700)]
Merge pull request #1194 from cr1901/miss-semi

Fix missing semicolon in Windows-specific code in aigerparse.cc.

5 years agoFix missing semicolon in Windows-specific code in aigerparse.cc.
William D. Jones [Sun, 14 Jul 2019 15:57:08 +0000 (11:57 -0400)]
Fix missing semicolon in Windows-specific code in aigerparse.cc.

Signed-off-by: William D. Jones <thor0505@comcast.net>
5 years agoMerge pull request #1183 from whitequark/ice40-always-relut
Clifford Wolf [Fri, 12 Jul 2019 08:48:00 +0000 (10:48 +0200)]
Merge pull request #1183 from whitequark/ice40-always-relut

synth_ice40: switch -relut to be always on

5 years agosynth_ice40: switch -relut to be always on.
whitequark [Thu, 11 Jul 2019 10:46:30 +0000 (10:46 +0000)]
synth_ice40: switch -relut to be always on.

5 years agosynth_ice40: fix help text typo. NFC.
whitequark [Thu, 11 Jul 2019 10:46:45 +0000 (10:46 +0000)]
synth_ice40: fix help text typo. NFC.

5 years agoMerge pull request #1182 from koriakin/xc6s-bram
Eddie Hung [Thu, 11 Jul 2019 19:55:35 +0000 (12:55 -0700)]
Merge pull request #1182 from koriakin/xc6s-bram

synth_xilinx: Initial Spartan 6 block RAM inference support.

5 years agoMerge pull request #1185 from koriakin/xc-ff-init-vals
Eddie Hung [Thu, 11 Jul 2019 19:55:14 +0000 (12:55 -0700)]
Merge pull request #1185 from koriakin/xc-ff-init-vals

xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.

5 years agoxilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.
Marcin Kościelnicki [Thu, 11 Jul 2019 19:13:12 +0000 (21:13 +0200)]
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.

5 years agoEnable &mfs for abc9, even if it only currently works for ice40
Eddie Hung [Thu, 11 Jul 2019 15:49:06 +0000 (08:49 -0700)]
Enable &mfs for abc9, even if it only currently works for ice40

5 years agosynth_xilinx: Initial Spartan 6 block RAM inference support.
Marcin Kościelnicki [Tue, 2 Jul 2019 12:28:35 +0000 (14:28 +0200)]
synth_xilinx: Initial Spartan 6 block RAM inference support.

5 years agoMerge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
Clifford Wolf [Thu, 11 Jul 2019 05:25:52 +0000 (07:25 +0200)]
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark

write_verilog: write RTLIL::Sa aka - as Verilog ?

5 years agoMerge pull request #1179 from whitequark/attrmap-proc
Clifford Wolf [Thu, 11 Jul 2019 05:23:28 +0000 (07:23 +0200)]
Merge pull request #1179 from whitequark/attrmap-proc

attrmap: also consider process, switch and case attributes

5 years agoMove dsp_map.v into cells_map.v; cleanup synth_xilinx a little
Eddie Hung [Wed, 10 Jul 2019 23:00:03 +0000 (16:00 -0700)]
Move dsp_map.v into cells_map.v; cleanup synth_xilinx a little

5 years agoMerge remote-tracking branch 'origin/master' into xc7dsp
Eddie Hung [Wed, 10 Jul 2019 22:58:01 +0000 (15:58 -0700)]
Merge remote-tracking branch 'origin/master' into xc7dsp

5 years agoMerge pull request #1180 from YosysHQ/eddie/no_abc9_retime
Eddie Hung [Wed, 10 Jul 2019 21:38:13 +0000 (14:38 -0700)]
Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime

Error out if -abc9 and -retime specified

5 years agoMerge pull request #1148 from YosysHQ/xc7mux
Eddie Hung [Wed, 10 Jul 2019 21:38:00 +0000 (14:38 -0700)]
Merge pull request #1148 from YosysHQ/xc7mux

synth_xilinx to infer wide multiplexers using new '-widemux <min>' option

5 years agoError out if -abc9 and -retime specified
Eddie Hung [Wed, 10 Jul 2019 19:47:48 +0000 (12:47 -0700)]
Error out if -abc9 and -retime specified

5 years agoAdd some spacing
Eddie Hung [Wed, 10 Jul 2019 19:32:33 +0000 (12:32 -0700)]
Add some spacing

5 years agoAdd some ASCII art explaining mux decomposition
Eddie Hung [Wed, 10 Jul 2019 19:20:04 +0000 (12:20 -0700)]
Add some ASCII art explaining mux decomposition

5 years agoattrmap: also consider process, switch and case attributes.
whitequark [Wed, 10 Jul 2019 12:28:32 +0000 (12:28 +0000)]
attrmap: also consider process, switch and case attributes.

5 years agoMerge pull request #1177 from YosysHQ/clifford/async
Clifford Wolf [Wed, 10 Jul 2019 06:48:20 +0000 (08:48 +0200)]
Merge pull request #1177 from YosysHQ/clifford/async

Fix clk2fflogic adff reset semantic to negative hold time on reset

5 years agoCall muxpack and pmux2shiftx before cmp2lut
Eddie Hung [Wed, 10 Jul 2019 04:26:38 +0000 (21:26 -0700)]
Call muxpack and pmux2shiftx before cmp2lut

5 years agoRestore opt_clean back to original place
Eddie Hung [Tue, 9 Jul 2019 21:29:58 +0000 (14:29 -0700)]
Restore opt_clean back to original place

5 years agoRestore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6
Eddie Hung [Tue, 9 Jul 2019 21:28:54 +0000 (14:28 -0700)]
Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6

5 years agosynth_ecp5: Fix typo in copyright header
David Shah [Tue, 9 Jul 2019 21:26:10 +0000 (22:26 +0100)]
synth_ecp5: Fix typo in copyright header

Signed-off-by: David Shah <dave@ds0.me>
5 years agoMerge pull request #1174 from YosysHQ/eddie/fix1173
Clifford Wolf [Tue, 9 Jul 2019 20:59:51 +0000 (22:59 +0200)]
Merge pull request #1174 from YosysHQ/eddie/fix1173

Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero

5 years agoMerge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
Clifford Wolf [Tue, 9 Jul 2019 20:51:25 +0000 (22:51 +0200)]
Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position

write_verilog: fix placement of case attributes

5 years agoFix tests/various/async FFL test
Clifford Wolf [Tue, 9 Jul 2019 20:44:39 +0000 (22:44 +0200)]
Fix tests/various/async FFL test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove tests/various/async, disable failing ffl test
Clifford Wolf [Tue, 9 Jul 2019 20:21:25 +0000 (22:21 +0200)]
Improve tests/various/async, disable failing ffl test

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoExtend using A[1] to preserve don't care
Eddie Hung [Tue, 9 Jul 2019 19:35:41 +0000 (12:35 -0700)]
Extend using A[1] to preserve don't care

5 years agoMerge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc
Eddie Hung [Tue, 9 Jul 2019 19:19:40 +0000 (12:19 -0700)]
Merge pull request #1171 from YosysHQ/revert-1166-eddie/synth_keepdc

Revert "Add "synth -keepdc" option"

5 years agoMerge remote-tracking branch 'origin/eddie/fix1173' into xc7mux
Eddie Hung [Tue, 9 Jul 2019 19:16:33 +0000 (12:16 -0700)]
Merge remote-tracking branch 'origin/eddie/fix1173' into xc7mux

5 years agowrite_verilog: fix placement of case attributes. NFC.
whitequark [Tue, 9 Jul 2019 19:14:03 +0000 (19:14 +0000)]
write_verilog: fix placement of case attributes. NFC.

5 years agoIncrement _TECHMAP_BITS_CONNMAP_ by one since counting from zero
Eddie Hung [Tue, 9 Jul 2019 19:14:00 +0000 (12:14 -0700)]
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero

5 years agoAdd tests/various/async.{sh,v}
Clifford Wolf [Tue, 9 Jul 2019 18:58:59 +0000 (20:58 +0200)]
Add tests/various/async.{sh,v}

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoImprove tests/various/run-test.sh
Clifford Wolf [Tue, 9 Jul 2019 18:58:28 +0000 (20:58 +0200)]
Improve tests/various/run-test.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agoAdd tests/simple_abc9/.gitignore
Clifford Wolf [Tue, 9 Jul 2019 18:58:01 +0000 (20:58 +0200)]
Add tests/simple_abc9/.gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>
5 years agowrite_verilog: write RTLIL::Sa aka - as Verilog ?.
whitequark [Tue, 9 Jul 2019 18:30:24 +0000 (18:30 +0000)]
write_verilog: write RTLIL::Sa aka - as Verilog ?.

Currently, the only ways (determined by grepping for regex \bSa\b) to
end up with RTLIL::Sa in a netlist is by reading a Verilog constant
with ? in it as a part of case, or by running certain FSM passes.
Both of these cases should be round-tripped back to ? in Verilog.

5 years agoExtend during mux decomposition with 1'bx
Eddie Hung [Tue, 9 Jul 2019 17:59:37 +0000 (10:59 -0700)]
Extend during mux decomposition with 1'bx

5 years agoFix typo and comments
Eddie Hung [Tue, 9 Jul 2019 17:38:07 +0000 (10:38 -0700)]
Fix typo and comments

5 years agoMerge pull request #1170 from YosysHQ/eddie/fix_double_underscore
Eddie Hung [Tue, 9 Jul 2019 17:22:57 +0000 (10:22 -0700)]
Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore

Rename __builtin_bswap32 -> bswap32

5 years agoMerge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung [Tue, 9 Jul 2019 17:22:49 +0000 (10:22 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux

5 years agosynth_xilinx to call commands of synth -coarse directly
Eddie Hung [Tue, 9 Jul 2019 17:21:54 +0000 (10:21 -0700)]
synth_xilinx to call commands of synth -coarse directly

5 years agoRevert "synth_xilinx to call "synth -run coarse" with "-keepdc""
Eddie Hung [Tue, 9 Jul 2019 17:15:02 +0000 (10:15 -0700)]
Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""

This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.

5 years agoRevert "Add "synth -keepdc" option"
Eddie Hung [Tue, 9 Jul 2019 17:14:23 +0000 (10:14 -0700)]
Revert "Add "synth -keepdc" option"

5 years agoRename __builtin_bswap32 -> bswap32
Eddie Hung [Tue, 9 Jul 2019 16:35:09 +0000 (09:35 -0700)]
Rename __builtin_bswap32 -> bswap32

5 years agoFix spacing
Eddie Hung [Tue, 9 Jul 2019 16:22:12 +0000 (09:22 -0700)]
Fix spacing

5 years agoFix spacing
Eddie Hung [Tue, 9 Jul 2019 16:16:00 +0000 (09:16 -0700)]
Fix spacing

5 years agoMerge pull request #1168 from whitequark/bugpoint-processes
Clifford Wolf [Tue, 9 Jul 2019 14:59:43 +0000 (16:59 +0200)]
Merge pull request #1168 from whitequark/bugpoint-processes

Add support for processes in bugpoint

5 years agoMerge pull request #1169 from whitequark/more-proc-cleanups
Clifford Wolf [Tue, 9 Jul 2019 14:59:18 +0000 (16:59 +0200)]
Merge pull request #1169 from whitequark/more-proc-cleanups

A new proc_prune pass

5 years agoMerge pull request #1163 from whitequark/more-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:57:16 +0000 (16:57 +0200)]
Merge pull request #1163 from whitequark/more-case-attrs

More support for case rule attributes

5 years agoMerge pull request #1162 from whitequark/rtlil-case-attrs
Clifford Wolf [Tue, 9 Jul 2019 14:56:29 +0000 (16:56 +0200)]
Merge pull request #1162 from whitequark/rtlil-case-attrs

Allow attributes on individual switch cases in RTLIL

5 years agoMerge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup
Clifford Wolf [Tue, 9 Jul 2019 14:49:08 +0000 (16:49 +0200)]
Merge pull request #1167 from YosysHQ/eddie/xc7srl_cleanup

Cleanup synth_xilinx SRL inference, make more consistent

5 years agoproc_prune: promote assigns to module connections when legal.
whitequark [Tue, 9 Jul 2019 08:14:52 +0000 (08:14 +0000)]
proc_prune: promote assigns to module connections when legal.

This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)

5 years agoproc_prune: new pass.
whitequark [Mon, 8 Jul 2019 15:19:01 +0000 (15:19 +0000)]
proc_prune: new pass.

The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.

5 years agobugpoint: add -assigns and -updates options.
whitequark [Tue, 9 Jul 2019 09:08:38 +0000 (09:08 +0000)]
bugpoint: add -assigns and -updates options.

5 years agoproc_clean: add -quiet option.
whitequark [Tue, 9 Jul 2019 08:57:57 +0000 (08:57 +0000)]
proc_clean: add -quiet option.

This is useful for other passes that call it often, like bugpoint.

5 years agoDecompose mux inputs in delay-orientated (rather than area) fashion
Eddie Hung [Tue, 9 Jul 2019 06:51:13 +0000 (23:51 -0700)]
Decompose mux inputs in delay-orientated (rather than area) fashion

5 years agoDo not call opt -mux_undef (part of -full) before muxcover
Eddie Hung [Tue, 9 Jul 2019 06:49:16 +0000 (23:49 -0700)]
Do not call opt -mux_undef (part of -full) before muxcover

5 years agoAdd one more comment
Eddie Hung [Tue, 9 Jul 2019 06:05:48 +0000 (23:05 -0700)]
Add one more comment

5 years agoLess thinking
Eddie Hung [Tue, 9 Jul 2019 06:02:57 +0000 (23:02 -0700)]
Less thinking