Ron Dreslinski [Mon, 9 Oct 2006 04:31:24 +0000 (00:31 -0400)]
Put a check in so people know not to create more than 8 memtesters.
--HG--
extra : convert_revision :
41ab297dc681b2601be1df33aba30c39f49466d8
Ron Dreslinski [Mon, 9 Oct 2006 04:28:26 +0000 (00:28 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
77b06379a520dd91f124c0a543e30ec3a9cd1452
Ron Dreslinski [Mon, 9 Oct 2006 04:27:41 +0000 (00:27 -0400)]
Don't create a response if one isn't needed.
--HG--
extra : convert_revision :
37bd230f527f64eb12779157869aae9dcfdde7fd
Ron Dreslinski [Mon, 9 Oct 2006 04:27:03 +0000 (00:27 -0400)]
Don't block responses even if the cache is blocked.
--HG--
extra : convert_revision :
a1558eb55806b2a3e7e63249601df2c143e2235d
Ron Dreslinski [Mon, 9 Oct 2006 04:26:10 +0000 (00:26 -0400)]
Update the Memtester, commit a config file/test for it.
src/cpu/SConscript:
Add memtester to the compilation environment.
Someone who knows this better should make the MemTest a cpu model parameter.
For now attached with the build of o3 cpu.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Update Memtest for new mem system
src/python/m5/objects/MemTest.py:
Update memtest python description
--HG--
extra : convert_revision :
d6a63e08fda0975a7abfb23814a86a0caf53e482
Lisa Hsu [Mon, 9 Oct 2006 04:12:16 +0000 (00:12 -0400)]
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd.
so you can restore by a command line like this:
m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3
configs/example/fs.py:
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.
--HG--
extra : convert_revision :
bf9c8d3265a3875cdfb6a878005baa7ae29af90d
Lisa Hsu [Mon, 9 Oct 2006 03:19:03 +0000 (23:19 -0400)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
a0775bf59ff7049b76917b1ab551bc28efd56b3d
Lisa Hsu [Mon, 9 Oct 2006 03:18:19 +0000 (23:18 -0400)]
post checkpoint restoration the bus ranges need to be re-initialized for ALL pci devs, not just ide.
src/dev/ide_ctrl.cc:
this range change needs to be done for all pio devices, not just the ide.
src/dev/pcidev.cc:
range change needs to be done at here, not in the ide_ctrl file.
--HG--
extra : convert_revision :
60c65c55e965b02d671dba7aa8793e5a81f40348
Lisa Hsu [Mon, 9 Oct 2006 03:16:40 +0000 (23:16 -0400)]
add in serialization of AtomicSimpleCPU _status. This is needed because right now unserializing breaks an assert since CPU status is not saved. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
src/cpu/simple/atomic.cc:
add in serialization of AtomicSimpleCPU _status. Kev says that this will break uniform serialization across CPUs since each type of CPU has its own "status" enum set. So, the repercussions are that if you serialize in this CPU, you must first unserialize in this CPU before switching to something else you want.
--HG--
extra : convert_revision :
7000f660aecea6fef712bf81853d9a7b90d625ee
Steve Reinhardt [Mon, 9 Oct 2006 02:11:19 +0000 (19:11 -0700)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision :
755af6a54b309417afbc022544ee72f96bdac493
Steve Reinhardt [Mon, 9 Oct 2006 02:11:06 +0000 (19:11 -0700)]
Set cpu_id params (required by ll/sc code now).
--HG--
extra : convert_revision :
e0f7ccbeccca191a8edb54494d2b4f9369e9914c
Lisa Hsu [Mon, 9 Oct 2006 02:05:34 +0000 (22:05 -0400)]
update for m5 base linux. (the last changes were for the latest m5hack, i.e. with nate's stuff in it).
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
update for m5 base linux.
--HG--
extra : convert_revision :
c78a1748bf8a0950450c29a7b96bb8735c1bb3d2
Steve Reinhardt [Mon, 9 Oct 2006 01:26:59 +0000 (18:26 -0700)]
Fixes for Port proxies and proxy parameters.
--HG--
extra : convert_revision :
76b16fe2926611bd1c12c8ad7392355ad30a5138
Ron Dreslinski [Mon, 9 Oct 2006 01:08:27 +0000 (21:08 -0400)]
Update stats for functional path fix
--HG--
extra : convert_revision :
0f38abab28e7e44f1dc748c25938185651dd1b7d
Ron Dreslinski [Mon, 9 Oct 2006 00:47:50 +0000 (20:47 -0400)]
Make sure to propogate sendFunctional calls with functional not atomic.
src/mem/cache/cache_impl.hh:
Fix a error case by putting a panic in.
Make sure to propogate sendFunctional calls with functional not atomic.
--HG--
extra : convert_revision :
05d03f729a40cfa3ecb68bcba172eb560b24e897
Ron Dreslinski [Mon, 9 Oct 2006 00:30:42 +0000 (20:30 -0400)]
Fixes for functional path.
If the cpu needs to update any state when it gets a functional write (LSQ??)
then that code needs to be written.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
CPU's can recieve functional accesses, they need to determine if they need to do anything with them.
src/mem/bus.cc:
src/mem/bus.hh:
Make the fuctional path do the correct tye of snoop
--HG--
extra : convert_revision :
70d09f954b907a8aa9b8137579cd2b06e02ae2ff
Ron Dreslinski [Sun, 8 Oct 2006 23:05:48 +0000 (19:05 -0400)]
Only respond if the pkt needs a response.
Fix an issue with memory handling writebacks.
src/mem/cache/base_cache.hh:
src/mem/tport.cc:
Only respond if the pkt needs a response.
src/mem/physical.cc:
Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.
--HG--
extra : convert_revision :
7601987a7923e54a6d1a168def4f8133d8de19fd
Ron Dreslinski [Sun, 8 Oct 2006 22:49:30 +0000 (18:49 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
f3067efb7f3ff30158d541dfc52de4ea8edae576
Ron Dreslinski [Sun, 8 Oct 2006 22:48:03 +0000 (18:48 -0400)]
Move away from using the statusChange function on snoops. Clean up snooping code in general.
--HG--
extra : convert_revision :
5a57bfd7742a212047fc32e8cae0dc602fdc915c
Steve Reinhardt [Sun, 8 Oct 2006 21:48:24 +0000 (14:48 -0700)]
Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().
--HG--
extra : convert_revision :
f22ce3221d270ecf8631d3dcaed05753accd5461
Steve Reinhardt [Sun, 8 Oct 2006 21:07:23 +0000 (17:07 -0400)]
Update ref stats: ll/sc, cpu_id, new kernel (?)
--HG--
extra : convert_revision :
060cb7319c4474429917a6347a9a47f390208ec8
Steve Reinhardt [Sun, 8 Oct 2006 17:53:24 +0000 (10:53 -0700)]
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision :
6ce982d44924cc477e049b9adf359818908e72be
Steve Reinhardt [Sun, 8 Oct 2006 17:43:31 +0000 (10:43 -0700)]
Rename some vars for clarity.
--HG--
extra : convert_revision :
765283ae54d2d6b5885ea44c6c1813d4bcf18488
Steve Reinhardt [Sun, 8 Oct 2006 08:29:40 +0000 (04:29 -0400)]
Allocate new thread stacks and shared mem region via Process page table
for Tru64 thread library emulation.
--HG--
extra : convert_revision :
dbd307536e260e24ef79130d2aa88d84e33f03d4
Ali Saidi [Sat, 7 Oct 2006 18:49:10 +0000 (14:49 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head
--HG--
extra : convert_revision :
acab791328d16daace6dfbdc667067ddc68fb6ca
Ron Dreslinski [Sat, 7 Oct 2006 16:58:37 +0000 (12:58 -0400)]
Update stats for change in functional path in cache
--HG--
extra : convert_revision :
5abc964ca95b80522266c5c1bc5e661d41f2798a
Ron Dreslinski [Sat, 7 Oct 2006 16:55:37 +0000 (12:55 -0400)]
Fix a missing pointer
--HG--
extra : convert_revision :
2056b530d48fd004ab700f09e58f44adae3ea0e9
Ron Dreslinski [Sat, 7 Oct 2006 16:20:29 +0000 (12:20 -0400)]
No need to keep trying to request the data bus if we are already waiting.
--HG--
extra : convert_revision :
dbaad52ed8d0841dc9224661e3df0d8ef4989aa3
Ron Dreslinski [Sat, 7 Oct 2006 16:02:59 +0000 (12:02 -0400)]
Add mechanism for caches to handle failure of the fast path on responses.
For now, responses have priority over requests (may want to revist this).
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Add mechanism for caches to handle failure of the fast path on responses.
--HG--
extra : convert_revision :
01524c727d1bb300cc21bdc989eb862ec8bf0b7a
Ron Dreslinski [Sat, 7 Oct 2006 15:37:18 +0000 (11:37 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
10cdbc57c8fa1cae755e0a224bc74ea8f3782c75
Ron Dreslinski [Sat, 7 Oct 2006 15:36:55 +0000 (11:36 -0400)]
Fix infinite writebacks bug in cache.
src/mem/cache/cache_impl.hh:
Make sure to pop the list. Fixes infinite writeback bug.
src/mem/cache/miss/mshr_queue.cc:
Add an assert as sanity check in case .full() stops working again.
--HG--
extra : convert_revision :
d847e49a397eeb0b7c5ac060fcfc3eaeac921311
Kevin Lim [Sat, 7 Oct 2006 15:32:10 +0000 (11:32 -0400)]
Update refs.
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
Update refs. (Korey's initial push didn't use the default O3-timing config?)
--HG--
extra : convert_revision :
d6bc241534483114def9cf88d7815ddfc9c88fd1
Ali Saidi [Sat, 7 Oct 2006 01:46:04 +0000 (21:46 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head
--HG--
extra : convert_revision :
326605820dce7641058eb0cdc0ddb2cc9602f67e
Ali Saidi [Sat, 7 Oct 2006 01:45:34 +0000 (21:45 -0400)]
system.cc:
Make new_page() check for an out of memory condition
src/sim/system.cc:
Make new_page() check for an out of memory condition
--HG--
extra : convert_revision :
daee82788464fca186eb24285b5f43c9fabc25b3
Ron Dreslinski [Fri, 6 Oct 2006 13:28:16 +0000 (09:28 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
2f1bbe84c92879fd1bfa579adc62a367ece1cddd
Ron Dreslinski [Fri, 6 Oct 2006 13:27:59 +0000 (09:27 -0400)]
Another thread number removed
--HG--
extra : convert_revision :
4cfb83b8162745d686e8697f29f74f37b1a71525
Ron Dreslinski [Fri, 6 Oct 2006 13:15:53 +0000 (09:15 -0400)]
Remove threadnum from cache everywhere for now
Fix so that blocking for the same reason doesn't fail. I.E. multiple writebacks want to set the blocked flag.
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
Remove threadnum from cache everywhere for now
--HG--
extra : convert_revision :
7890712147655280b4f1439d486feafbd5b18b2b
Korey Sewell [Fri, 6 Oct 2006 08:24:02 +0000 (04:24 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/m5-clean
--HG--
extra : convert_revision :
25200efe03b7cf9b3c546c939be74210f65a196a
Korey Sewell [Fri, 6 Oct 2006 08:23:27 +0000 (04:23 -0400)]
add SMT hello world test - 2 threads
--HG--
extra : convert_revision :
54cb19d1325295895b6f0b992499bbb0216b45df
Lisa Hsu [Fri, 6 Oct 2006 05:29:50 +0000 (01:29 -0400)]
checkpoint recovery was screwed up because a new section was created in the middle of another section and messed up unserializing.
--HG--
extra : convert_revision :
7af15fdc9e8d203b26840a2eb5fef511b6a2b21d
Lisa Hsu [Fri, 6 Oct 2006 05:27:02 +0000 (01:27 -0400)]
there are two main thrusts of this changeset.
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again).
2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.
src/arch/alpha/isa/decoder.isa:
src/mem/cache/cache_impl.hh:
modify arg. order for new calling convention of exitSimLoop.
src/cpu/base.cc:
src/sim/main.cc:
src/sim/pseudo_inst.cc:
src/sim/root.cc:
now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args.
src/sim/sim_events.cc:
src/sim/sim_events.hh:
src/sim/sim_exit.hh:
add the periodicity of checkpointing back into the code.
to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.
--HG--
extra : convert_revision :
c61f4bf05517172edd2c83368fd10bb0f0678029
Lisa Hsu [Fri, 6 Oct 2006 04:42:39 +0000 (00:42 -0400)]
add an option for defining a directory in which to place all your checkpoints. if none, default is cwd.
--HG--
extra : convert_revision :
23a602c2d800c922346c9743cc0c583d178a0ee7
Lisa Hsu [Fri, 6 Oct 2006 04:39:49 +0000 (00:39 -0400)]
Merge zizzer:/bk/newmem
into zizzer.eecs.umich.edu:/z/hsul/newmem
--HG--
extra : convert_revision :
ecf61b323a93c9192450388c8812c26b919d06cb
Lisa Hsu [Fri, 6 Oct 2006 04:39:21 +0000 (00:39 -0400)]
update full system references for newest disk image from linux-dist.
--HG--
extra : convert_revision :
c1232dafff0d92d8041af1b9de1dc8c55ee50f40
Nathan Binkert [Fri, 6 Oct 2006 04:16:42 +0000 (21:16 -0700)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/research/m5/incoming
--HG--
extra : convert_revision :
b4d6a36ee07d858829369027127e00a2aec097fd
Nathan Binkert [Fri, 6 Oct 2006 04:14:43 +0000 (21:14 -0700)]
remove traces of binning
--HG--
extra : convert_revision :
b33cc67cfde04c9af6f50cbef538104e1298bedc
Ron Dreslinski [Fri, 6 Oct 2006 03:28:03 +0000 (23:28 -0400)]
Fixes for functional accesses to use the snoop path.
And small other tweaks to snooping coherence.
src/mem/cache/base_cache.hh:
Make timing response at the time of send.
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
Update probe interface to be bi-directional for functional accesses
src/mem/packet.hh:
Add the function to create an atomic response to a given request
--HG--
extra : convert_revision :
04075a117cf30a7df16e6d3ce485543cc77d4ca6
Ron Dreslinski [Fri, 6 Oct 2006 01:10:03 +0000 (21:10 -0400)]
First pass at snooping stuff that compiles and doesn't break.
Still need:
-Handle NACK's on the recieve side
-Distinguish top level caches
-Handle repsonses from caches failing the fast path
-Handle BusError and propogate it
-Fix the invalidate packet associated with snooping in the cache
src/mem/bus.cc:
Make sure to snoop on functional accesses
src/mem/cache/base_cache.cc:
Wait to make a request into a response until it is ready to be issued
src/mem/cache/base_cache.hh:
Support range changes for snoops
Set up snoop responses for cache->cache transfers
src/mem/cache/cache_impl.hh:
Only access the cache if it wasn't satisfied by cache->cache transfer
Handle snoop phases (detect block, then snoop)
Fix functional access to work properly (still need to fix snoop path for functional accesses)
--HG--
extra : convert_revision :
4c25f11d7a996c1f56f4f7b55dde87a344e5fdf8
Lisa Hsu [Thu, 5 Oct 2006 17:18:32 +0000 (13:18 -0400)]
fix the argument to m5.simulate() on a checkpoint.
src/sim/stat_control.cc:
add curTick to reset stats printf.
--HG--
extra : convert_revision :
da8cf5921e81b73f47d6831d539ca1fbdace3d1d
Nathan Binkert [Thu, 5 Oct 2006 10:37:43 +0000 (03:37 -0700)]
Static global object don't work well, if the variables are
accessed during the construction of another static global
object because there are no guarantees on ordering of
construction, so stick the static global into a function
as a static local and return a reference to the variable.
This fixes the exit callback stuff on my Mac.
--HG--
extra : convert_revision :
63a3844d0b5ee18e2011f1bc7ca7bb703284da94
Kevin Lim [Mon, 2 Oct 2006 22:13:42 +0000 (18:13 -0400)]
Oops, forgot to assign the option to the param context.
--HG--
extra : convert_revision :
022c3efaa3ade3fca3dfe554ececa4eeb396dc9c
Kevin Lim [Mon, 2 Oct 2006 22:12:21 +0000 (18:12 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision :
1010a4ee8e1abec0e8290637feee523ca9ef9a9b
Kevin Lim [Mon, 2 Oct 2006 22:10:10 +0000 (18:10 -0400)]
Be sure to set progress interval.
--HG--
extra : convert_revision :
793ca7d6af1deedf6b1fb4676288b11114f583a6
Kevin Lim [Mon, 2 Oct 2006 16:06:30 +0000 (12:06 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision :
9bfd96dfbd1d58d56ceaf0e266807c31cb578c34
Kevin Lim [Mon, 2 Oct 2006 16:04:24 +0000 (12:04 -0400)]
Add in ability to start a trace at a specific cycle.
--HG--
extra : convert_revision :
54098f3974d2a05d60e57113f7ceb46cb7a26672
Kevin Lim [Mon, 2 Oct 2006 15:58:09 +0000 (11:58 -0400)]
Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh:
This got changed to the wrong version by accident.
src/cpu/base.cc:
Fix up progress event to not schedule itself if the interval is set to 0.
src/cpu/base.hh:
Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here).
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
Remove float variable of instResult; it's always held within the double part now.
src/cpu/checker/cpu_impl.hh:
Use thread and not cpuXC.
src/cpu/o3/alpha/cpu_builder.cc:
src/cpu/o3/checker_builder.cc:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu_builder.cc:
src/python/m5/objects/BaseCPU.py:
Remove stats_reset_inst.
src/cpu/o3/commit_impl.hh:
src/cpu/ozone/lw_back_end_impl.hh:
Get TC, not XCProxy.
src/cpu/o3/cpu.cc:
Switch out updates from the version of m5 I have. Also remove serialize code that got added twice.
src/cpu/o3/iew_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/thread_state.hh:
Remove code that was added twice.
src/cpu/o3/lsq_unit.hh:
Add back in stats that got lost in the merge.
src/cpu/o3/lsq_unit_impl.hh:
Use proper method to get flags. Also wake CPU if we're coming back from a cache miss.
src/cpu/o3/thread_context_impl.hh:
src/cpu/o3/thread_state.hh:
Support profiling.
src/cpu/ozone/cpu.hh:
Update to use proper typename.
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/dyn_inst_impl.hh:
Updates for newmem.
src/cpu/ozone/lw_lsq_impl.hh:
Get flags correctly.
src/cpu/ozone/thread_state.hh:
Reorder constructor initialization, use tc.
src/sim/pseudo_inst.cc:
Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext.
--HG--
extra : convert_revision :
c5657f84155807475ab4a1e20d944bb6f0d79d94
Steve Reinhardt [Sun, 1 Oct 2006 05:42:18 +0000 (01:42 -0400)]
Move Python setup into Configure section so we can test whether the
setup is correct and provide meeaningful error messages when it's not.
Also fix for building on Cygwin where python lib is in /bin and not /lib.
--HG--
extra : convert_revision :
7a29ba17463de60c72b3d8b04e4c4f81fc64bf61
Kevin Lim [Sun, 1 Oct 2006 03:43:23 +0000 (23:43 -0400)]
Merge ktlim@zamp:./local/clean/o3-merge/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
configs/boot/micro_memlat.rcS:
configs/boot/micro_tlblat.rcS:
src/arch/alpha/ev5.cc:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa_traits.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.hh:
src/cpu/checker/cpu_impl.hh:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/params.hh:
src/cpu/o3/checker_builder.cc:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/checker_builder.cc:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/base.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.hh:
src/dev/ide_disk.cc:
src/python/m5/objects/O3CPU.py:
src/python/m5/objects/Root.py:
src/python/m5/objects/System.py:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/system.hh:
util/m5/m5.c:
Hand merge.
--HG--
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh
rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc
rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh
rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh
rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh
rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh
rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh
rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh
rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh
rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh
rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh
rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh
rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh
rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh
rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc
rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc
rename : cpu/thread_state.hh => src/cpu/thread_state.hh
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py
rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/system.hh => src/sim/system.hh
extra : convert_revision :
135d90e43f6cea89f9460ba4e23f4b0b85886e7d
Kevin Lim [Thu, 28 Sep 2006 04:14:15 +0000 (00:14 -0400)]
Updates to Ozone CPU.
cpu/ozone/cpu_impl.hh:
Be sure to update rename tables.
cpu/ozone/front_end_impl.hh:
Handle serialize instructions slightly differently. This allows front end to continue even if back end hasn't processed it yet.
cpu/ozone/lw_back_end_impl.hh:
Handle stores with faults properly.
cpu/ozone/lw_lsq.hh:
Handle committed stores properly.
cpu/ozone/lw_lsq_impl.hh:
Handle uncacheable loads properly.
--HG--
extra : convert_revision :
093edc2eee890139a9962c97c938575e6d313f09
Kevin Lim [Thu, 28 Sep 2006 04:09:27 +0000 (00:09 -0400)]
Minor changes plus updates to O3.
cpu/base.cc:
Have output message regardless of build.
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
Be sure to include all parameters.
cpu/o3/cpu.cc:
IEW also needs to switch out.
cpu/o3/iew_impl.hh:
Handle stores with faults properly.
cpu/o3/inst_queue_impl.hh:
Switch out properly, handle squashing properly.
cpu/o3/lsq_unit_impl.hh:
Minor fixes.
cpu/o3/mem_dep_unit_impl.hh:
Make sure mem dep unit is switched out properly.
cpu/o3/rename_impl.hh:
Switch out fix.
--HG--
extra : convert_revision :
b94deb83f724225c01166c84a1b3fdd3543cbe9a
Steve Reinhardt [Tue, 19 Sep 2006 00:12:46 +0000 (17:12 -0700)]
Add CoherenceProtocol object to objects list.
--HG--
extra : convert_revision :
46c14f37906c44100eaf4e7b66b882ff42fed014
Ali Saidi [Tue, 19 Sep 2006 00:12:45 +0000 (20:12 -0400)]
add boiler plate intel nic code
src/SConscript:
add intel nic to sconscript
src/dev/pcidev.cc:
fix bug with subsystemid value
src/python/m5/objects/Ethernet.py:
add intel nic to ethernet.py
src/python/m5/objects/Ide.py:
src/python/m5/objects/Pci.py:
Move config_latency into pci where it belogs
--HG--
extra : convert_revision :
7163aaf7b4098496518b0910cef62f2ce3dd574d
Gabe Black [Sun, 17 Sep 2006 07:46:30 +0000 (03:46 -0400)]
Adding what was tracedump but is now statetrace to the tree. Let me know if statetrace is also already taken.
util/statetrace/Makefile:
Makefile to build statetrace. Targets are:
statetrace: alias to build using the "native" compiler
statetrace-native: use the native compiler
statetrace-sparc: use the sparc cross compiler
I'll make this a little more fancy and capable later.
util/statetrace/arch/tracechild_i386.cc:
Implementation of i386 support
util/statetrace/arch/tracechild_i386.hh:
Declaration of i386 support
util/statetrace/arch/tracechild_sparc.cc:
implementation of SPARC support
util/statetrace/arch/tracechild_sparc.hh:
declaration of SPARC support
util/statetrace/printer.cc:
Implementation of the "Printer" objects which parse and output the state of the process after each instruction. There are currently two types of printers, nested ones and register ones. These are called NestingPrinter and RegPrinter respectively.
util/statetrace/printer.hh:
Declaration of "Printer" objects
util/statetrace/refcnt.hh:
This is copied from m5. I should use the one already in the tree, but I'll do that later.
util/statetrace/regstate.hh:
Interface for accessing registers.
util/statetrace/statetrace.cc:
Main file with argument parsing and the "main" function which contains the tracing loop.
util/statetrace/tracechild.cc:
Implementation of the base tracechild class.
util/statetrace/tracechild.hh:
Declaration of the base tracechild class.
util/statetrace/tracechild_arch.cc:
This file hooks in support for the appropriate architecture. Just the implementation is brought in, since the main program should ideally not have to know anything at all about an architecture other than it's interface.
util/statetrace/x86.format:
An example output template for x86. A few example SPARC templates will be added later.
--HG--
extra : convert_revision :
7c8bf8230907aba42ed1e707b9ca2d6da0d4e6d4
Gabe Black [Sun, 17 Sep 2006 07:00:55 +0000 (03:00 -0400)]
Finished changing how stat structures are translated, fixed the handling of various ids as LiveProcess parameters.
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.
--HG--
extra : convert_revision :
0198b838e5c09a730065dc6f018738145bc96269
Gabe Black [Sat, 16 Sep 2006 01:43:12 +0000 (21:43 -0400)]
Changes to correct stat behavior
--HG--
extra : convert_revision :
43e5788105738aebd79acb05301bb7da68bfe129
Gabe Black [Fri, 15 Sep 2006 04:59:39 +0000 (00:59 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision :
91aacb435c223e8c37f6ba0a458b0dee55edcaf2
Ali Saidi [Mon, 11 Sep 2006 21:57:30 +0000 (17:57 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head
--HG--
extra : convert_revision :
14ac24236ff65b7e489c1ce4b4e9a295966013b8
Ali Saidi [Mon, 11 Sep 2006 21:57:20 +0000 (17:57 -0400)]
add annotation code to m5
configs/common/Benchmarks.py:
add annotate test app
src/SConscript:
add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
add annotate instructions
src/base/traceflags.py:
Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
add anotate ops
--HG--
extra : convert_revision :
7f965c0d84e41ce34f2ec8ec27a009276d67d8d6
Steve Reinhardt [Fri, 8 Sep 2006 23:22:25 +0000 (19:22 -0400)]
Added cscope-find.py utility to generate file list for cscope.
--HG--
extra : convert_revision :
80f2db90f1c2406039d0447b84aa0442b7b974f8
Steve Reinhardt [Fri, 8 Sep 2006 23:10:11 +0000 (19:10 -0400)]
Add support for assigning lists of ports or proxies to VectorPorts.
Includes support for printing readable VectorPort and Proxy names
(via __str__).
--HG--
extra : convert_revision :
c48534a498b3036fe6ac45ff1606656546c79afb
Steve Reinhardt [Thu, 7 Sep 2006 06:07:06 +0000 (02:07 -0400)]
Update port numbers from new unproxy ordering.
--HG--
extra : convert_revision :
514d2c53bd6afa6bea43c37c1242b6775e86c556
Steve Reinhardt [Thu, 7 Sep 2006 05:37:35 +0000 (22:37 -0700)]
Try to make unproxy order more deterministic.
--HG--
extra : convert_revision :
0bc543014dced6dfed4122d4c1b8f22e6c8d7a13
Steve Reinhardt [Wed, 6 Sep 2006 22:36:50 +0000 (15:36 -0700)]
Delete some output files that never should have been
committed.
--HG--
extra : convert_revision :
29780a4cc82dc397681a2b4a61eaa658e6eed83e
Steve Reinhardt [Wed, 6 Sep 2006 05:04:34 +0000 (22:04 -0700)]
Enable proxies (Self/Parent) for specifying ports.
Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
--HG--
extra : convert_revision :
db73b6cdd004a82a08b2402afd1e16544cb902a4
Steve Reinhardt [Tue, 5 Sep 2006 20:24:47 +0000 (16:24 -0400)]
Update reference config.ini files to include port mappings.
--HG--
extra : convert_revision :
f9e91a60fa09b707d2a26be57f265b7ab1c07263
Steve Reinhardt [Tue, 5 Sep 2006 19:22:47 +0000 (12:22 -0700)]
Print ports in config.ini as well.
--HG--
extra : convert_revision :
703d3a57250613315735709de8f40a9956cee6e2
Steve Reinhardt [Tue, 5 Sep 2006 00:14:07 +0000 (17:14 -0700)]
More Python hacking to deal with config.py split
and resulting recursive import trickiness.
--HG--
extra : convert_revision :
1ea93861eb8d260c9f3920dda0b8106db3e03705
Steve Reinhardt [Mon, 4 Sep 2006 17:52:26 +0000 (10:52 -0700)]
Split config.py into multiple files.
Some tweaking to deal with mutually recursive imports.
--HG--
rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision :
166f7bfabfd20100e93d26a89382469465859988
Steve Reinhardt [Mon, 4 Sep 2006 17:40:33 +0000 (10:40 -0700)]
config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
src/python/m5/config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
--HG--
extra : convert_revision :
cb25ee1f4f77d1902511ee9aa766403733dd8841
Gabe Black [Sun, 3 Sep 2006 06:12:11 +0000 (02:12 -0400)]
Made system calls use the uid, etc parameters from the live process.
--HG--
extra : convert_revision :
2aadb87b4602324423aadb903010f5b49fcef41b
Gabe Black [Sun, 3 Sep 2006 06:10:05 +0000 (02:10 -0400)]
Fix up the parameters to getInstRecord
--HG--
extra : convert_revision :
0fac43035a2510d3a3f596d3d8f57193045570f6
Gabe Black [Sun, 3 Sep 2006 06:09:25 +0000 (02:09 -0400)]
Make the ASI constants available to the decoder.
--HG--
extra : convert_revision :
65f2e02ce8f5e4f0c8727ebf16c927c7a6a4fe7f
Gabe Black [Sun, 3 Sep 2006 06:08:24 +0000 (02:08 -0400)]
Make the auxiliary vectors use the uid, euid, gid and egid parameters from the live process
--HG--
extra : convert_revision :
945b5883a15a6df35709edea2731f54a2448e418
Gabe Black [Sun, 3 Sep 2006 06:05:44 +0000 (02:05 -0400)]
Fixing up parameters of getInstRecord
--HG--
extra : convert_revision :
4ce06ac4f7d135cc04b39cf0e957a2539c7e946d
Gabe Black [Sun, 3 Sep 2006 06:04:25 +0000 (02:04 -0400)]
Added uid, euid, gid, egid, pid and ppid parameters to a live process.
--HG--
extra : convert_revision :
2101be8000bcdaf683730cfc079b4b78e34365d0
Gabe Black [Sun, 3 Sep 2006 06:02:56 +0000 (02:02 -0400)]
A quick fix to isolate the tracing code to SPARC
--HG--
extra : convert_revision :
90c77f4d01101cad55f60d528b2a8be92d2f9aba
Steve Reinhardt [Sat, 2 Sep 2006 15:20:54 +0000 (08:20 -0700)]
regress:
Clean up help output.
util/regress:
Clean up help output.
--HG--
extra : convert_revision :
8375d58a9d72e1871a15690991dc8fc60d47a2b3
Steve Reinhardt [Sat, 2 Sep 2006 00:12:43 +0000 (17:12 -0700)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into vm1.(none):/home/stever/bk/newmem-head
--HG--
extra : convert_revision :
8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
Steve Reinhardt [Sat, 2 Sep 2006 00:11:50 +0000 (20:11 -0400)]
Get rid of extra stuff in util/regress only needed by cron job,
to make it more usable by regular folks.
util/regress:
Get rid of extra stuff only needed by cron job,
to make it more usable by regular folks.
--HG--
extra : convert_revision :
e113c05af5eec846db526d734cce8ff66aa95d72
Steve Reinhardt [Fri, 1 Sep 2006 21:59:36 +0000 (17:59 -0400)]
Add o3-timing configuration for ALPHA_SE "Hello world" tests.
build_opts/ALPHA_SE:
Add O3CPU to default CPU model list.
tests/SConscript:
Add o3-timing configuration.
--HG--
extra : convert_revision :
378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
Steve Reinhardt [Fri, 1 Sep 2006 20:27:24 +0000 (16:27 -0400)]
diff-out:
Don't consider it a success if no stats at all were found.
tests/diff-out:
Don't consider it a success if no stats at all were found.
--HG--
extra : convert_revision :
733f10abdf17d1f7eeca912f84f3df37e56fe510
Steve Reinhardt [Fri, 1 Sep 2006 16:59:48 +0000 (12:59 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
54c63c9a8c7146bb45ecfa9a177ab0bda9541d1b
Steve Reinhardt [Fri, 1 Sep 2006 00:58:46 +0000 (17:58 -0700)]
Tweak proxy resolution error message.
--HG--
extra : convert_revision :
3b186209515975be0d8bc9acc214425adcaa16f2
Korey Sewell [Fri, 1 Sep 2006 00:51:30 +0000 (20:51 -0400)]
add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA
--HG--
extra : convert_revision :
24c7460d9391e8d443c9fe08e17c331ae8e9c36a
Steve Reinhardt [Wed, 30 Aug 2006 23:24:26 +0000 (16:24 -0700)]
Move more common functionality into SimpleTimingPort,
allowing derived classes to be simplified.
--HG--
extra : convert_revision :
c980d3aec5e6c044d8f41e96252726fe9a256605
Gabe Black [Wed, 30 Aug 2006 23:08:24 +0000 (19:08 -0400)]
Change the cpu pointer in the InstRecord object to a thread context pointer.
--HG--
extra : convert_revision :
7efb2680cef4219281b94d680a4a7c75c123f89d
Gabe Black [Wed, 30 Aug 2006 22:33:47 +0000 (18:33 -0400)]
Forgot some commas
--HG--
extra : convert_revision :
d178c87ba156be6302f871f1ab1030889586168f
Steve Reinhardt [Wed, 30 Aug 2006 16:57:46 +0000 (09:57 -0700)]
Minor include file & formatting cleanup.
--HG--
extra : convert_revision :
fa23563b2897687752379d63ddab5cccb92484ba
Steve Reinhardt [Tue, 29 Aug 2006 21:36:35 +0000 (14:36 -0700)]
Add FULL_SYSTEM check to example/fs.py.
--HG--
extra : convert_revision :
4cab46e73f29d2c9d24d9c0c847d598bf6d5c389
Steve Reinhardt [Tue, 29 Aug 2006 21:14:29 +0000 (14:14 -0700)]
Add missing cpu mem param to example/se.py.
configs/example/se.py:
Add missing cpu mem param.
--HG--
extra : convert_revision :
29a11b09524612f079b8998e99b8f5ee8c67c8a6