whitequark [Sat, 3 Aug 2019 15:31:00 +0000 (15:31 +0000)]
hdl.ir: raise DomainError if a domain is used but not defined.
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
whitequark [Sat, 3 Aug 2019 14:54:20 +0000 (14:54 +0000)]
hdl.ir: call back from Fragment.prepare if a clock domain is missing.
See #57.
whitequark [Sat, 3 Aug 2019 14:00:29 +0000 (14:00 +0000)]
hdl.dsl: warn on suspicious statements like `m.If(~True):`.
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.
Fixes #159.
whitequark [Sat, 3 Aug 2019 13:44:44 +0000 (13:44 +0000)]
Improve test added in
29fee01f to not leak warnings.
whitequark [Sat, 3 Aug 2019 13:27:47 +0000 (13:27 +0000)]
back.rtlil: fix sim-synth mismatch with assigns following switches.
Closes #155.
whitequark [Sat, 3 Aug 2019 13:21:09 +0000 (13:21 +0000)]
hdl.ast: fix typo.
whitequark [Sat, 3 Aug 2019 13:05:41 +0000 (13:05 +0000)]
hdl.ast: deprecate Value.part, add Value.{bit,word}_select.
Fixes #148.
whitequark [Sat, 3 Aug 2019 12:44:52 +0000 (12:44 +0000)]
hdl.ast, back.rtlil: add source locations to anonymous wires.
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.
Also fixes incorrect source location on value.part().
whitequark [Sat, 3 Aug 2019 12:30:39 +0000 (12:30 +0000)]
hdl.ir: warn if .elaborate() returns None.
Fixes #164.
whitequark [Wed, 31 Jul 2019 05:19:24 +0000 (05:19 +0000)]
hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.
Fixes #154.
N. Engelhardt [Sun, 21 Jul 2019 07:49:21 +0000 (15:49 +0800)]
vendor: don't emit duplicate iobuf submodule names.
These are no longer allowed after commit
698b005.
N. Engelhardt [Fri, 19 Jul 2019 12:39:47 +0000 (20:39 +0800)]
hdl.dsl: add getters to m.submodules.
Alain Péteut [Sun, 14 Jul 2019 22:28:06 +0000 (00:28 +0200)]
lib.fifo: fix typo.
Staf Verhaegen [Sun, 14 Jul 2019 19:15:09 +0000 (21:15 +0200)]
Pin: Add extra hierarchy level for name derivation
William D. Jones [Sun, 14 Jul 2019 17:28:19 +0000 (13:28 -0400)]
build.run: Ensure batch script returns proper error code.
whitequark [Fri, 12 Jul 2019 12:17:18 +0000 (12:17 +0000)]
back.pysim: correctly add gtkwave traces for signals with decoders.
William D. Jones [Wed, 10 Jul 2019 15:29:09 +0000 (11:29 -0400)]
build.dsl: Add optional name_suffix to Resource.family.
whitequark [Wed, 10 Jul 2019 12:54:59 +0000 (12:54 +0000)]
back.pysim: avoid malformed VCD files when a decoder uses tabs.
whitequark [Wed, 10 Jul 2019 12:46:46 +0000 (12:46 +0000)]
hdl.ir: make UnusedElaboratable a real warning.
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
whitequark [Tue, 9 Jul 2019 19:45:15 +0000 (19:45 +0000)]
back.rtlil: add decodings to cases when switching on a signal.
Fixes #134.
whitequark [Tue, 9 Jul 2019 19:28:09 +0000 (19:28 +0000)]
back.verilog: run proc_prune for much cleaner output.
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@
44bcb7a1.
whitequark [Tue, 9 Jul 2019 19:18:02 +0000 (19:18 +0000)]
hdl.{ast,dsl},back.rtlil: track source locations for switch cases.
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@
93bc5aff.
Jacob Lifshay [Tue, 9 Jul 2019 07:29:01 +0000 (00:29 -0700)]
tracer: add PyPy support to get_var_name().
Fixes #141.
whitequark [Tue, 9 Jul 2019 02:44:03 +0000 (02:44 +0000)]
build.dsl: add Resource.family abstraction.
whitequark [Mon, 8 Jul 2019 11:15:04 +0000 (11:15 +0000)]
build.{dsl,res}: allow platform-dependent attributes using callables.
Fixes #132.
whitequark [Mon, 8 Jul 2019 10:59:15 +0000 (10:59 +0000)]
hdl.rec: respect modifications to signals in Record.like().
Fixes #126.
whitequark [Mon, 8 Jul 2019 10:48:07 +0000 (10:48 +0000)]
back.rtlil: don't name-prefix signals connected to instance ports.
This gives particularly pathological results on IO buffers, like:
connect \D_OUT_0 \user_led_0_user_led_0__o
Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
whitequark [Mon, 8 Jul 2019 10:41:45 +0000 (10:41 +0000)]
build.{dsl,res}: allow removing attributes from subsignals.
This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.
Fixes #128.
whitequark [Mon, 8 Jul 2019 10:32:41 +0000 (10:32 +0000)]
build.dsl: allow assertions on subsignal widths.
This is useful when building abstractions around resources where
the pin names are user-specified.
Fixes #129.
whitequark [Mon, 8 Jul 2019 10:26:49 +0000 (10:26 +0000)]
hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain.
Fixes #125.
whitequark [Mon, 8 Jul 2019 10:20:24 +0000 (10:20 +0000)]
test: fix Travis.
whitequark [Mon, 8 Jul 2019 10:12:15 +0000 (10:12 +0000)]
test: generate examples to verilog as part of unit tests.
This is to make sure
806a62c2 doesn't happen again.
whitequark [Mon, 8 Jul 2019 10:00:16 +0000 (10:00 +0000)]
examples/basic/ctr_ce: fix outdated syntax.
whitequark [Mon, 8 Jul 2019 10:03:20 +0000 (10:03 +0000)]
compat.genlib.fsm: fix after commit
dac62754.
whitequark [Mon, 8 Jul 2019 09:57:14 +0000 (09:57 +0000)]
hdl.xfrm: don't overwrite source locations on ClockDomain signals.
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
whitequark [Mon, 8 Jul 2019 09:50:07 +0000 (09:50 +0000)]
hdl.{dsl,mem,xfrm}: inject appropriate source locations.
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.
On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
whitequark [Mon, 8 Jul 2019 09:33:01 +0000 (09:33 +0000)]
back.rtlil: ignore empty source locations.
This was a bug introduced during refactoring in
2492f490.
whitequark [Mon, 8 Jul 2019 09:23:33 +0000 (09:23 +0000)]
hdl.ast: use keyword-only arguments as appropriate.
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
whitequark [Mon, 8 Jul 2019 09:09:40 +0000 (09:09 +0000)]
back.rtlil: attach source locations to switches, not processes.
This effectively reverts and reimplements half of commit
82903e49.
I was confused and did not realize that RTLIL does, in fact, have
attributes on switches.
After this commit, processes no longer have any source locations.
This is semantically fine, as the processes we emit are purely
artificial (because of LHS grouping), but I have not checked how
downstream tooling handles this.
whitequark [Mon, 8 Jul 2019 08:57:36 +0000 (08:57 +0000)]
back.rtlil: use a more principled approach to attributes. NFC.
This also refactors the RTLIL builder to use a more aspect-oriented
approach.
Alain Péteut [Sun, 7 Jul 2019 21:36:32 +0000 (23:36 +0200)]
vendor.xilinx_7series: generate also binary bitfile.
Fixes #139.
William D. Jones [Sun, 7 Jul 2019 20:44:48 +0000 (16:44 -0400)]
vendor.xilinx_spartan_3_6: Add Spartan3A family support.
whitequark [Sun, 7 Jul 2019 02:30:56 +0000 (02:30 +0000)]
vendor.lattice_ecp5: don't leave LUT inputs disconnected.
This causes YosysHQ/nextpnr#301.
Fixes #136.
whitequark [Sun, 7 Jul 2019 01:03:59 +0000 (01:03 +0000)]
hdl.dsl: further clarify error message for incorrect nesting.
Fixes #133.
whitequark [Sun, 7 Jul 2019 00:59:57 +0000 (00:59 +0000)]
hdl.dsl: clarify error message for incorrect nesting.
Refs #133.
whitequark [Sun, 7 Jul 2019 00:59:34 +0000 (00:59 +0000)]
hdl.dsl: gracefully handle FSM with no states.
whitequark [Sun, 7 Jul 2019 00:41:03 +0000 (00:41 +0000)]
build.plat: source a script with toolchain environment.
Fixes #131.
whitequark [Sun, 7 Jul 2019 00:18:56 +0000 (00:18 +0000)]
build.run: only use os.path on the target OS.
Before this commit, BuildPlan.add_file would use os.path.normpath,
which would be the wrong thing for cross-builds.
whitequark [Sun, 7 Jul 2019 00:07:55 +0000 (00:07 +0000)]
build.run: make BuildProducts abstract, add LocalBuildProducts.
This makes it clear that we plan to have remote builds as well.
Also, document everything in build.run.
whitequark [Sat, 6 Jul 2019 23:09:46 +0000 (23:09 +0000)]
build.plat, vendor.*: don't join strings passed as _opts overrides.
Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.
Fixes #130.
whitequark [Sat, 6 Jul 2019 18:44:25 +0000 (18:44 +0000)]
build.run: make sure BuildProducts._root is not easily accessible.
Staf Verhaegen [Thu, 4 Jul 2019 15:13:56 +0000 (17:13 +0200)]
vendor.xilinx_{7series,spartan6}: Support extra VHDL files.
whitequark [Wed, 3 Jul 2019 16:34:31 +0000 (16:34 +0000)]
hdl.dsl: fix src_loc_at for FSM state signal.
whitequark [Wed, 3 Jul 2019 16:27:54 +0000 (16:27 +0000)]
back.rtlil: emit \src attributes for processes via Switch and Assign.
The locations are unfortunately not very precise, but they provide
some improvement over status quo.
whitequark [Wed, 3 Jul 2019 15:25:14 +0000 (15:25 +0000)]
hdl.ast: fix src_loc_at for Mux().
whitequark [Wed, 3 Jul 2019 15:07:44 +0000 (15:07 +0000)]
build.res: detect physical conflicts earlier.
This is useful for two reasons:
1. nMigen can provide better error messages than the platform and
do it earlier in the build pipeline.
2. Many platforms handle diffpairs by only constraining the P pin;
the N pin is completely ignored. If this is undetected,
downstream users (human or software) can rely on this
information assuming it is correct and introduce more errors.
(Of course, this will not catch every mistake, but the most
common is a copy-paste issue, and that will handle it.)
Fixes #124.
whitequark [Wed, 3 Jul 2019 14:49:20 +0000 (14:49 +0000)]
hdl.rec: thread src_loc_at to all inner Signals and Records.
whitequark [Wed, 3 Jul 2019 14:43:03 +0000 (14:43 +0000)]
vendor: give names to IO buffer instances.
Fixes #123.
whitequark [Wed, 3 Jul 2019 14:35:48 +0000 (14:35 +0000)]
hdl.rec: accept Record(src_loc_at=...).
whitequark [Wed, 3 Jul 2019 13:28:57 +0000 (13:28 +0000)]
compat.fhdl.specials: mark CompatMemory as Elaboratable.
This suppresses a warning that is not useful in the compat context.
whitequark [Wed, 3 Jul 2019 13:25:12 +0000 (13:25 +0000)]
compat.fhdl.specials: use "sync" as default domain, not "sys".
In compat.fhdl.module, we already default to "sync" as the default
clocked domain. Using "sys" in memories only would be inconsistent
and result in more bugs.
whitequark [Wed, 3 Jul 2019 13:24:00 +0000 (13:24 +0000)]
compat.fhdl.specials: fix Memory.get_port() after
94e8f479.
This also makes sure the native ports are instantiated for correct
clock domain.
whitequark [Wed, 3 Jul 2019 13:19:15 +0000 (13:19 +0000)]
compat.fhdl.structure: fix If/Elif/Else after
32446831.
Sebastien Bourdeauducq [Wed, 3 Jul 2019 02:25:32 +0000 (10:25 +0800)]
lattice_ecp5: fix get_input
whitequark [Tue, 2 Jul 2019 19:02:16 +0000 (19:02 +0000)]
hdl.ast: recognize a Enum used as decoder and format it better.
whitequark [Tue, 2 Jul 2019 18:37:02 +0000 (18:37 +0000)]
hdl.mem: fix naming of registers inside unnamed memories.
Before this commit, `None` would leak into the vcd file with pysim.
Alain Péteut [Tue, 2 Jul 2019 08:44:12 +0000 (10:44 +0200)]
build.plat: add iter_extra_files method.
* vendor.*: employ iter_extra_files.
whitequark [Tue, 2 Jul 2019 18:06:50 +0000 (18:06 +0000)]
back.rtlil: emit \sig$next wires instead of \$next\sig. NFC.
Just a bit more readable.
whitequark [Tue, 2 Jul 2019 18:05:34 +0000 (18:05 +0000)]
back.rtlil: do not emit $next wires for comb signals.
According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.
This change results in major improvements in Verilog readability.
See also #98.
whitequark [Tue, 2 Jul 2019 17:44:55 +0000 (17:44 +0000)]
hdl.rec: implement slicing by component names.
Fixes #121.
whitequark [Tue, 2 Jul 2019 17:35:00 +0000 (17:35 +0000)]
hdl.rec: implement Record.like.
Fixes #120.
Alain Péteut [Tue, 2 Jul 2019 07:47:40 +0000 (09:47 +0200)]
vendor.xilinx_7series: read extra .xdc files.
whitequark [Mon, 1 Jul 2019 19:56:49 +0000 (19:56 +0000)]
hdl.mem: use read_port(domain="comb") for asynchronous read ports.
This avoids the absurdity of the combination of arguments that is
read_port(domain="sync", synchronous=True).
Fixes #116.
whitequark [Mon, 1 Jul 2019 01:53:56 +0000 (01:53 +0000)]
back.rtlil: fix Array regression in
32446831.
Fixes #117.
whitequark [Fri, 28 Jun 2019 08:34:02 +0000 (08:34 +0000)]
back.pysim: create unique ResetSynchronizer internal domains.
Commit
300d47ca introduced the same bug commit
779f3ee9 was trying to
avoid, but now only in the simulator. Since the names in simulator
don't have to make any sense, just use DUID to generate them.
whitequark [Fri, 28 Jun 2019 07:49:14 +0000 (07:49 +0000)]
back.pysim: override ResetSynchronizer implementation.
This was rewritten to use Yosys cells in
779f3ee9 to avoid leaking
the interior clock domain, but the simulator doesn't understand Yosys
cells. So, use the old implementation in the simulator.
whitequark [Fri, 28 Jun 2019 07:34:10 +0000 (07:34 +0000)]
lib.cdc: avoid interior clock domains in ResetSynchronizer.
Such clock domains will "leak" into the enclosing scope, which is
generally undesirable. Also, this is instructive for a platform
overriding the behavior, since it provides guidance on how to
correctly instantiate platform-specific flops.
I've considered also doing this for MultiReg(), but it is very
challenging in presence of non-reset-less CDC FFs, since Yosys'
$dffsr primitive has separate set and clear inputs, and reshuffling
the reset value for those results in quite a bit of additional logic.
(That said, it might have to be done anyway, precisely because
letting Yosys generate this additional logic might prove too much
for the toolchain to cope with, and again, platform-independent
code should provide guidance to platform-specific code.)
whitequark [Fri, 28 Jun 2019 07:22:54 +0000 (07:22 +0000)]
lib.cdc: eliminate no_retiming attributes.
See #115 for rationale.
whitequark [Fri, 28 Jun 2019 07:05:10 +0000 (07:05 +0000)]
vendor.lattice_ice40: fix instance of negedge FF due to a typo.
Alain Péteut [Thu, 27 Jun 2019 18:56:37 +0000 (20:56 +0200)]
build.plat: fix dedent overrides.
whitequark [Fri, 28 Jun 2019 05:10:29 +0000 (05:10 +0000)]
README: tone down the instability warning to reflect current status.
whitequark [Fri, 28 Jun 2019 04:37:08 +0000 (04:37 +0000)]
hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.
This means that instead of:
with m.Case(0b00):
<body>
with m.Case(0b01):
<body>
it is legal to write:
with m.Case(0b00, 0b01):
<body>
with no change in semantics, and slightly nicer RTLIL or Verilog
output.
Fixes #103.
whitequark [Fri, 28 Jun 2019 04:14:38 +0000 (04:14 +0000)]
hdl.ir, back.rtlil: allow specifying attributes on instances.
Fixes #107.
whitequark [Thu, 27 Jun 2019 04:51:45 +0000 (04:51 +0000)]
examples: add concise UART example.
This example uses shift registers and counters instead of an explicit
FSM, which makes it very compact in terms of generated logic, and
more concise too.
whitequark [Wed, 26 Jun 2019 05:22:09 +0000 (05:22 +0000)]
back.pysim: fix scope screwup.
whitequark [Tue, 25 Jun 2019 21:53:08 +0000 (21:53 +0000)]
compat.fhdl.structure: fix typo.
whitequark [Tue, 25 Jun 2019 21:52:03 +0000 (21:52 +0000)]
compat.fhdl.structure: simplify handling of default case.
whitequark [Tue, 25 Jun 2019 17:53:09 +0000 (17:53 +0000)]
hdl.{ast,dst}: directly represent RTLIL default case.
This makes RTLIL mildly nicer:
casez ({ \$5 , \$3 , \$1 })
3'bzz1:
\$next\o = \$7 ;
3'bz1z:
\$next\o = \$9 ;
3'b1zz:
\$next\o = \$11 ;
- 3'bz:
+ default:
{ \$next\co , \$next\o } = \$13 ;
endcase
whitequark [Tue, 25 Jun 2019 15:51:52 +0000 (15:51 +0000)]
vendor.xilinx_{spartan6,7series}: speedgrade→speed.
For consistency with ECP5.
whitequark [Tue, 25 Jun 2019 15:47:53 +0000 (15:47 +0000)]
vendor.lattice_ecp5: implement.
Note that because of issues with Yosys and nextpnr, it is not yet
possible to use either SDR or DDR I/O.
Sebastien Bourdeauducq [Mon, 24 Jun 2019 02:05:25 +0000 (10:05 +0800)]
README: update nMigen libs paragraph
Sebastien Bourdeauducq [Mon, 24 Jun 2019 02:00:31 +0000 (10:00 +0800)]
README: add clarification about HLS
whitequark [Wed, 19 Jun 2019 06:09:08 +0000 (06:09 +0000)]
vendor.lattice_ice40: use different --package for 4k devices.
Jean-François Nguyen [Mon, 17 Jun 2019 18:01:26 +0000 (20:01 +0200)]
vendor.xilinx_7series: fix IOB packing.
whitequark [Sat, 15 Jun 2019 16:07:40 +0000 (16:07 +0000)]
vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly.
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
whitequark [Sat, 15 Jun 2019 16:01:37 +0000 (16:01 +0000)]
vendor.xilinx_{7series,spartan6}: cleanup. NFC.
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
whitequark [Sat, 15 Jun 2019 15:55:10 +0000 (15:55 +0000)]
vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly.
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
Alain Péteut [Sun, 16 Jun 2019 12:06:39 +0000 (14:06 +0200)]
build.plat: dedent overrides.
whitequark [Fri, 14 Jun 2019 20:44:02 +0000 (20:44 +0000)]
vendor.lattice_ice40: never place an inverter on global buffer output.
This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.
Jean-François Nguyen [Thu, 13 Jun 2019 12:33:24 +0000 (14:33 +0200)]
vendor.xilinx_7series: implement inverters.