arch,cpu,sim: Route system calls through the workload.

System calls should now be requested from the workload directly and not
routed through ExecContext or ThreadContext interfaces. That removes a
major special case for SE mode from those interfaces.

For now, when the SE workload gets a request for a system call, it
dispatches it to the appropriate Process object. In the future, the
ISA specific Workload subclasses will be responsible for handling system
calls and not the Process classes.

For simplicity, the Workload syscall() method is defined in the base
class but will panic everywhere except when SEWorkload overrides it. In
the future, this mechanism will turn into a way to request generic
services from the workload which are not necessarily system calls. For
instance, it could be a way to request handling of a page fault without
having to have another PseudoInst just for that purpose.

Change-Id: I18d36d64c54adf4f4f17a62e7e006ff2fc0b22f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33282
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Create a Workload object for SE mode.

The workload object is still optional for the sake of compatibility,
even though it probably shouldn't be in the long term. If a simulation
is just a collection of components with nothing in particular running on
it, for instance driven by a traffic generator, should it even have a
System object in the first place?

Change-Id: I8bcda72bdfa3730248226fb62f0bba9a83243d95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33278
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Stop using the OS page size in the IDE controller.

This size was used to break up DMA transactions so that a single
transaction would not cross a page boundary. This was because on Alpha,
there was an actual page table which translated between PCI and DMA
address spaces. On all currently implemented systems, the mapping is
simply to add a scalar offset, so it's not possible for a legal region
of memory to be contiguous in one space but not in the other.

Additionally, if it *was* possible for there to be a mismatch, it was
only coincidence that Alpha used a page table which had the same sized
pages as it normally used. There is no requirement that there even would
be fixed sized pages in the first place.

To avoid this artificial dependency between the IDE controller and the
ISA, this change simply changes the chunk size for DMA accesses to 4K.
That's the page size at least on x86 and probably other architectures,
and will be a pretty close approximation of the previous behavior.

It's possible that even having this chunking in the first place is
unnecessary and functionally useless, but there are some checks which
happen between chunks, and changing how big they are would change the
frequency of those checks. For instance, the controller/disk may not
notice in the same amount of time if a DMA was cancelled somehow.

Change-Id: I1ec840d1f158c3faa31ba0184458b69bf654c252
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34178
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Increase the minimum clang version to 3.9.

This matches what's documented elsewhere. We *need* version 3.4 to
support c++14, but we support only as far back as 3.9. Also, the
argument to set c++14 as the standard is different in 3.4 and earlier
(-std=c++1y), so it makes life slightly easier to move past it to 3.9.

Change-Id: I66fa578dd3222c62907496a888f8068ed0918c7b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34819
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Use M5_UNLIKELY with conditional DPRINTF family functions.

Most DPRINTFs will be skipped over most of the time, and when they
aren't they'll already have overhead from string handling, output to the
console and/or a file, etc, which will drown out the behavior of a
branch.

Change-Id: I5475d7b5add63b44f60c0a1d46b4b14e6bf30fd3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34818
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Use M5_UNLIKELY for conditional panic, etc., macros.

panic_if and fail_if should happen at most once in any given simulation,
and warn_if, etc., should still not happen most of the time.

Change-Id: Iaa6cb03c11b86d84f51cc4738efb8f203de4201c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34817
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add M5_LIKELY and M5_UNLIKELY macros to compiler.hh.

The clang/gcc implementation uses the nonstandard __builtin_expect(). In
C++20, new standard attributes can be used instead. We can't use those
yet though.

Change-Id: Idd2541a7eca0d97ac6c643abbf2910cbc343d7e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34816
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Clear out some unnecessary ISA dependence in thread_context.hh.

The ISA version of the ISA class isn't used any more. Neither is
TheISA::MachInst.

Change-Id: I9085ad2b51ba19bf6e5bb17769dd048ac6384fec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34821
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu: Stop using TheISA in the GPU TLB.

This class is defined inside the X86ISA namespace, so there's no point
in pretending it's generic. Remove TheISA and let the code access what
it needs from X86ISA naturally since it's there already.

Change-Id: I21b5d2d2b9af6aa0c10ddbb5b3ddca1692188dcc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34173
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>

tests: cleanup all SE tests previously moved to gem5-resources

The move was done at:
https://gem5-review.googlesource.com/c/public/gem5-resources/+/32074

All files keep exact same name, or are obvious renames like underscore to
-. threads/ is the only non obvious and remaps to src/simple/std_thread.cpp

Only m5-exit is left because it does squashfs generation which wasn't yet
moved.

Change-Id: I72ad104c9311c2f81af49458bdd44e24a6bafc0a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34476
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Add a missing override.

A recent change accidentally left off the override, upsetting gcc.

Change-Id: I78cf1969aa6ac462539a2793a8a91dea32002f3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34756
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: Fix deadlock in fetch_unit after branch instruction

The following deadlock was occuring in fetch_unit w/timingSim:
1. exec() is called, a wave is ready to fetch, so it sets pendingFetch
2. A packet is sent to ITLB to fetch for that wave
3. The wave executes a branch, causing the fetch buffer to be cleared
4. The packet is handled, and fetch() is called. However, because the
fetch buffer was cleared, it returns doing nothing.
5. exec() gets called again, but the wave will never be scheduled to
fetch, as pendingFetch is still set to true.

This patch clears pendingFetch (and dropFetch) before returning in fetch()
when the fetch buffer has been cleared.

dropFetch needed to be cleared otherwise gem5 would crash.

Change-Id: Iccbac7defc4849c19e8b17aa2492da641defb772
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34555
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add an unmap_m5_mem() function to the m5 util's m5_mmap.*.

This cleans up the mmap-ing. This is primarily used for testing since
the tests may end up mmap-ing the backing file many times, and we don't
want all those earlier mappings lying around.

This change also makes the original mmap-ing function close the file it
opens, since the man page for mmap explicitly says you can do that and
not lose the mapping. That means we don't have to keep track of the file
descriptor which corresponds to the mmap-ed file when we do the
unmapping, and it's slightly cleaner in general.

Change-Id: I90e3e755cebf3d03e2bf644adf8ef3e157236172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27750
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a "semi" call type unit test to the m5 utility.

This is largely similar to the "inst" call type test since it's also
another form of illegal instruction, but there's more checking to do
since the way arguments are passed is more complex.

Change-Id: Ie61bb4da8befab579c3044fd2ddee753926de174
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27749
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: self-manage TimeSlot in Scheduler

TimeSlot is new and deleted frequently. Having a recycling memory
manager can help saving the time spent new and delete. Tested and see
about 4% improvement in simulation speed.

Change-Id: I0ab173168336a883b85f768d7fdf07a936a14d69
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34615
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: use list instead of map in scheduler

The queue in systemC scheduler is implemented as a std::map. This provides
the best big-O solution. However, most of simulation usecases has very
small number of pending events. This is expected as we usually only trigger a
few new events after some events are processed. In such scenario, we
should optimize for insert/erase instead of search. This change use
std::list instead of std::map.

As a proof, we can find that gem5's original event_queue is also
implemented as a list instead of tree.

We see 5% speed improvement with the example provided by Matthias Jung:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840

Change-Id: I75c30df9134e94df42fd778115cf923488ff5886
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Merge branch 'release-staging-v20.1.0.0' into develop

Change-Id: I8c3277af7903f0b055b26e497139455a03678524

misc: Add Matt Poremba as GPU maintainer

Change-Id: I90494955b6db628695ef8a42111977decba27618
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34655
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add special case in MemConfig

SimpleMemory doesn't implement a full MemCtrl interface. Thus, like the
NVM and HMC memories, we need to add a special case to MemConfig.py. The
--mem-type command line option now works for SimpleMemory and all of the
DRAM interfaces (it does not work for the NVM interfaces, though).

Issue-on: https://gem5.atlassian.net/browse/GEM5-777

Change-Id: I6d60649215be324bdd2a104b1976752f936c960e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34595
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu: Get rid of the IsMemRef StaticInst flag.

A comment at the top of StaticInstFlags.py says that if IsMemRef is set,
exactly one of IsStore or IsLoad will be set. That's not strictly true
since IsAtomic may be set as well, in which case neither IsStore or
IsLoad will be set (in one example I found).

The isMemRef accessor still exists, and now just ors the IsStore,
IsLoad, and IsAtomic flags.

Change-Id: Ic5ff104da68978273977a6eff2abab5dd0ae7fda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33744
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Create a SConscript for the loader subdirectory.

These files had been handled in base/SConscript, but there are enough of
them that they deserve their own.

Change-Id: I0c4166d8ff3c761c25940d2af5d7f0a9a6c874fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33898
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch,cpu: Rearrange StaticInst flags for memory barriers.

There were three different StaticInst flags for memory barriers,
IsMemBarrier, IsReadBarrier, and IsWriteBarrier. IsReadBarrier was never
used, and IsMemBarrier was for both loads and stores, so a composite of
IsReadBarrier and IsWriteBarrier.

This change gets rid of IsMemBarrier and replaces by setting
IsReadBarrier and IsWriteBarrier at the same time. An isMemBarrier
accessor is left, but is now implemented by checking if both of the
other flags are set, and renamed to isFullMemBarrier to make it clear
that it's checking both for both types of barrier, not one or the other.

Change-Id: I702633a047f4777be4b180b42d62438ca69f52ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33743
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: use setjmp to speed up fiber

ucontext is an order of magnitude slower compared to most of the fiber
implementation, mainly due to the additional signal mask operation.

This change applies the trick provided in
http://www.1024cores.net/home/lock-free-algorithms/tricks/fibers,
which uses _setjmp/_longjmp to switch between contexts created by
ucontext.

Combine with NodeList improvement, we see 81% speed improvement with the
example provided by Matthias Jung:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840

Compared with Accellera's SystemC, gem5 SystemC was originally 10x
slower, and with this change it's about 1.8x.

Change-Id: I0ffb6978e83dc8be049b750dc1baebb3d251601c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34356
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Remove conditional includes based on THE_ISA in ruby.

These were including instruction class definitions from x86 for some
reason. There was no code in those .cc files which actually used
anything from them, as evidenced by the fact that the GCN3_X86 build
still works. No other code in the file was conditionally compiled as of
today.

Change-Id: I3cef8348fb601dd7af67665cf64bbf514c91c3db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34577
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu: Fix a syntax error in X86GPUTLB.py.

The recent changes which removed master/slave terminology also
accidentally deleted an "=", making the syntax in that file illegal.

Change-Id: I50aa945f0f66765db36775380b98a88caff23c13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34576
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Use zero initialization for the BigRegVect types.

These were being initialized with BigRegVect brv = {0}, which made the
compiler complain because there is internal structure. The first element
of the union is actually an array, and this was telling it to initialize
that array to scalar 0. It was warning about this which was breaking the
build.

Instead, use zero initlization like BigRegVect brv = {}. This
initializes the first element of the union to all zeroes, with all
padding bits initialized to zero as well.

This satisfies the compiler and avoids a build error.

Change-Id: I31e7a8730c538637ff2e0c7fb00a4e12ed05e074
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34575
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mips,cpu: Eliminate the unused IsIndexed StaticInst flag.

It's set by some MIPS instructions, but does not have an accessor in
StaticInst and is not used by anything.

Change-Id: I3466f7d2723fb1b0ac195064867e3840e3a8f21b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33735
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Remove #if THE_ISA in the AbstractMemory class.

This used to guard the extraction of the endianness when tracing memory
accesses. Since that's now always possible even in NULL_ISA, we don't
need conditional compilation.

Change-Id: Ie5ec76f5b0f27dd4123bc0f0a4c02438bed629ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34499
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Get rid of the unused IsMicroBranch StaticInst flag.

This flag was never set, nor read.

Change-Id: I74506c220d96b53dcd44740639286b1dbbe84d2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33742
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86,cpu: Get rid of the unused IsCC StaticInst flag.

This flag was set when some registers were used in x86, but never
actually checked by anything.

Change-Id: Id0f9847aeca5017455929ab4bbf28210288a3553
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33741
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mips,cpu: Get rid of the IsDpsOp StaticInst flag.

This flag was set by MIPS for a few instructions, but didn't have an
accessor in StaticInst and was never used for anything.

Change-Id: I153cedde0d16cb1d78b2705bd7340ebfd10e4fb6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33740
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Merge branch 'release-staging-v20.1.0.0' into develop

Change-Id: I1eacbc5719aa85c5a7650ec33fd99f673fdf443d

cpu,misc: Revert problematic terminology renames in BaseCPU

Due to gem5's use of duck-typing, we must termorarly revert the
terminology in BaseCPU back to master/slave to avoid issues.

This fixes https://gem5.atlassian.net/browse/GEM5-775.

Change-Id: Idf1cb99aa9568ee70943ebec96f27394d8167f8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34495
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: avoid dynamic_cast in the critical path

NodeList is in the critical path of the systemc scheduler in gem5. A
unnecessary dynamic_cast in the NodeList slow down the event process by
about 15%. Fix the issue by avoiding dynamic_cast.

We see about 15% speed improvement on the example provided by Matthias Jung:
https://gist.github.com/myzinsky/557200aa04556de44a317e0a10f51840

Compare with Accellera implementation, gem5 version is originally 10x
slower and now it's about 8.5x slower.

Change-Id: I3b4ddca31e58e1d4e96144a4021b0a5bb956fda4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34355
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips,cpu: Get rid of the IsIprAccess StaticInst flag.

This was set by MIPS in two places, I think largely just because it was
available. This flag refers to IPRs which are an Alpha concept. In the
O3 CPU, IsIprAccess was used as a possible indicator to determine if an
instruction IsSerializeBefore, but we've already got a flag for that. In
the minor CPU, which hasn't been made to work with MIPS as far as I
know, it was used in a condition but not mentioned in the comment
alongside the condition. I think there it was added for the sake of
Alpha.

This change eliminates that flag and removes it from the O3 and minor
CPUs. In the MIPS ISA description, the instructions that were marked as
IsIprAccess have now been marked as IsSerializeBefore since, if there
was a real reason for them to be marked as IsIprAccess, it would have
been to get it them to work in O3, and there IsSerializeBefore gets
equivalent behavior.

Change-Id: Ia874cde12fa70b998d3e638458f13d69798d40b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33739
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mips,cpu: Get rid of the IsERET StaticInst flag.

This is set by MIPS but doesn't have an accessor in StaticInst, and
isn't used by anything.

Change-Id: Ie28d2df134dcf264bca17c9c66dd32515a240492
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33738
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

cpu: Get rid of the IsThreadSync StaticInst flag.

This flag was never set and only checked in one place. If it was set, it
would have triggered a panic there.

Change-Id: I934a0346837c66bae8ce06f50027003bfd47083d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33737
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.

This is set by MIPS in a few places, but not actually used by anything.

Change-Id: Iaf3b29b2c14bb1de3ffd6a0035f12f238591cb60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33736
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

sparc,sim: Remove special handling of SPARC in the clone system call.

We can set the extra syscall return values in the ISA specific archClone
function. We don't need a special #ifdef to handle them.

Change-Id: I82904b3d4bdf211c89d271d7277a60151191cdfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34167
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

mem-ruby: Update port names in Ruby

After the terminology update commit there were still many confusing
names in the Ruby ports. This changeset is a proposal for updating these
names.

For an example use case, see the following resources changeset.
https://gem5-review.googlesource.com/c/public/gem5-resources/+/34416

Change-Id: I01d4f24a70b300e39438ee147dfab7a8d674d5c7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34417
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Remove MIPS from Learning gem5 tests

Change-Id: Iffd9f5da188cac26ac75a8109886c36789956959
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34415
Reviewed-by: mike upton <michaelupton@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Fix port name in x86 device

Change-Id: I7704109287b9a1a09e51da3c62c29720631ce87e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34435
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

stats: Move global CPU stats to BaseCPU

We currently register global CPU statistics such as sim_insts and
sim_ops from stat_control.cc. This adds an undesriable dependency on
BaseCPU from stats_contro.cc. Move the CPU-specific stats to a global
stat group in BaseCPU. This group is merged with the Root object's
stats which means that they appear as global stats in a typical stat
dump.

Care has been taken to keep the old stat names. However, the order of
the stats.txt will be slightly different due to the way legacy stats
and new-style stats are serialised.

Change-Id: I5410bc432f1a8cf3de58b08ca54a1aa2711d9c76
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34395
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base, sim, mem, arch: Remove the dummy CPU in NULL

The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.

Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix ArmISA namespace requirement for Arm KVM

This is needed after:

https://gem5-review.googlesource.com/c/public/gem5/+/34155

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I614b908a48145d8c2f5e8b8177448e3269f8dac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34418
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Update documentation of SimObject related APIs

Updated documentation of Drain, Serialize, Evnet queue and Simobject
APIs. Made some corrections to where the documentation was available
in the code but did not appear in the documentation.

Change-Id: I5254e87eb5663232e824bcd5592da0a04eba673b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31814
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Upgrade garnet version to 3.0

This version of garnet includes HeteroGarnet which
supports heterogenous interconnect systems, flexible
router and link configurations, and better debugging
resources.
This patch changes the garnet directory structure
to not include the version number. The user will be
informed about the garnet version being used.

Change-Id: Id4763421528305193ae0cd10c159b385a9513553
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34259
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Initialize some cases of destReg

Some compilers complained that this variable may be uninitialized. This
change initializes it to 0.

Change-Id: I201d75ba05ce49d13bbaf4d67e1c728ef704fdf0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34335
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: mike upton <michaelupton@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Update x86 system.py for MemCtrl interface

Change-Id: If4103b197720f74df70d0a24602e2b3715936826
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34315
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: mike upton <michaelupton@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Allow empty vnet list for garnet network links

An empty supporting_vnet list is the default and implies that
all vnets are supported. This removes the assert which requires
the list to have a minimum list size of 1.

Change-Id: I6710ba06041164bbd597d98e75374a26a1aa5655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34258
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Fix default value of network bridge

Initializing the network bridge with NULL causes it to have
an class error when instatiating a link. The bridge is only
needed whne either a CDC or SerDes is enabled. This is handled
later during construction of the GarnetLink.

Change-Id: If19a21a6d9bf49449b9c390467d08d3422ae991a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Replaced master/slave terminology

Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,python: Fixes an issue with python3 and the config scripts when restoring a checkpoint

Fixes a compatibility issue with the configuration scripts when trying to restore a checkpoint.  Since python2.4 list.sort has an updated interface.  The older one has been dropped in python3.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-754

Change-Id: I09f819057d510e477d6ceae0356fafad40f4280d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34295
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: cross-compiling hello binaries for hello_se tests.

Some of the hello_se tests fail due to different syntax of the string
for different isas. This patch adds makefiles for cross-compiling the
hello.c file located at tests/test-progs/hello/src/.

Change-Id: I8ccfc0487020df9da722a97e57310db2d2e8882c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28528
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fixed unused var error when with fast builds

As `is_htm_speculative` is only used in assert statements, it is
considered unused during the `.fast` compilation. This commit adds the
`M5_USED_VAR` macro.

This caused our compiler tests to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35913.html

Change-Id: I00d187d1a31d065c236ac29a657bd479ad4b03bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34256
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: just return the fault in twoEqualRegInst{,Fp}

This prevents the code from using the uninitialized destReg when
running the ``if (imm >= eCount)`` branch, which will make GCC 10.2
report a -Werror=maybe-uninitialized error when building gem5.opt.

Change-Id: Ie6e7d3d47a1b65b840b2106263ecfc21eb6af26b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34275
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix build errors with gcc 10.2

The "-Werror=type-limits" flag in GCC 10.2 reports these errors,
because ``imm`` in neon.isa, and ``imm`` and ``count`` in sve.isa are
unsigned, and they're used to do ``imm < 0`` and ``imm * count >= 0``
comparison.

Change-Id: I33934357f578a9fc1040a6d9c08ea929fb36eb47
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33154
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Use the new ByteOrder param type in VirtIO devices

VirtIO devices currently request their endianness from the System
object. Instead of explicitly querying the system for its endianness,
expose the device's endianness as a param. This param defaults to the
endianness of a parent object using the Parent proxy (in practice the
system).

Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33296
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

dev: Use the new ByteOrder param type in SimpleUart

Use the new ByteOrder param type in SimpleUart. The default value is
currently little endian. However, it is expected that most users of
this device will use single-byte accesses which aren't affected by
endianness.

Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33295
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Add an ISA class which defers to IRIS.

This class is just to enable checkpointing of "ISA" state, aka the
MiscRegs.

Change-Id: I45315b8aaa09aaf6230f44665c13597400efd780
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29822
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Create a fake "Interrupts" object for fast model CPUs.

This object doesn't actually manage interrupts since the fast model
CPUs do that on their own, it just checkpoints interrupt related state.

Change-Id: I9d3a6354b02e4ae7bfd032c50e51a3a841b81388
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29821
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips: Replaced `BigEndianByteOrder` in MIPS

The following change removed the `BigEndianByteOrder` enum and replaced
it with `ByteOrder:big`:
https://gem5-review.googlesource.com/c/public/gem5/+/33174

This change was not propogated to `src/arch/mips/isa/decoder.isa` and
`src/arch/mips/isa/formats/mem.isa`, and therefore caused compilation
errors. This caused the Nightly Build to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35900.html

This commit fixes this error.

Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34255
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix ArmISA namespace requirement for TME instructions

This is needed after:

https://gem5-review.googlesource.com/c/public/gem5/+/34155

Change-Id: I8ef0b5ce9cd5ae5224331e1c9347fdd9e884a536
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34235
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: convert rename to new style stats

Change-Id: Id34a85e40ad7e83d5805a034df6e0c5ad9b9af82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33397
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: convert rob to new style stats

Change-Id: I84430d50c49742cd536dd75ce25184c2316dce51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33398
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: convert lsq_unit to new style stats

Removes unused stats: invAddrLoads, invAddrSwpfs, lsqBlockedLoads

Change-Id: Icd7fc6d8a040f4a1f9b190409b7cdb0a57fd68cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33394
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: convert decode to new style stats

Change-Id: Ia67a51f3b2c2d40d8bf09f1636c721550f5e9a23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33316
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: convert commit to new style stats

Change-Id: I859fe753d1a2ec2da8a4209d1db122f1014af5d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33315
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Expose the system's byte order as a param

There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.

Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

mem: Remove the unused nvm private member from NVMInterface::Rank.

This unused (and otherwise unusable) member caused a compiler warning
and broke the build for me. It can be reintroduced if used in the
future.

Change-Id: I48181f6bca60c059e74727290950adfb9a194680
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34217
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix style and add overrides to bas_dyn_inst.hh.

Either return types, brackets and the function body should all be on
their own line, or the entire function should be on a single line.

Consistently place the * or & up against the variable name and not the
type name. There isn't an official rule for which to use, but the
majority of existing uses were this way.

Add overrides for overridden virtual methods.

These fixes get rid of compiler warnings which are breaking the build
for me.

Change-Id: Ifc6ace4794a66ffd031ee686f6b6ef888004d786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34216
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add a virtual destructor to BaseHTMCheckpoint.

Since it has virtual methods, it should also have a virtual destructor.
My compiler complains otherwise, which breaks my build.

Change-Id: I44bba97b76931bab6e3511fcdee79831080c12d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34215
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-minor: convert fetch2 to new style stats

Change-Id: Idfe0f1f256c93209fe51140b9cab3b454153c597
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33975
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.

This has been in this file since it was created in 2009. No global "using
namespace ${NAMESPACE}" should ever appear in a .hh file since then that
namespace is "used" in all files that include the .hh, even if they
aren't aware of it or even actively don't want to.

Change-Id: Idb7d7c5b959077eb4905fbb2044aa55959b8f37f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34155
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Transactional Memory Extension (TME)

This patch extends the generic hardware transactional memory support in
Ruby and the O3/TimingSimpleCPU cores with the Arm-specific hardware
transactional memory architectural extensions (TME).

JIRA: https://gem5.atlassian.net/browse/GEM5-588

Change-Id: I8c663da977ed3e8c94635fcb11834bd001e92054
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30329
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

base,misc: Add group definitions for newly tagged API in src/base

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: If2f5ce3bc4f5d0a8cc31def17702223a27e6970e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33034
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Check number of vnets when creating links

Added error checking to ensure that the system has sufficient virtual
networks when setting latency and weight values.

Change-Id: I1b28144bbe9fefab0c0a6227f1fdf4ea10403061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32603
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

dev,arm: Use the ArmSystem::PageBytes constant in the generic timer.

This component very specific to ARM, and so there's no reason to use
generic interfaces to get the page size.

Change-Id: Id757b5742c807c5f616a6dc8df94a7709932d071
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34171
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Replicate the PageBytes constant in the ArmSystem class.

When isa_traits.hh hopefully goes away in the not too distant future,
this constant will need somewhere to live so ARM components can find it.
There are valid arguments that this should not be a constant in the
first place, but that's outside the scope of this change.

Change-Id: Ic5bd046dc1cc196b3cf6b6c36878fdbf5eb4c0bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34170
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: convert trace cpu to new style stats

This required making minor changes to how the name was set for the
generators within the trace CPU to enable the stats to keep similar
names.

Change-Id: I9f97d4006a0edbd717fc34d0033b9548011d1631
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33875
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>

cpu-o3: convert elastic trace to new style stats

Change-Id: If767f17b905a77e12058022a9e8bc65b854978a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33399
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext,tests: Copy test's output files from /tmp to testing-results

When a test is complete, the output files are in a random folder
in /tmp.

This commit adds a procedure copying those files to
testing-results/SuiteUID/TestUID/ folder, where SuiteUID and
TestUID are the corresponding uid's of the test.

This procedure is triggered after a test is complete and before
the folder in /tmp being removed.

Change-Id: Id960e7f2f1629769008ae99aff4c8bfafa9ca849
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33998
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

ext: Add post_test_procedure to testlib runner

This procedure is trigger after a test has finished and before
the tearing down process kicks in.

Change-Id: I58ce10814fbc80d96f2f72565491b18de0ec290a
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33997
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

ext: Force testlib to only create one Log object

Log object should remain being a singleton throughout the program.
The current code creates multiple Log objects, which at least
causes the issues of missing outputs in stdout.

E.g., "Logging call to command", which logs which command is
being called in a subprocess, is missing from stdout.

Change-Id: I96c5dd79c4f14e0a013c15d42d202397488d56b6
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33715
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

cpu: convert memtest to new style stats

Change-Id: I91b17dd46fd0f70816159ea14c1c8f498048c696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34137
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Clean up Memory Controller

Make the actual controller more generic
    - Rename DRAMCtrl to MemCtrl
    - Rename DRAMacket to MemPacket
    - Rename dram_ctrl.cc to mem_ctrl.cc
    - Rename dram_ctrl.hh to mem_ctrl.hh
    - Create MemCtrl debug flag

Move the memory interface classes/functions to separate files
    - mem_interface.cc
    - mem_interface.hh

Change-Id: I1acba44c855776343e205e7733a7d8bbba92a82c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31654
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add NVM interface

Add NVM interface to memory controller.

This can be used with or instead of the existing
DRAM interface. Therefore, a single controller can interface
to either DRAM or NVM, or both.

Specifically, a memory channel can be configured as:
- Memory controller interfacing to DRAM only
- Memory controller interfacing to NVM only
- Memory controller interfacing to both DRAM and NVM

How data is placed or migrated between media types is outside
of the scope of this change.

The NVM interface incorporates new static delay parameters
for read and write completion. The interface defines a 2
stage read to manage non-deterministic read delays while
enabling deterministic data transfer, similar to NVDIMM-P.
The NVM interface also includes parameters to define
read and write buffers on the media side (on-DIMM). These are
utilized to quickly offload commands and write data, mitigating
the effects of lower latency and bandwidth media characteristics.

Change-Id: I6b22ddb495877f88d161f0bd74ade32cc8fdcbcc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29027
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

mem: Make MemCtrl a ClockedObject

Made DRAMCtrl a ClockedObject, with DRAMInterface
defined as an AbstractMemory. The address
ranges are now defined per interface. Currently
the model only includes a DRAMInterface but this
can be expanded for other media types.

The controller object includes a parameter to the
interface, which is setup when gem5 is configured.

Change-Id: I6a368b845d574a713c7196c5671188ca8c1dc5e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28968
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Factor out DRAM interface

Separate out the DRAM specific functions into a new class:
- DRAMInterface

Move the Rank class to DRAMInterface since rank functions are
specific to the media.

Move DRAMPacket and Bank class definitions outside of DRAMCtrl.

This is patch 1 within a set of patches that separate the
memory controller and media interface. These changes enable
future incorporation of new media interfaces into the model.

Change-Id: Ief632d73ec27176a61f16b4f642c10d56630f376
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28967
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Make the testing-results folder visible

Currently, testlib will write outputs to .testing-results, which
is a hidden folder. However, the outputs in the folder are useful
for debugging. This commit makes this folder visible on Linux
systems.

Change-Id: I158e1a4a62c7b494309a0a4bf6521fedd04cbe22
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34015
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Tag API methods in crc.hh

Change-Id: I4fc8977dad705a6774f649479184cdfb15aa2be5
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32961
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

base: Tag API methods to debug.hh

Change-Id: Ic4395f3594cbc156a2b678710a3ed4717ce87a81
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Tag API methods in inet.hh

Change-Id: Id53ab873c7de9de7ccb99ff8434827aeec676c30
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33254
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Tag API variables in date.cc

Change-Id: I5a90f6496ef1e39b6135a14dfdf3f5febd22ece2
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32974
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

base: Tag API methods in flags.hh

Change-Id: I12eb94b43e190ee46f82fba7d2a3ef6c29fdee80
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33035
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

base: Tag API variables in version.cc

Change-Id: I49438963a1cdb82b00fa6bea153d55b8cdbfcf33
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33079
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

base: Tag API methods in intmath.hh

Change-Id: Ia50830c7620380ff2aba081f56f74822aff982bf
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33075
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

base: Tag API methods in sat_counter.hh

Change-Id: Id5da647f35cca30276bb34b745999f4571a47d89
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33117
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

base: Tag API methods in condcodes.hh

Change-Id: Ife6b5ed6ee684b65790c374ab6e709ce8eb708ad
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33074
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Tag API methods to trace.hh

Change-Id: Ia2ad759b9bee4fd3413abd62cfa6b120616a14f9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33255
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>