Immanuel, Yehowshua U [Sun, 29 Mar 2020 16:09:08 +0000 (16:09 +0000)]
[libre-riscv-dev] BlueSpec Floating Point
Immanuel, Yehowshua U [Sun, 29 Mar 2020 16:05:37 +0000 (16:05 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Immanuel, Yehowshua U [Sun, 29 Mar 2020 16:03:51 +0000 (16:03 +0000)]
Re: [libre-riscv-dev] Building Docker Containers
Luke Kenneth Casson Leighton [Sun, 29 Mar 2020 15:26:25 +0000 (15:26 +0000)]
Re: [libre-riscv-dev] Building Docker Containers
bugzilla-daemon [Sun, 29 Mar 2020 14:50:32 +0000 (14:50 +0000)]
[libre-riscv-dev] [Bug 271] New: SigDecode in power_fields has extra spurious fields
Immanuel, Yehowshua U [Sun, 29 Mar 2020 13:48:27 +0000 (13:48 +0000)]
[libre-riscv-dev] Building Docker Containers
Luke Kenneth Casson Leighton [Sun, 29 Mar 2020 13:46:38 +0000 (13:46 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jock Tanner [Sun, 29 Mar 2020 13:23:10 +0000 (23:23 +1000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Sun, 29 Mar 2020 11:35:08 +0000 (11:35 +0000)]
Re: [libre-riscv-dev] GardenSnake.py
Luke Kenneth Casson Leighton [Sun, 29 Mar 2020 11:22:44 +0000 (11:22 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jock Tanner [Sun, 29 Mar 2020 10:46:06 +0000 (20:46 +1000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Sun, 29 Mar 2020 10:40:31 +0000 (10:40 +0000)]
[libre-riscv-dev] GardenSnake.py
Immanuel, Yehowshua U [Sun, 29 Mar 2020 03:15:03 +0000 (03:15 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Immanuel, Yehowshua U [Sun, 29 Mar 2020 03:14:18 +0000 (03:14 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
whygee [Sun, 29 Mar 2020 00:41:25 +0000 (01:41 +0100)]
Re: [libre-riscv-dev] another
CDC6600 reference on IEEE
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 23:16:52 +0000 (23:16 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 18:33:43 +0000 (18:33 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Michael Nolan [Sat, 28 Mar 2020 18:07:19 +0000 (14:07 -0400)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
bugzilla-daemon [Sat, 28 Mar 2020 17:35:22 +0000 (17:35 +0000)]
[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 17:14:23 +0000 (17:14 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 17:13:28 +0000 (17:13 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jean-Paul Chaput [Sat, 28 Mar 2020 16:44:48 +0000 (17:44 +0100)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
bugzilla-daemon [Sat, 28 Mar 2020 16:20:53 +0000 (16:20 +0000)]
[libre-riscv-dev] [Bug 270] investigate nmigen clock gating
bugzilla-daemon [Sat, 28 Mar 2020 14:34:31 +0000 (14:34 +0000)]
[libre-riscv-dev] [Bug 270] investigate nmigen clock gating
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 14:26:09 +0000 (14:26 +0000)]
Re: [libre-riscv-dev] Clock Gating (was cache SRAM organisation)
bugzilla-daemon [Sat, 28 Mar 2020 14:14:45 +0000 (14:14 +0000)]
[libre-riscv-dev] [Bug 270] New: investigate nmigen clock gating
Staf Verhaegen [Sat, 28 Mar 2020 14:08:25 +0000 (15:08 +0100)]
[libre-riscv-dev] Clock Gating (was cache SRAM organisation)
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 11:52:34 +0000 (11:52 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
bugzilla-daemon [Sat, 28 Mar 2020 11:12:43 +0000 (11:12 +0000)]
[libre-riscv-dev] [Bug 269] New: auto-conversion / parser of POWER ISA Spec v3.0B
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 10:02:22 +0000 (10:02 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jock Tanner [Sat, 28 Mar 2020 08:09:33 +0000 (18:09 +1000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Sat, 28 Mar 2020 06:07:16 +0000 (06:07 +0000)]
Re: [libre-riscv-dev] another
CDC6600 reference on IEEE
whygee [Sat, 28 Mar 2020 01:19:13 +0000 (02:19 +0100)]
[libre-riscv-dev] another
CDC6600 reference on IEEE
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 21:36:47 +0000 (21:36 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 21:32:01 +0000 (21:32 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jacob Lifshay [Fri, 27 Mar 2020 21:31:11 +0000 (14:31 -0700)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jacob Lifshay [Fri, 27 Mar 2020 21:29:15 +0000 (14:29 -0700)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 19:21:04 +0000 (19:21 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 19:20:38 +0000 (19:20 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Michael Nolan [Fri, 27 Mar 2020 16:56:24 +0000 (12:56 -0400)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Tobias Platen [Fri, 27 Mar 2020 16:35:45 +0000 (17:35 +0100)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
bugzilla-daemon [Fri, 27 Mar 2020 16:05:39 +0000 (16:05 +0000)]
[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 15:49:45 +0000 (15:49 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Immanuel, Yehowshua U [Fri, 27 Mar 2020 14:39:46 +0000 (14:39 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jacob Lifshay [Fri, 27 Mar 2020 14:18:33 +0000 (07:18 -0700)]
[libre-riscv-dev] Fwd: [llvm-dev] TTA-based Co-Design Environment (TCE) v1.21 Released
bugzilla-daemon [Fri, 27 Mar 2020 13:45:23 +0000 (13:45 +0000)]
[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 10:59:30 +0000 (10:59 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
bugzilla-daemon [Fri, 27 Mar 2020 10:55:40 +0000 (10:55 +0000)]
[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM
bugzilla-daemon [Fri, 27 Mar 2020 10:44:30 +0000 (10:44 +0000)]
[libre-riscv-dev] [Bug 268] nmigen does not seem to support write-through SRAM
Staf Verhaegen [Fri, 27 Mar 2020 10:36:15 +0000 (11:36 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 10:10:46 +0000 (10:10 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Lauri Kasanen [Fri, 27 Mar 2020 10:03:26 +0000 (12:03 +0200)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 09:52:22 +0000 (09:52 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
bugzilla-daemon [Fri, 27 Mar 2020 09:50:48 +0000 (09:50 +0000)]
[libre-riscv-dev] [Bug 268] New: nmigen does not seem to support write-through SRAM
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 09:46:52 +0000 (09:46 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 09:44:30 +0000 (09:44 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Fri, 27 Mar 2020 09:40:50 +0000 (10:40 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Fri, 27 Mar 2020 09:25:24 +0000 (10:25 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 09:16:15 +0000 (09:16 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Fri, 27 Mar 2020 09:08:48 +0000 (10:08 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 08:47:10 +0000 (08:47 +0000)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
Jacob Lifshay [Fri, 27 Mar 2020 05:49:27 +0000 (22:49 -0700)]
Re: [libre-riscv-dev] extremely busy crowdsupply update started
bugzilla-daemon [Fri, 27 Mar 2020 02:17:11 +0000 (02:17 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Luke Kenneth Casson Leighton [Fri, 27 Mar 2020 02:15:03 +0000 (02:15 +0000)]
[libre-riscv-dev] microwatt tlb
bugzilla-daemon [Fri, 27 Mar 2020 01:27:02 +0000 (01:27 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Fri, 27 Mar 2020 00:38:29 +0000 (00:38 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Fri, 27 Mar 2020 00:03:17 +0000 (00:03 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
bugzilla-daemon [Thu, 26 Mar 2020 23:10:07 +0000 (23:10 +0000)]
[libre-riscv-dev] [Bug 267] The efficiency of adder/subtractor
bugzilla-daemon [Thu, 26 Mar 2020 22:58:59 +0000 (22:58 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Hendrik Boom [Thu, 26 Mar 2020 22:41:20 +0000 (18:41 -0400)]
Re: [libre-riscv-dev] email etiquette
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 22:05:50 +0000 (22:05 +0000)]
Re: [libre-riscv-dev] [OP-CD] OpenPOWER Foundation "Virtual Coffee" Calls
bugzilla-daemon [Thu, 26 Mar 2020 22:05:29 +0000 (22:05 +0000)]
[libre-riscv-dev] [Bug 267] New: The efficiency of adder/subtractor
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 21:41:13 +0000 (21:41 +0000)]
Re: [libre-riscv-dev] email etiquette
bugzilla-daemon [Thu, 26 Mar 2020 21:41:16 +0000 (21:41 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 21:39:34 +0000 (21:39 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 21:37:12 +0000 (21:37 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Cole Poirier [Thu, 26 Mar 2020 21:33:02 +0000 (14:33 -0700)]
Re: [libre-riscv-dev] email etiquette
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 21:28:32 +0000 (21:28 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Jacob Lifshay [Thu, 26 Mar 2020 21:25:15 +0000 (14:25 -0700)]
[libre-riscv-dev] email etiquette
bugzilla-daemon [Thu, 26 Mar 2020 21:23:08 +0000 (21:23 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 21:03:24 +0000 (21:03 +0000)]
[libre-riscv-dev] extremely busy crowdsupply update started
bugzilla-daemon [Thu, 26 Mar 2020 20:58:58 +0000 (20:58 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Thu, 26 Mar 2020 20:34:34 +0000 (20:34 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 20:29:41 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Staf Verhaegen [Thu, 26 Mar 2020 20:18:34 +0000 (21:18 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Thu, 26 Mar 2020 20:08:04 +0000 (21:08 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Cole Poirier [Thu, 26 Mar 2020 19:42:49 +0000 (12:42 -0700)]
Re: [libre-riscv-dev] Setup automation scripts
bugzilla-daemon [Thu, 26 Mar 2020 19:39:46 +0000 (19:39 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 18:01:26 +0000 (18:01 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 17:56:17 +0000 (17:56 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 17:51:08 +0000 (17:51 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 17:41:30 +0000 (17:41 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 17:15:44 +0000 (17:15 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 17:06:04 +0000 (17:06 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Thu, 26 Mar 2020 16:57:47 +0000 (16:57 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 16:52:54 +0000 (16:52 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 15:15:06 +0000 (15:15 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 15:15:06 +0000 (15:15 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
bugzilla-daemon [Thu, 26 Mar 2020 14:56:30 +0000 (14:56 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 14:43:54 +0000 (14:43 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
projects / libre-riscv-dev.git / log