Merge remote-tracking branch 'origin/master' into xaig

Merge pull request #914 from YosysHQ/xc7srl

synth_xilinx to now infer SRL16E/SRLC32E

Temporarily remove 'r' extension

Update help message

Allow POs to be PIs in XAIG

Remove kernel/cost.cc since master has refactored it

Merge remote-tracking branch 'origin/master' into xaig

Merge pull request #952 from YosysHQ/clifford/fix370

Determine correct signedness and expression width in for-loop unrolling

Merge pull request #951 from YosysHQ/clifford/logdebug

Add log_debug() framework

Merge pull request #949 from YosysHQ/clifford/pmux2shimprove

Add full_pmux feature to pmux2shiftx

Merge pull request #953 from YosysHQ/clifford/fix948

Add support for zero-width signals to Verilog back-end

Move 'shregmap -tech xilinx' into map_cells

Add support for zero-width signals to Verilog back-end, fixes #948

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/master' into xc7srl

Determine correct signedness and expression width in for loop unrolling, fixes #370

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add log_debug() framework

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #950 from whitequark/attrmap_remove_wildcard

attrmap: extend -remove to allow removing attributes with any value

attrmap: extend -remove to allow removing attributes with any value.

Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.

Updaye pmux2shiftx test

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add full_pmux feature to pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Set ENABLE_LIBYOSYS=0 by default

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Set ENABLE_PYOSYS=0 by default

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #905 from christian-krieg/feature/python_bindings

Feature/python bindings

Merge pull request #941 from Wren6991/sim_lib_io_clke

ice40 cells_sim.v: update clock enable behaviour based on hardware experiments

Merge branch 'dh73-master'

Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master

Re-added clean after techmap in synth_xilinx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #916 from YosysHQ/map_cells_before_map_luts

synth_xilinx to map_cells before map_luts

Merge pull request #911 from mmicko/gowin-nobram

Make nobram false by default for gowin

Merge pull request #909 from zachjs/master

support repeat loops with constant repeat counts outside of constant functions

Merge pull request #944 from YosysHQ/clifford/pmux2shiftx

Add pmux2shiftx command

Merge pull request #945 from YosysHQ/clifford/libwb

New behavior for read_verilog handling of whiteboxes

Merge remote-tracking branch 'origin/clifford/libwb' into xaig

Disable blackbox detection in techmap files

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Tidy up, fix for -nosrl

Convert to use #945

Merge remote-tracking branch 'origin/clifford/libwb' into xaig

Merge branch 'map_cells_before_map_luts' into xc7srl

Merge branch 'master' into map_cells_before_map_luts

Add comments

Use new pmux2shiftx from #944, remove my old attempt

ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments

Fix tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "noblackbox" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/clifford/pmux2shiftx' into xc7srl

Merge remote-tracking branch 'origin/master' into xc7srl

New behavior for front-end handling of whiteboxes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/master' into xaig

Merge pull request #943 from YosysHQ/clifford/whitebox

[WIP] Add "whitebox" attribute, add "read_verilog -wb"

Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl

Merge remote-tracking branch 'origin' into xc7srl

Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "onehot" pass, improve "pmux2shiftx" onehot handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "techmap -wb", use in formal flows

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Check blackbox attribute in techmap/simplemap

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "wbflip" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #942 from YosysHQ/clifford/fix931

Improve proc full_case detection and handling

ABC_FLOPS -> ABC_MODEL -- only whitebox if ABC_MODEL set

Improve "pmux2shiftx"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix some typos

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in "pmux2shiftx"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Select to find union of both sets on stack

Fixes for simple_abc9 tests

Improvements in pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add test for pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve pmux2shift ctrl permutation finder

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Complete rewrite of pmux2shiftx

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Import initial pmux2shiftx from eddieh

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "show" handling of 0/1/X/Z padding

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Change "ne" to "neq" in btor2 output

we need to do this because they changed the parser:
https://github.com/Boolector/btor2tools/commit/e97fc9cedabadeec4f621de22096e514f862c690

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Do not assume inst_module is always present

ignore_boxes -> holes_mode

Make SB_DFF whitebox

Add tests/aiger/.gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Spelling fixes

Fix SB_DFF comb model

Revert "write_json to not write contents (cells/wires) of whiteboxes"

This reverts commit 4ef03e19a8eafc324d3442f0642abf858071fdd4.

Missing close bracket

Annotate SB_DFF* with abc_flop and abc_box_id

Add SB_DFF* to boxes

Add flop support for write_xaiger

read_aiger to parse 'r' extension

Spelling

Update to ABC 3709744

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #917 from YosysHQ/eddie/fix_retime

Retime by default when abc -dff

Use new -wb flag for ABC flow

write_json to not write contents (cells/wires) of whiteboxes

Ignore 'whitebox' attr in flatten with "-wb" option

write_json to not write contents (cells/wires) of whiteboxes

Ignore 'whitebox' attr in flatten with "-wb" option

Also update Makefile.inc

Fix abc's remap_name to not ignore [^0-9] when extracting sid

Make SB_LUT4 a blackbox

Fix rename

Rename to abc_*.{box,lut}

Merge remote-tracking branch 'origin/clifford/whitebox' into xaig

ABC to call retime all the time

Add "whitebox" attribute, add "read_verilog -wb"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Revert "synth_* with -retime option now calls abc with -D 1 as well"

This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.

Merge branch 'master' into eddie/fix_retime