mesa.git
9 years agogallivm: add LLVMAttribute parameter to lp_build_intrinsic
Marek Olšák [Sat, 25 Jul 2015 09:17:48 +0000 (11:17 +0200)]
gallivm: add LLVMAttribute parameter to lp_build_intrinsic

This will help remove some duplicated code from radeon.

Reviewed-by: Dave Airlie <airlied@redhat.com>
9 years agogallium/util: clear up that debug_get_flags_option returns a 64-bit mask
Marek Olšák [Sat, 25 Jul 2015 13:55:45 +0000 (15:55 +0200)]
gallium/util: clear up that debug_get_flags_option returns a 64-bit mask

Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
9 years agoradeonsi: completely rework updating descriptors without CP DMA
Marek Olšák [Fri, 24 Jul 2015 22:53:16 +0000 (00:53 +0200)]
radeonsi: completely rework updating descriptors without CP DMA

The patch has a better explanation. Just a summary here:
- The CPU always uploads a whole descriptor array to previously-unused memory.
- CP DMA isn't used.
- No caches need to be flushed.
- All descriptors are always up-to-date in memory even after a hang, because
  CP DMA doesn't serve as a middle man to update them.

This should bring:
- better hang recovery (descriptors are always up-to-date)
- better GPU performance (no KCACHE and TC flushes)
- worse CPU performance for partial updates (only whole arrays are uploaded)
- less used IB space (no CP_DMA and WRITE_DATA packets)
- simpler code
- hopefully, some of the corruption issues with SI cards will go away.
  If not, we'll know the issue is not here.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
9 years agoi965/fs: Fix regression with SIMD8 VS since b5f1a48e234d47b24df38cb562cffb8941d43795.
Francisco Jerez [Thu, 30 Jul 2015 11:45:57 +0000 (14:45 +0300)]
i965/fs: Fix regression with SIMD8 VS since b5f1a48e234d47b24df38cb562cffb8941d43795.

With num_direct_uniforms == 0 there's no space allocated in the
param_size array for the one block of direct uniforms -- On the FS
stage this would be a harmless no-op because it would simply re-set
one of the param_size entries allocated for the sampler units to zero,
but on the VS stage it has been reported to cause memory corruption
followed by a crash -- Surprising how a full piglit run on Gen8 didn't
catch it.

Reported-and-reviewed-by: "Lofstedt, Marta" <marta.lofstedt@intel.com>
9 years agoi965/gen9: Add hs, ds, and cs thread + urb info
Ben Widawsky [Fri, 31 Jul 2015 02:16:32 +0000 (19:16 -0700)]
i965/gen9: Add hs, ds, and cs thread + urb info

For SKL: These are the production values.

For BXT: These are low estimates to enable platforms.

This patch was originally part of
i965/skl: Add production thread counts and URB size
but was split out at Jordan's request (which I found to be reasonable).

Note on stable inclusion: 10.6 does not care about hs, and ds. It does care
about cs, but since Jordan was the one that asked me to extract it, I'll leave
it up to him to deal with a backport to stable is required.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agoi965/bxt: Use more conservative thread counts
Ben Widawsky [Fri, 31 Jul 2015 02:12:15 +0000 (19:12 -0700)]
i965/bxt: Use more conservative thread counts

Since we really do not know what may occur in the future, pick a more
conservative value for thread counts until we know better what values are
correct. As far as I can tell, the old values will work fine, but some of the
registers seem to indicate that going even lower is possible and the purpose of
having early support is to enable as many configurations that can possibly
exist (we can trim things down after platforms begin shipping later).

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agoi965/skl: Add production thread counts and URB size
Ben Widawsky [Wed, 29 Jul 2015 19:35:24 +0000 (12:35 -0700)]
i965/skl: Add production thread counts and URB size

This patch adjusts the SKL values to the best known values we have.

v2: Remove HS/DS/CS fields. Adding this makes most sense to add to the
GEN9_FEATURES macro, however, doing that would require updating BXT values, and
Jordan requested I not do that. Conveniently, this request makes a lot of sense
wrt to stable backport as HS, and DS do not even exist there.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
9 years agovc4: Lower uniform loads to scalar in NIR.
Eric Anholt [Thu, 30 Jul 2015 18:16:13 +0000 (11:16 -0700)]
vc4: Lower uniform loads to scalar in NIR.

This also moves the vec4-to-byte-addressing math into NIR, so that
algebraic has a chance at it.

9 years agovc4: Move some FS input lowering into NIR.
Eric Anholt [Thu, 30 Jul 2015 00:27:54 +0000 (17:27 -0700)]
vc4: Move some FS input lowering into NIR.

9 years agovc4: Move program keys to the header file.
Eric Anholt [Thu, 30 Jul 2015 00:29:39 +0000 (17:29 -0700)]
vc4: Move program keys to the header file.

I want to be able to inspect them from other files for lowering passes in
NIR.

9 years agovc4: Lower NIR inputs to scalar as well.
Eric Anholt [Thu, 30 Jul 2015 00:16:26 +0000 (17:16 -0700)]
vc4: Lower NIR inputs to scalar as well.

For now this is just scalarizing, but it also means we'll get to dump a
bunch of QIR-based lowering in a moment.

9 years agovc4: Start adding a NIR-based output lowering pass.
Eric Anholt [Wed, 29 Jul 2015 22:52:18 +0000 (15:52 -0700)]
vc4: Start adding a NIR-based output lowering pass.

For now, this just splits up store_output intrinsics to be scalars, and
drops unused outputs in the coordinate shader.  My goal is to be able to
drop a bunch of my VC4-specific optimization by letting NIR handle it.

9 years agovc4: Mark our shaders as single-threaded.
Eric Anholt [Wed, 29 Jul 2015 19:16:50 +0000 (12:16 -0700)]
vc4: Mark our shaders as single-threaded.

I had my understanding of this bit flipped.  We're using the full register
space, so we need to say so.

9 years agovc4: Avoid leaking indirect array access UBOs.
Eric Anholt [Wed, 29 Jul 2015 21:41:22 +0000 (14:41 -0700)]
vc4: Avoid leaking indirect array access UBOs.

9 years agovc4: Avoid overflowing various static tables.
Eric Anholt [Wed, 29 Jul 2015 21:40:10 +0000 (14:40 -0700)]
vc4: Avoid overflowing various static tables.

9 years agovc4: Fix return values from recent validation changes.
Eric Anholt [Wed, 29 Jul 2015 19:20:33 +0000 (12:20 -0700)]
vc4: Fix return values from recent validation changes.

9 years agodocs: trivial cleanup of GL3.txt, remove redundant radeonsi entries.
Kai Wasserbäch [Thu, 30 Jul 2015 18:32:36 +0000 (20:32 +0200)]
docs: trivial cleanup of GL3.txt, remove redundant radeonsi entries.

Follow-up to 1b2b0e42ce47bfd1fcb5513ed2c23b9bb7a5a5b8

Signed-off-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agost/mesa: don't draw instead of asserting in transform feedback
Dave Airlie [Thu, 30 Jul 2015 10:44:50 +0000 (20:44 +1000)]
st/mesa: don't draw instead of asserting in transform feedback

if we get a request to take the count from feedback, but there
is no buffer to take it from, just draw as if we got 0 vertices
so nothing.

This fixes this assert killing the ogl conform, and a piglit
test I've sent.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agomesa: remove now unused _mesa_get_uniform_location
Timothy Arceri [Fri, 3 Jul 2015 22:35:35 +0000 (08:35 +1000)]
mesa: remove now unused _mesa_get_uniform_location

Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agomesa: remove now unused subscript validations
Timothy Arceri [Sat, 25 Jul 2015 02:39:43 +0000 (12:39 +1000)]
mesa: remove now unused subscript validations

Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agomesa: fix and simplify resource query for arrays
Timothy Arceri [Sat, 25 Jul 2015 02:33:53 +0000 (12:33 +1000)]
mesa: fix and simplify resource query for arrays

This removes the need for multiple functions designed to validate an array
subscript and replaces them with a call to a single function.

The change also means that validation is now only done once and the index
is retrived at the same time, as a result the getUniformLocation code can
be simplified saving an extra hash table lookup (and yet another
validation call).

This chage also fixes some tests in:
ES31-CTS.program_interface_query.uniform

V3: rebase on subroutines, and move the resource index array == 0
check into _mesa_GetProgramResourceIndex() to simplify things further

V2: Fix bounds checks for program input/output, split unrelated comment fix
and _mesa_get_uniform_location() removal into their own patch.

Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agoi965/bxt: Don't use brw_device_info_skl_early on BXT
Neil Roberts [Wed, 29 Jul 2015 16:40:37 +0000 (17:40 +0100)]
i965/bxt: Don't use brw_device_info_skl_early on BXT

Previously it could end up using the “SKL early” device on BXT
depending on the revision number. This would probably break things
because for example has_llc would be wrong.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoglsl: set stage flag for structs and arrays in resource list
Timothy Arceri [Sat, 4 Jul 2015 05:43:15 +0000 (15:43 +1000)]
glsl: set stage flag for structs and arrays in resource list

This fixes the remaining failing tests in:
ES31-CTS.program_interface_query.uniform-types

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agodocs: consolidate radeonsi in GL3.txt
Dave Airlie [Wed, 29 Jul 2015 09:51:46 +0000 (10:51 +0100)]
docs: consolidate radeonsi in GL3.txt

move into DONE for GL4.0 and GL4.1

Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agoradeonsi: enable GL4.1 and update documentation (v2)
Dave Airlie [Wed, 22 Jul 2015 00:24:39 +0000 (01:24 +0100)]
radeonsi: enable GL4.1 and update documentation (v2)

This enables GL4.1 for radeonsi, and updates the
docs in the correct places.

v2: enable only for llvm 3.7 which has fixes in place.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agoradeonsi: add GS multiple streams support (v2)
Dave Airlie [Mon, 20 Jul 2015 01:37:14 +0000 (02:37 +0100)]
radeonsi: add GS multiple streams support (v2)

This is the final piece for ARB_gpu_shader5,

The code is based on the r600 code from Glenn Kennard,
and myself.

While developing this, I'm not 100% sure of all the calculations
made in the GS registers, this is why the max_stream is worked
out there and used to limit the changes in registers. Otherwise
my initial attempts either regressed GS texelFetch tests
or primitive-id-restart. The current code has no regressions
in piglit.

This commit doesn't enable ARB_gpu_shader5, since that just
bumps the glsl level to 4.00, so I'll just do a separate patch
for 4.10.

v1.1: fix bug introduced in rebase.
v2: Address Marek's review comments,
remove my llvm stream code for simpler C,
move gsvs_ring and gs_next_vertex to arrays.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
9 years agoDelete unused functions in format parser
Anuj Phogat [Wed, 29 Jul 2015 17:15:03 +0000 (10:15 -0700)]
Delete unused functions in format parser

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
9 years agoi965: Change the type of max_{vs, hs, ...}_threads variables to unsigned
Anuj Phogat [Wed, 29 Jul 2015 16:57:26 +0000 (09:57 -0700)]
i965: Change the type of max_{vs, hs, ...}_threads variables to unsigned

Fixes following compiler warning:
brw_cs.cpp:386:27: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
9 years agoDelete duplicate function is_power_of_two() and use _mesa_is_pow_two()
Anuj Phogat [Wed, 29 Jul 2015 16:41:18 +0000 (09:41 -0700)]
Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
9 years agogallium/auxiliary: Ensure c99_math.h is included.
Jose Fonseca [Wed, 29 Jul 2015 19:45:09 +0000 (20:45 +0100)]
gallium/auxiliary: Ensure c99_math.h is included.

As it is needed for exp2.

Trivial.

9 years agoc99_math: (trivial) implement exp2 for MSVC too
Roland Scheidegger [Wed, 29 Jul 2015 20:20:04 +0000 (22:20 +0200)]
c99_math: (trivial) implement exp2 for MSVC too

Unsurprisingly doesn't build otherwise with old msvc.

9 years agoi965/bxt: Support 3src simd16 instructions
Ben Widawsky [Wed, 29 Jul 2015 02:52:49 +0000 (19:52 -0700)]
i965/bxt: Support 3src simd16 instructions

This is easily accomplished by moving simd16 3src to GEN9_FEATURES.

v2: small cleanup to make it more similar to GEN8_FEATURES

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agotargets/dri: scons: add missing link against libdrm
Emil Velikov [Wed, 22 Jul 2015 15:04:28 +0000 (16:04 +0100)]
targets/dri: scons: add missing link against libdrm

Otherwise the final dri module will have (additional) unresolved
symbols.

Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviwed-by: Jose Fonseca <jfonseca@vmware.com>
9 years agosvga: scons: remove unused HAVE_SYS_TYPES_H define
Emil Velikov [Fri, 17 Jul 2015 17:18:20 +0000 (18:18 +0100)]
svga: scons: remove unused HAVE_SYS_TYPES_H define

There isn't a single instance in mesa that
mentions HAVE_SYS_TYPES_H, other than this file.

Cc: Jose Fonseca <jfonseca@vmware.com>
Acked-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agoglsl: Avoid double promotion.
Matt Turner [Thu, 16 Jul 2015 04:29:21 +0000 (21:29 -0700)]
glsl: Avoid double promotion.

9 years agomesa: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 06:15:42 +0000 (23:15 -0700)]
mesa: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agomesa/math: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 06:15:32 +0000 (23:15 -0700)]
mesa/math: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agoprogram: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 06:15:19 +0000 (23:15 -0700)]
program: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agoswrast: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 06:15:10 +0000 (23:15 -0700)]
swrast: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agotnl: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 06:15:01 +0000 (23:15 -0700)]
tnl: Avoid double promotion.

There are a couple of unrelated changes in t_vb_lighttmp.h that I hope
you'll excuse -- there's a block of code that's duplicated modulo a few
trivial differences that I took the liberty of fixing.

9 years agovbo: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 06:14:54 +0000 (23:14 -0700)]
vbo: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agoutil: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 01:01:54 +0000 (18:01 -0700)]
util: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agogallium/auxiliary: Avoid double promotion.
Matt Turner [Mon, 13 Jul 2015 01:01:42 +0000 (18:01 -0700)]
gallium/auxiliary: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
9 years agonir: Avoid double promotion.
Matt Turner [Sun, 12 Jul 2015 19:37:00 +0000 (12:37 -0700)]
nir: Avoid double promotion.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agoi965: Use float calculations when double is unnecessary.
Matt Turner [Sun, 12 Jul 2015 07:13:45 +0000 (00:13 -0700)]
i965: Use float calculations when double is unnecessary.

Literals without an f/F suffix are of type double, and implicit
conversion rules specify that the float in (float op double) be
converted to a double before the operation is performed. I believe float
execution was intended (in nearly all cases) or is sufficient (in the
case of gen7_urb.c).

Removes a lot of float <-> double conversion instructions and replaces
many double instructions with float instructions which are cheaper.

   text     data      bss      dec      hex  filename
4928659   195160    26192  5150011   4e953b  i965_dri.so before
4928315   195152    26192  5149659   4e93db  i965_dri.so after

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
9 years agogallium/auxiliary: Use exp2(x) instead of pow(2.0, x).
Matt Turner [Mon, 13 Jul 2015 22:19:54 +0000 (15:19 -0700)]
gallium/auxiliary: Use exp2(x) instead of pow(2.0, x).

9 years agoprogram: Use exp2(x) instead of pow(2.0, x).
Matt Turner [Mon, 13 Jul 2015 22:19:33 +0000 (15:19 -0700)]
program: Use exp2(x) instead of pow(2.0, x).

9 years agomesa: Use floats for viewport bounds.
Matt Turner [Sun, 12 Jul 2015 05:46:19 +0000 (22:46 -0700)]
mesa: Use floats for viewport bounds.

ARB_viewport_array specifies that DEPTH_RANGE consists of double-
precision parameters (corresponding commit d4dc35987), and a preparatory
commit (6340e609a) added _mesa_get_viewport_xform() which returned
double-precision scale[3] and translate[3] vectors, even though X, Y,
Width, and Height were still floats.

All users of _mesa_get_viewport_xform() immediately convert the double
scale and translation vectors into floats (which were floats originally,
but were converted to doubles in _mesa_get_viewport_xform(), sigh).

i965 at least cannot consume doubles (see SF_CLIP_VIEWPORT). If we want
to pass doubles to hardware, we should have a different function that
does that.

Acked-by: Mathias Froehlich <Mathias.Froehlich@web.de>
9 years agoc99_math: Implement exp2f for MSVC.
Matt Turner [Thu, 16 Jul 2015 04:28:56 +0000 (21:28 -0700)]
c99_math: Implement exp2f for MSVC.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
9 years agoglsl: Remove MSVC implementations of copysign and isnormal.
Matt Turner [Thu, 16 Jul 2015 03:54:46 +0000 (20:54 -0700)]
glsl: Remove MSVC implementations of copysign and isnormal.

Non-Gallium parts of Mesa require MSVC 2013 which provides these.

9 years agoi965/fs: Make the default builder 64-wide before entering the optimization loop.
Francisco Jerez [Mon, 27 Jul 2015 15:51:01 +0000 (18:51 +0300)]
i965/fs: Make the default builder 64-wide before entering the optimization loop.

Not a typo.  Replace the default builder with one of bogus width to
catch cases in which optimization passes assume that the default
dispatch width is good enough.  The execution controls of instructions
emitted during optimization should in general match the original code
that is being manipulated.  Many of the problems fixed in this series
were caught by the assertions introduced in this patch.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Don't set exec_all on instructions wider than the original in lower_simd_width.
Francisco Jerez [Mon, 27 Jul 2015 15:42:31 +0000 (18:42 +0300)]
i965/fs: Don't set exec_all on instructions wider than the original in lower_simd_width.

This could have led to somewhat increased bandwidth usage for lowered
texturing instructions on Gen4 (which is the only case in which
lower_width may be greater than inst->exec_size).  After the previous
patches the invariant mentioned in the comment should no longer be
assumed by any of the other optimization and lowering passes, so the
exec_all() call shouldn't be necessary anymore.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Initialize a builder explicitly in the gen4 send dependency work-arounds.
Francisco Jerez [Mon, 27 Jul 2015 15:28:39 +0000 (18:28 +0300)]
i965/fs: Initialize a builder explicitly in the gen4 send dependency work-arounds.

Instead of relying on the default one.  This shouldn't lead to any
functional changes because DEP_RESOLVE_MOV overrides the execution
size of the instruction anyway and other execution controls are
irrelevant.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/cfg: Assert that cur_do/while/if pointers are non-NULL.
Matt Turner [Sat, 11 Jul 2015 02:49:49 +0000 (19:49 -0700)]
i965/cfg: Assert that cur_do/while/if pointers are non-NULL.

More.. like in commit 4d93a07c.

9 years agonvc0/ir: cache vertex out base so that we don't recompute again
Ilia Mirkin [Wed, 29 Jul 2015 15:01:08 +0000 (11:01 -0400)]
nvc0/ir: cache vertex out base so that we don't recompute again

The global CSE pass stinks and is unable to pull this out. Easy enough
to handle it here and avoid generating unnecessary special register
loads (which can allegedly be quite slow).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agonvc0/ir: output base for reading is based on laneid
Ilia Mirkin [Wed, 29 Jul 2015 13:37:14 +0000 (09:37 -0400)]
nvc0/ir: output base for reading is based on laneid

PFETCH retrieves the address for incoming vertices, not output vertices
in TCS. For output vertices, we must use the laneid as a base.

Fixes barrier piglit test, which was failing for entirely non-barrier
reasons, but rather that it was (a) trying to draw multiple patches and
(b) the incoming patch size was not the same as the outgoing patch size.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
9 years agoRevert "pipe-loader: simplify pipe_loader_drm_probe"
Francisco Jerez [Wed, 29 Jul 2015 12:37:52 +0000 (15:37 +0300)]
Revert "pipe-loader: simplify pipe_loader_drm_probe"

This reverts commit a27ec5dc460b91dc44675f48cddbbb2631ee824f.  It
breaks the intended behaviour of pipe_loader_probe() with ndev==0 as
relied upon by clover to query the number of devices available to the
pipe loader in the system.

Acked-by: Emil Velikov <emil.l.velikov@gmail.com>
9 years agoi965/fs: Switch opt_cse() to the fs_builder constructor from instruction.
Francisco Jerez [Mon, 27 Jul 2015 16:18:51 +0000 (19:18 +0300)]
i965/fs: Switch opt_cse() to the fs_builder constructor from instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Switch lower_logical_sends() to the fs_builder constructor from instruction.
Francisco Jerez [Mon, 27 Jul 2015 15:41:18 +0000 (18:41 +0300)]
i965/fs: Switch lower_logical_sends() to the fs_builder constructor from instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Switch lower_load_payload() to the fs_builder constructor from instruction.
Francisco Jerez [Mon, 27 Jul 2015 15:34:43 +0000 (18:34 +0300)]
i965/fs: Switch lower_load_payload() to the fs_builder constructor from instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Don't rely on the default builder to create a null register in emit_spill.
Francisco Jerez [Mon, 27 Jul 2015 17:14:41 +0000 (20:14 +0300)]
i965/fs: Don't rely on the default builder to create a null register in emit_spill.

It's not guaranteed to have the same width as the instruction
generating the spilled variable.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Set up the builder execution size explicitly in opt_sampler_eot().
Francisco Jerez [Mon, 27 Jul 2015 15:15:44 +0000 (18:15 +0300)]
i965/fs: Set up the builder execution size explicitly in opt_sampler_eot().

opt_sampler_eot() was relying on the default builder to have the same
width as the sampler and FB write opcodes it was eliminating, the
channel selects didn't matter because the builder was only being used
to allocate registers, no new instructions were being emitted with it.
A future commit will change the width of the default builder what will
break this assumption, so initialize it explicitly here.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Initialize a builder explicitly in opt_peephole_predicated_break().
Francisco Jerez [Mon, 27 Jul 2015 16:20:50 +0000 (19:20 +0300)]
i965/fs: Initialize a builder explicitly in opt_peephole_predicated_break().

This wasn't taking into account the execution controls of the original
instruction, but it was most likely not a bug because control flow
instructions are typically full width.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Set execution controls explicitly in opt_peephole_sel().
Francisco Jerez [Mon, 27 Jul 2015 16:27:30 +0000 (19:27 +0300)]
i965/fs: Set execution controls explicitly in opt_peephole_sel().

Emit the SELs and MOVs with the same execution controls as the
original MOVs, and the CMP with the same execution controls as the IF.
Also explicitly check that the execution controls of any pair of MOVs
being folded into a SEL are compatible (which is almost always going
to be the case), since otherwise it would seem wrong to initialize the
builder object below from the then_mov instruction only.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Set execution controls correctly in lower_integer_multiplication().
Francisco Jerez [Mon, 27 Jul 2015 15:38:59 +0000 (18:38 +0300)]
i965/fs: Set execution controls correctly in lower_integer_multiplication().

lower_integer_multiplication() was ignoring the execution controls of
the original MUL instruction.  Fix it by using the new fs_builder
constructor.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Set execution controls correctly for lowered pull constant loads.
Francisco Jerez [Mon, 27 Jul 2015 14:55:49 +0000 (17:55 +0300)]
i965/fs: Set execution controls correctly for lowered pull constant loads.

demote_pull_constants() was ignoring the execution size and channel
selects of the instruction that wanted the constant, which doesn't
matter for uniform pull constant loads because all channels get the
same scalar value, but it might for varying pull constant loads.  Fix
it by using the new fs_builder() constructor that takes care of
setting execution controls compatible with the instruction passed as
argument.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Set the execution size of the MOVs correctly in opt_combine_constants().
Francisco Jerez [Mon, 27 Jul 2015 16:09:45 +0000 (19:09 +0300)]
i965/fs: Set the execution size of the MOVs correctly in opt_combine_constants().

The execution size was being left equal to the default of 8/16, which
AFAICT would have overwritten components other than the one we wanted
to initialize and could potentially have corrupted other registers.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Define a new fs_builder constructor taking an instruction as argument.
Francisco Jerez [Mon, 27 Jul 2015 14:54:46 +0000 (17:54 +0300)]
i965/fs: Define a new fs_builder constructor taking an instruction as argument.

We have a number of optimization passes that repeat the same pattern
before inserting new instructions into the program based on some
previous instruction: They point the default builder at the original
instruction, then call exec_all() and group() to select the same
execution controls the original instruction had, and then maybe call
annotate() to clone the debug annotation from the original
instruction.

In fact an optimization pass missing any of these steps is likely to
be broken if the intention was to emit new code based on a preexisting
instruction, so let's make it easy for passes to do the right thing by
having an fs_builder constructor that automates the task of setting up
a builder to emit a given instruction provided as argument.

The following patches fix all cases I've found in which we weren't
explicitly initializing the execution controls of the emitted
instructions, and clean-up optimization passes which were already
doing the right thing to use the new constructor.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Translate memory barrier NIR intrinsics.
Francisco Jerez [Mon, 27 Jul 2015 13:25:55 +0000 (16:25 +0300)]
i965/fs: Translate memory barrier NIR intrinsics.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Execute nir_setup_uniforms, _inputs and _outputs unconditionally.
Francisco Jerez [Sun, 28 Jun 2015 18:15:28 +0000 (21:15 +0300)]
i965/fs: Execute nir_setup_uniforms, _inputs and _outputs unconditionally.

Images take up zero uniform slots in the nir_shader::num_uniforms
calculation, but nir_setup_uniforms needs to be executed even if the
program has no non-image uniforms so the driver-specific image
parameters are uploaded.  nir_setup_uniforms is a no-op if there are
really no uniforms, so checking the num_uniform count is useless in
any case.

The nir_setup_inputs and _outputs changes shouldn't lead to any
functional change, they are just meant to preserve the symmetry
between them and nir_setup_uniforms.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Don't overwrite fs_visitor::uniforms and ::param_size during the SIMD16...
Francisco Jerez [Tue, 5 May 2015 19:12:03 +0000 (22:12 +0300)]
i965/fs: Don't overwrite fs_visitor::uniforms and ::param_size during the SIMD16 run.

Image variables need to allocate additional uniform slots over
nir_shader::num_uniforms.  nir_setup_uniforms() overwrites the values
imported from the SIMD8 visitor and then exits early before entering
the nir_shader::uniforms loop, so image uniforms are never re-created.
Instead leave the imported values alone, they *must* be the same for
the uniform layout of both runs to be compatible.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Drop unused untyped surface read and atomic emit methods.
Francisco Jerez [Mon, 29 Jun 2015 13:50:49 +0000 (16:50 +0300)]
i965/fs: Drop unused untyped surface read and atomic emit methods.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Revisit NIR atomic counter intrinsic translation.
Francisco Jerez [Tue, 5 May 2015 17:52:58 +0000 (20:52 +0300)]
i965/fs: Revisit NIR atomic counter intrinsic translation.

Rewrite the NIR atomic counter intrinsics translation code making use
of the recently introduced surface builder.  This will allow the
removal of some of the functionality duplicated between the visitor
and surface builder.

v2: Drop VEC4 suport.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Import surface message builder helper functions.
Francisco Jerez [Thu, 30 Apr 2015 16:31:44 +0000 (19:31 +0300)]
i965/fs: Import surface message builder helper functions.

Implement helper functions that can be used to construct and send
untyped and typed surface read, write and atomic messages to the
shared dataport unit easily.

v2: Drop VEC4 suport.
v3: Reimplement in terms of logical send opcodes.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Handle zero-size allocations in fs_builder::vgrf().
Francisco Jerez [Mon, 13 Jul 2015 12:39:03 +0000 (15:39 +0300)]
i965/fs: Handle zero-size allocations in fs_builder::vgrf().

This will be handy to avoid some ugly ternary operators in the next
patch, like:
 fs_reg reg = (size == 0 ? null_reg_ud() : vgrf(..., size));

Because a zero-size register allocation is guaranteed not to ever be
read or written we can just return the null register.  Another
possibility would be to actually allocate a zero-size VGRF what would
involve defining a zero-size register class in the register allocator
and a considerable amount of churn.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Implement lowering of logical surface instructions.
Francisco Jerez [Tue, 14 Jul 2015 15:42:57 +0000 (18:42 +0300)]
i965/fs: Implement lowering of logical surface instructions.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Hook up SIMD lowering to unroll surface instructions of unsupported width.
Francisco Jerez [Sat, 18 Jul 2015 13:16:19 +0000 (16:16 +0300)]
i965/fs: Hook up SIMD lowering to unroll surface instructions of unsupported width.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Define logical typed and untyped surface opcodes.
Francisco Jerez [Tue, 21 Jul 2015 15:45:32 +0000 (18:45 +0300)]
i965/fs: Define logical typed and untyped surface opcodes.

Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects its arguments
separately as individual sources, like:

 typed_surface_write_logical null, coordinates, source, surface,
                                    num_coordinates, num_components

This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mainly as
documentation for their source registers.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965: Lift the constness restriction on surface indices passed to untyped ops.
Francisco Jerez [Mon, 20 Jul 2015 14:38:15 +0000 (17:38 +0300)]
i965: Lift the constness restriction on surface indices passed to untyped ops.

v2: Update NIR atomic intrinsic handling too (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965: Define the setup_vector_uniform_values() backend_visitor interface.
Francisco Jerez [Sun, 28 Jun 2015 18:04:17 +0000 (21:04 +0300)]
i965: Define the setup_vector_uniform_values() backend_visitor interface.

This cleans up the VEC4 implementation of setup_uniform_values()
somewhat and will avoid duplication of the image uniform upload code
by having a common interface to upload a vector of uniforms on either
back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Remove the emit_texture_gen*() fs_visitor methods.
Francisco Jerez [Fri, 24 Jul 2015 13:51:14 +0000 (16:51 +0300)]
i965/fs: Remove the emit_texture_gen*() fs_visitor methods.

This is now dead code.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Reimplement emit_mcs_fetch() in terms of logical sends.
Francisco Jerez [Fri, 17 Jul 2015 15:23:31 +0000 (18:23 +0300)]
i965/fs: Reimplement emit_mcs_fetch() in terms of logical sends.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Reimplement emit_texture() in terms of logical send messages.
Francisco Jerez [Mon, 13 Jul 2015 13:07:45 +0000 (16:07 +0300)]
i965/fs: Reimplement emit_texture() in terms of logical send messages.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Hook up SIMD lowering to handle texturing opcodes of unsupported width.
Francisco Jerez [Mon, 13 Jul 2015 18:19:52 +0000 (21:19 +0300)]
i965/fs: Hook up SIMD lowering to handle texturing opcodes of unsupported width.

This should match the set of cases in which we currently call fail()
or no16() from the emit_texture_*() methods and the ones in which
emit_texture_gen4() enables the SIMD16 workaround.

Hint for reviewers: It's not a big deal if I happen to have missed
some case here, it will just lead to an assertion failure down the
road which is easily fixable, however being stricter than necessary
won't cause any visible breakage, it would just decrease performance
silently due to the unnecessary message splitting, so feel free to
double-check that all cases listed here already cause a SIMD8/16
fall-back with the current texturing code -- You may want to skip over
the Gen5-6 cases though if you don't have pencil and paper at hand.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Implement lowering of logical texturing opcodes on Gen4.
Francisco Jerez [Sat, 18 Jul 2015 14:09:37 +0000 (17:09 +0300)]
i965/fs: Implement lowering of logical texturing opcodes on Gen4.

Unlike its Gen5 and Gen7 counterparts this patch isn't a plain
refactor of the previous Gen4 texturing code, it's more of a rewrite
largely based on emit_texture_gen4_simd16().  The reason is that on
the one hand the original emit_texture_gen4() code didn't seem easily
fixable to be SIMD width-invariant and had plenty of clutter to
support SIMD-width workarounds which are no longer required.  On the
other hand emit_texture_gen4_simd16() was missing a number of
SIMD8-only opcodes.  This should generalize both and roughly match
their current behaviour where there is overlap.

Incidentally this will fix the following piglits on Gen4:

    arb_shader_texture_lod.execution.arb_shader_texture_lod-texgrad
    arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 2d
    arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 3d
    arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d
    arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d_projvec4
    arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 3d

Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Implement lowering of logical texturing opcodes on Gen5-6.
Francisco Jerez [Sat, 18 Jul 2015 13:52:06 +0000 (16:52 +0300)]
i965/fs: Implement lowering of logical texturing opcodes on Gen5-6.

This should be largely equivalent to emit_texture_gen5() except for
slight codestyle changes and the use i965 opcodes instead of the
ir_texture_opcode enum, see "i965/fs: Implement lowering of logical
texturing opcodes on Gen7+." for the mapping between them.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Lower SHADER_OPCODE_TXF_UMS/MCS_LOGICAL too on Gen7+.
Francisco Jerez [Fri, 17 Jul 2015 15:50:27 +0000 (18:50 +0300)]
i965/fs: Lower SHADER_OPCODE_TXF_UMS/MCS_LOGICAL too on Gen7+.

These weren't being handled by emit_texture_gen7() but we can easily
lower them here for consistency with other texturing opcodes.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Implement lowering of logical texturing opcodes on Gen7+.
Francisco Jerez [Mon, 13 Jul 2015 15:08:51 +0000 (18:08 +0300)]
i965/fs: Implement lowering of logical texturing opcodes on Gen7+.

This should be largely equivalent to emit_texture_gen7() except that
we now get i965 sampling opcodes directly rather than
ir_texture_opcode enum values.  The mapping is as follows:

 - ir_tex -> SHADER_OPCODE_TEX
 - ir_txb -> FS_OPCODE_TXB
 - ir_txl -> SHADER_OPCODE_TXL
 - ir_txd -> SHADER_OPCODE_TXD
 - ir_txf -> SHADER_OPCODE_TXF
 - ir_txf_ms -> SHADER_OPCODE_TXF_CMS
 - ir_txs -> SHADER_OPCODE_TXS
 - ir_query_levels -> SHADER_OPCODE_TXS too, the visitor will make
                      sure that the provided lod value is zero in this
                      case.
 - ir_lod -> SHADER_OPCODE_LOD
 - ir_tg4 -> SHADER_OPCODE_TG4_OFFSET if the offset value is not
             immediate, SHADER_OPCODE_TG4 otherwise.

Other than that there are only minor changes and style fixes like the
implementation now being factored out in static functions to improve
encapsulation.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Fix misleading comment regarding the message header in emit_texture_gen7.
Francisco Jerez [Fri, 24 Jul 2015 13:41:19 +0000 (16:41 +0300)]
i965/fs: Fix misleading comment regarding the message header in emit_texture_gen7.

This hasn't been overallocating space for the header for a long time.
It still leaves the header uninitialized though until the generator
fixes it.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
9 years agoi965/fs: Pass a BAD_FILE header source to LOAD_PAYLOAD in emit_texture_gen7().
Francisco Jerez [Fri, 17 Jul 2015 15:46:21 +0000 (18:46 +0300)]
i965/fs: Pass a BAD_FILE header source to LOAD_PAYLOAD in emit_texture_gen7().

So that it's left uninitialized by LOAD_PAYLOAD, we only need to
reserve space for it in the message since it will be initialized
implicitly by the generator.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Fix opt_zero_samples() for texturing ops not matching dispatch_width.
Francisco Jerez [Mon, 13 Jul 2015 12:33:04 +0000 (15:33 +0300)]
i965/fs: Fix opt_zero_samples() for texturing ops not matching dispatch_width.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Use exec_size instead of dispatch_width to determine the message variant.
Francisco Jerez [Mon, 13 Jul 2015 12:42:20 +0000 (15:42 +0300)]
i965/fs: Use exec_size instead of dispatch_width to determine the message variant.

dispatch_width is global for a single compilation and doesn't
necessarily match the desired execution width if we had to lower the
original full-width instruction due to hardware limitations.  These
were all inside a Gen4-specific branch so this patch shouldn't have
any effect on more recent hardware.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Define logical texture sampling opcodes.
Francisco Jerez [Tue, 21 Jul 2015 15:42:27 +0000 (18:42 +0300)]
i965/fs: Define logical texture sampling opcodes.

Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:

 tex_logical dst, coordinates, shadow_c, lod, lod2,
                  sample_index, mcs, sampler, offset,
                  num_coordinate_components, num_grad_components

This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Reimplement emit_single_fb_write() in terms of logical framebuffer writes.
Francisco Jerez [Thu, 16 Jul 2015 13:12:48 +0000 (16:12 +0300)]
i965/fs: Reimplement emit_single_fb_write() in terms of logical framebuffer writes.

The only non-trivial thing it still has to do is figure out where to
take the src/dst depth values from and predicate the instruction if
discard is in use.  The manual SIMD unrolling logic in the dual-source
case goes away because this is now handled transparently by the SIMD
lowering pass.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Implement lowering of logical framebuffer writes.
Francisco Jerez [Mon, 13 Jul 2015 14:59:34 +0000 (17:59 +0300)]
i965/fs: Implement lowering of logical framebuffer writes.

This does essentially the same thing as
fs_visitor::emit_single_fb_write(), with some slight differences:

 - We don't have to worry about exec_size and use_2nd_half anymore,
   16-wide sources have already been lowered to 8-wide thanks to the
   previous commit and the manual argument unzipping is no longer
   required.

 - The src/dst_depth and sample_mask values are now explicit sources
   of the instruction instead of being taken from the visitor state
   directly.  The same goes for the kill-pixel mask that will be
   passed to the instruction explicitly as predicate.

 - Everything is now done in static functions to improve
   encapsulation.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Hook up SIMD lowering to unroll FB writes of unsupported width.
Francisco Jerez [Mon, 13 Jul 2015 18:19:28 +0000 (21:19 +0300)]
i965/fs: Hook up SIMD lowering to unroll FB writes of unsupported width.

This shouldn't have any effect because we don't emit logical
framebuffer writes yet.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.
Francisco Jerez [Mon, 13 Jul 2015 11:49:27 +0000 (14:49 +0300)]
i965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.

This is now unused.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Don't attempt to copy the useless half of oMask for SIMD8 FB writes.
Francisco Jerez [Wed, 15 Jul 2015 14:31:04 +0000 (17:31 +0300)]
i965/fs: Don't attempt to copy the useless half of oMask for SIMD8 FB writes.

There's no need to initialize the wrong half of oMask in the payload
when we're doing an 8-wide framebuffer write because it will be
ignored by the hardware anyway.  By doing it this way we can let the
SIMD lowering pass split the sample_mask source as a regular
per-channel source, otherwise we would have to introduce some sort of
per-instruction source query or use fs_inst::header_size for the
lowering pass to be able to find out whether some source is
header-like, and leave the source untouched in that case.

As a bonus this achieves the same purpose as the previous code without
making use of the SET_OMASK pseudo-instruction, which will be removed
in a future commit.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Move up Gen6 no16 check to emit_fb_writes().
Francisco Jerez [Wed, 15 Jul 2015 15:50:59 +0000 (18:50 +0300)]
i965/fs: Move up Gen6 no16 check to emit_fb_writes().

And update the comment.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
9 years agoi965/fs: Move up prog_data->uses_omask assignment up to brw_codegen_wm_prog().
Francisco Jerez [Wed, 15 Jul 2015 15:49:55 +0000 (18:49 +0300)]
i965/fs: Move up prog_data->uses_omask assignment up to brw_codegen_wm_prog().

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>