bugzilla-daemon [Thu, 26 Mar 2020 16:57:47 +0000 (16:57 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 16:52:54 +0000 (16:52 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 15:15:06 +0000 (15:15 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 15:15:06 +0000 (15:15 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
bugzilla-daemon [Thu, 26 Mar 2020 14:56:30 +0000 (14:56 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 14:43:54 +0000 (14:43 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 14:19:40 +0000 (14:19 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 14:14:13 +0000 (14:14 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 14:13:20 +0000 (14:13 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 13:05:49 +0000 (13:05 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 12:59:16 +0000 (12:59 +0000)]
Re: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Staf Verhaegen [Thu, 26 Mar 2020 12:31:38 +0000 (13:31 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Thu, 26 Mar 2020 12:27:06 +0000 (13:27 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Thu, 26 Mar 2020 12:18:53 +0000 (13:18 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 11:23:28 +0000 (11:23 +0000)]
Re: [libre-riscv-dev] [OP-CD] OpenPOWER Foundation "Virtual Coffee" Calls
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 11:12:19 +0000 (11:12 +0000)]
Re: [libre-riscv-dev] test failure when running nmutil tests on GitLab CI
bugzilla-daemon [Thu, 26 Mar 2020 11:10:39 +0000 (11:10 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Thu, 26 Mar 2020 11:02:24 +0000 (11:02 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Tobias Platen [Thu, 26 Mar 2020 10:51:58 +0000 (11:51 +0100)]
Re: [libre-riscv-dev] test failure when running nmutil tests on GitLab CI
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 10:13:05 +0000 (10:13 +0000)]
Re: [libre-riscv-dev] test failure when running nmutil tests on GitLab CI
bugzilla-daemon [Thu, 26 Mar 2020 10:09:26 +0000 (10:09 +0000)]
[libre-riscv-dev] [Bug 266] Allow read-only git clone over https
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 10:07:23 +0000 (10:07 +0000)]
Re: [libre-riscv-dev] nmigen upstream repo moved
Jacob Lifshay [Thu, 26 Mar 2020 08:19:51 +0000 (01:19 -0700)]
[libre-riscv-dev] nmigen upstream repo moved
Jacob Lifshay [Thu, 26 Mar 2020 07:54:02 +0000 (00:54 -0700)]
Re: [libre-riscv-dev] Git mirroring
Jacob Lifshay [Thu, 26 Mar 2020 07:46:44 +0000 (00:46 -0700)]
[libre-riscv-dev] test failure when running nmutil tests on GitLab CI
bugzilla-daemon [Thu, 26 Mar 2020 07:42:14 +0000 (07:42 +0000)]
[libre-riscv-dev] [Bug 266] Allow read-only git clone over https
bugzilla-daemon [Thu, 26 Mar 2020 05:54:13 +0000 (05:54 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 05:47:50 +0000 (05:47 +0000)]
Re: [libre-riscv-dev] Git mirroring
bugzilla-daemon [Thu, 26 Mar 2020 05:40:30 +0000 (05:40 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Jacob Lifshay [Thu, 26 Mar 2020 04:37:08 +0000 (21:37 -0700)]
Re: [libre-riscv-dev] Git mirroring
Jacob Lifshay [Thu, 26 Mar 2020 04:35:35 +0000 (21:35 -0700)]
Re: [libre-riscv-dev] Git mirroring
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 04:14:12 +0000 (04:14 +0000)]
Re: [libre-riscv-dev] Setup automation scripts
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 04:10:41 +0000 (04:10 +0000)]
Re: [libre-riscv-dev] [OP-CD] OpenPOWER Foundation "Virtual Coffee" Calls
Luke Kenneth Casson Leighton [Thu, 26 Mar 2020 04:08:18 +0000 (04:08 +0000)]
Re: [libre-riscv-dev] Git mirroring
Jacob Lifshay [Thu, 26 Mar 2020 02:15:56 +0000 (19:15 -0700)]
[libre-riscv-dev] Git mirroring
bugzilla-daemon [Wed, 25 Mar 2020 22:15:28 +0000 (22:15 +0000)]
[libre-riscv-dev] [Bug 266] Allow read-only git clone over https
bugzilla-daemon [Wed, 25 Mar 2020 22:12:49 +0000 (22:12 +0000)]
[libre-riscv-dev] [Bug 266] New: Allow read-only git clone over https
bugzilla-daemon [Wed, 25 Mar 2020 21:20:35 +0000 (21:20 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Wed, 25 Mar 2020 20:03:28 +0000 (20:03 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Wed, 25 Mar 2020 19:58:30 +0000 (19:58 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Wed, 25 Mar 2020 19:43:24 +0000 (19:43 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Jacob Lifshay [Wed, 25 Mar 2020 17:49:02 +0000 (10:49 -0700)]
Re: [libre-riscv-dev] cache SRAM organisation
bugzilla-daemon [Wed, 25 Mar 2020 17:29:51 +0000 (17:29 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Wed, 25 Mar 2020 17:27:03 +0000 (17:27 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Wed, 25 Mar 2020 17:17:09 +0000 (17:17 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Cole Poirier [Wed, 25 Mar 2020 17:03:16 +0000 (10:03 -0700)]
Re: [libre-riscv-dev] nmutil failing tests due to attribute errors
Cole Poirier [Wed, 25 Mar 2020 16:22:55 +0000 (09:22 -0700)]
Re: [libre-riscv-dev] Setup automation scripts
bugzilla-daemon [Wed, 25 Mar 2020 16:21:08 +0000 (16:21 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Luke Kenneth Casson Leighton [Wed, 25 Mar 2020 16:18:27 +0000 (16:18 +0000)]
Re: [libre-riscv-dev] Setup automation scripts
Luke Kenneth Casson Leighton [Wed, 25 Mar 2020 16:13:19 +0000 (16:13 +0000)]
Re: [libre-riscv-dev] nmutil failing tests due to attribute errors
Cole Poirier [Wed, 25 Mar 2020 16:04:43 +0000 (09:04 -0700)]
[libre-riscv-dev] Setup automation scripts
Cole Poirier [Wed, 25 Mar 2020 16:00:32 +0000 (09:00 -0700)]
[libre-riscv-dev] nmutil failing tests due to attribute errors
Luke Kenneth Casson Leighton [Wed, 25 Mar 2020 15:53:02 +0000 (15:53 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Wed, 25 Mar 2020 13:46:38 +0000 (14:46 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
bugzilla-daemon [Wed, 25 Mar 2020 13:07:22 +0000 (13:07 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 25 Mar 2020 12:49:36 +0000 (12:49 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Luke Kenneth Casson Leighton [Wed, 25 Mar 2020 12:33:24 +0000 (12:33 +0000)]
Re: [libre-riscv-dev] cache SRAM organisation
Staf Verhaegen [Wed, 25 Mar 2020 10:54:20 +0000 (11:54 +0100)]
Re: [libre-riscv-dev] cache SRAM organisation
Cole Poirier [Tue, 24 Mar 2020 22:35:40 +0000 (15:35 -0700)]
Re: [libre-riscv-dev] [OP-CD] OpenPOWER Foundation "Virtual Coffee" Calls
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 22:33:55 +0000 (22:33 +0000)]
Re: [libre-riscv-dev] Git repository access
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 22:32:52 +0000 (22:32 +0000)]
[libre-riscv-dev] cache SRAM organisation
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 22:28:51 +0000 (22:28 +0000)]
Re: [libre-riscv-dev] [OP-CD] OpenPOWER Foundation "Virtual Coffee" Calls
Jacob Lifshay [Tue, 24 Mar 2020 22:21:59 +0000 (15:21 -0700)]
[libre-riscv-dev] Fwd: [OpenPOWER-HDL-Cores] OpenPOWER Foundation "Virtual Coffee" Calls
bugzilla-daemon [Tue, 24 Mar 2020 20:27:37 +0000 (20:27 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Cole Poirier [Tue, 24 Mar 2020 20:25:17 +0000 (13:25 -0700)]
Re: [libre-riscv-dev] Git repository access
bugzilla-daemon [Tue, 24 Mar 2020 20:19:12 +0000 (20:19 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 20:12:12 +0000 (20:12 +0000)]
Re: [libre-riscv-dev] Status on Our RISCV Implementation
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 20:11:07 +0000 (20:11 +0000)]
Re: [libre-riscv-dev] Git repository access
Cole Poirier [Tue, 24 Mar 2020 18:56:06 +0000 (11:56 -0700)]
[libre-riscv-dev] Git repository access
bugzilla-daemon [Tue, 24 Mar 2020 18:00:58 +0000 (18:00 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Jacob Lifshay [Tue, 24 Mar 2020 17:44:05 +0000 (10:44 -0700)]
Re: [libre-riscv-dev] Status on Our RISCV Implementation
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 16:05:16 +0000 (16:05 +0000)]
[libre-riscv-dev] Fwd: multi-way LOAD/STORE buffers and misalignment
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 16:00:38 +0000 (16:00 +0000)]
Re: [libre-riscv-dev] ieee.org
Immanuel, Yehowshua U [Tue, 24 Mar 2020 14:44:40 +0000 (14:44 +0000)]
Re: [libre-riscv-dev] ieee.org
bugzilla-daemon [Tue, 24 Mar 2020 14:24:22 +0000 (14:24 +0000)]
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed
bugzilla-daemon [Tue, 24 Mar 2020 14:22:08 +0000 (14:22 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 14:06:31 +0000 (14:06 +0000)]
[libre-riscv-dev] ieee.org
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 13:58:20 +0000 (13:58 +0000)]
Re: [libre-riscv-dev] Status on Our RISCV Implementation
bugzilla-daemon [Tue, 24 Mar 2020 13:55:22 +0000 (13:55 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Immanuel, Yehowshua U [Tue, 24 Mar 2020 13:11:27 +0000 (13:11 +0000)]
Re: [libre-riscv-dev] Status on Our RISCV Implementation
Jean-Paul Chaput [Tue, 24 Mar 2020 13:08:33 +0000 (14:08 +0100)]
Re: [libre-riscv-dev] Advanced Topics on RISCV
Immanuel, Yehowshua U [Tue, 24 Mar 2020 13:00:41 +0000 (13:00 +0000)]
Re: [libre-riscv-dev] Advanced Topics on RISCV
Immanuel, Yehowshua U [Tue, 24 Mar 2020 12:58:29 +0000 (12:58 +0000)]
Re: [libre-riscv-dev] Advanced Topics on RISCV
Jean-Paul Chaput [Tue, 24 Mar 2020 12:23:36 +0000 (13:23 +0100)]
Re: [libre-riscv-dev] Advanced Topics on RISCV
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 12:07:31 +0000 (12:07 +0000)]
Re: [libre-riscv-dev] Status on Our RISCV Implementation
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 12:06:28 +0000 (12:06 +0000)]
Re: [libre-riscv-dev] Advanced Topics on RISCV
bugzilla-daemon [Tue, 24 Mar 2020 11:54:17 +0000 (11:54 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
Immanuel, Yehowshua U [Tue, 24 Mar 2020 11:51:56 +0000 (11:51 +0000)]
[libre-riscv-dev] Advanced Topics on RISCV
Immanuel, Yehowshua U [Tue, 24 Mar 2020 11:39:41 +0000 (11:39 +0000)]
[libre-riscv-dev] Status on Our RISCV Implementation
bugzilla-daemon [Tue, 24 Mar 2020 11:16:58 +0000 (11:16 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Tue, 24 Mar 2020 10:50:57 +0000 (10:50 +0000)]
[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed
Luke Kenneth Casson Leighton [Tue, 24 Mar 2020 10:48:55 +0000 (10:48 +0000)]
Re: [libre-riscv-dev] Next tasks for the Libre-SOC
Tobias Platen [Tue, 24 Mar 2020 09:23:18 +0000 (10:23 +0100)]
[libre-riscv-dev] Next tasks for the Libre-SOC
bugzilla-daemon [Tue, 24 Mar 2020 08:50:51 +0000 (08:50 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Tue, 24 Mar 2020 06:14:55 +0000 (06:14 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Tue, 24 Mar 2020 01:49:41 +0000 (01:49 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Tue, 24 Mar 2020 01:28:01 +0000 (01:28 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Mon, 23 Mar 2020 21:28:58 +0000 (21:28 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
bugzilla-daemon [Mon, 23 Mar 2020 20:12:13 +0000 (20:12 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Luke Kenneth Casson Leighton [Mon, 23 Mar 2020 16:21:03 +0000 (16:21 +0000)]
[libre-riscv-dev] write-up and diagrams for components in the 6600 scoreboard engine
projects / libre-riscv-dev.git / log