Improve comments for xilinx_dsp_CREG

Fix comment

Restore optimisation for sigM.empty()

Retry on fixing TODOs

Revert "Fix TODOs"

This reverts commit 8674a6c68d563908014d16671567459499c6dc99.

More comments, cleanup

Fix TODOs

Consistency

Add comments for xilinx_dsp

Fix typo in check_label()

Merge branch 'master' into eddie/abc_to_abc9

Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`

Remove DSP48E1 from *_cells_xtra.v

Fix xilinx_dsp for unsigned extensions

Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again

Add Const::{begin,end,empty}()

Rename abc_* names/attributes to more precisely be abc9_*

Panic over. Model was elsewhere. Re-arrange for consistency

Oops

Ohmilord this wasn't added all this time!?!

Add -async2sync to help text as per @daveshah1

Fixes for MSVC build

FF should be initialized to 0

Split mux tests per type

Split latch check

Add missing latch mapping

split rest od ff's

Separate check for ff's types

Cleaned tests

Remove not needed tests

Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix

Cleanup and formating

split latches into separate checks

check muxes per type

check ff's separately

Cleanup top modules and not used defines

remove alu test

Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic

Check latches type one by one

Removed top module where not needed

Test muxes synth one by one

Cleaned verilog code from not used defines

Check for MULT18X18D, since that is working now

Check flops one by one

Removed alu and div_mod tests as agreed

Use `sat -tempinduct` and comments for why equiv_opt not sufficient

Restore part of doc

Disable equiv check for ice40 latches

Add new -async2sync option

Use equiv_opt -async2sync for xilinx

Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"

This reverts commit a39505e329cc05dbd4ad624a1cf0f6caf664fd9a.

Revert "Update doc for equiv_opt"

This reverts commit a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.

Change smtbmc "Warmup failed" status to "PREUNSAT"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update ABC to git rev 623b5e8

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Bump version

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1419 from YosysHQ/eddie/lazy_derive

module->derive() to be lazy and not touch ast if already derived

Merge pull request #1422 from YosysHQ/eddie/aigmap_select

Add -select option to aigmap

Merge pull request #1429 from YosysHQ/clifford/checkmapped

Add "check -mapped"

Add "check -allow-tbuf"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

frontends/ast: code style

Signed-off-by: David Shah <dave@ds0.me>

sv: Improve tests

Signed-off-by: David Shah <dave@ds0.me>

sv: Fix typedefs in blocks

Signed-off-by: David Shah <dave@ds0.me>

sv: Disambiguate interface ports

Signed-off-by: David Shah <dave@ds0.me>

Update CHANGELOG and README

Signed-off-by: David Shah <dave@ds0.me>

sv: Add test scripts for typedefs

Signed-off-by: David Shah <dave@ds0.me>

sv: Fix memories of typedefs

Signed-off-by: David Shah <dave@ds0.me>

sv: Add %expect

Signed-off-by: David Shah <dave@ds0.me>

sv: Add support for memories of a typedef

Signed-off-by: David Shah <dave@ds0.me>

sv: Add support for memory typedefs

Signed-off-by: David Shah <dave@ds0.me>

sv: Fix typedefs in packages

Signed-off-by: David Shah <dave@ds0.me>

sv: Fix typedef parameters

Signed-off-by: David Shah <dave@ds0.me>

sv: Switch parser to glr, prep for typedef

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16

ecp5: Add support for mapping 36-bit wide PDP BRAMs

Fix broken CI, check reset even for constants, trim rstmux

Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire

RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"

Fix test

Merge branch 'eddie/fix_sat_init' into eddie/fix1427

Update test

Refactor peepopt_dffmux and be sensitive to \init when trimming

Add test

log_dump() to support State enum

Be mindful that sigmap(wire) could have dupes when checking \init

Add test that is expecting to fail

Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf

Extend test with renaming cells with prefix too

Merge pull request #1428 from YosysHQ/clifford/fixbtor

Fix btor back-end to use "state" instead of "input" for undef init bits

Add "check -mapped"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix btor back-end to use "state" instead of "input" for undef init bits

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1426 from YosysHQ/mmicko/fix_environ

Define environ, fixes #1424

Define environ, fixes #1424

ecp5: Fix shuffle_enable port

Signed-off-by: David Shah <dave@ds0.me>

ecp5: Add support for mapping 36-bit wide PDP BRAMs

Signed-off-by: David Shah <dave@ds0.me>

run-test.sh Move $x at end of line.

Merge branch 'master' into SergeyDegtyar/efinix

Merge branch 'master' into SergeyDegtyar/anlogic

run-test.sh Move $x at end of line.

equiv_opt with -assert

Update resource count for alu.ys

Add test

techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias