whitequark [Tue, 24 Sep 2019 14:54:22 +0000 (14:54 +0000)]
build.plat: strip internal attributes from Verilog output.
Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.
This still leaves the (*init*) attribute. See #220 for details.
whitequark [Tue, 24 Sep 2019 14:14:45 +0000 (14:14 +0000)]
build.plat,lib.cdc,vendor: unify platform related diagnostics. NFC.
whitequark [Tue, 24 Sep 2019 12:30:02 +0000 (12:30 +0000)]
lib.cdc: specify maximum input delay in seconds.
Since we use hertz elsewhere, this provides for easy conversions.
Also, cast the delay to string before applying it in xilinx_7series,
to avoid stripping the fractional digits.
Closes #234.
whitequark [Tue, 24 Sep 2019 12:22:29 +0000 (12:22 +0000)]
vendor.xilinx_spartan_3_6: explain why ASYNC_REG is used. NFC.
Kate Temkin [Tue, 24 Sep 2019 06:55:00 +0000 (00:55 -0600)]
vendor.lattice_ecp5: correct a typo in tristate buffer generation
Darrell Harmon [Tue, 24 Sep 2019 00:47:54 +0000 (18:47 -0600)]
vendor.xilinx_7series: apply false path / max delay constraints.
whitequark [Mon, 23 Sep 2019 20:27:42 +0000 (20:27 +0000)]
vendor.xilinx_7series: simplify. NFC.
whitequark [Mon, 23 Sep 2019 20:15:29 +0000 (20:15 +0000)]
vendor.xilinx_7series: override reset synchronizer.
whitequark [Mon, 23 Sep 2019 19:38:21 +0000 (19:38 +0000)]
lib.cdc: add diagnostic checks for synchronization stage count.
whitequark [Mon, 23 Sep 2019 19:31:23 +0000 (19:31 +0000)]
lib.cdc: expand ResetSynchronizer documentation.
Loosely based on work by @Wren6991.
whitequark [Mon, 23 Sep 2019 16:42:44 +0000 (16:42 +0000)]
lib.cdc: avoid modifying synchronizers in their elaborate() method.
Darrell Harmon [Mon, 23 Sep 2019 16:28:15 +0000 (10:28 -0600)]
vendor.xilinx_spartan_3_6: override reset synchronizer.
whitequark [Mon, 23 Sep 2019 16:01:59 +0000 (16:01 +0000)]
README: add a section on migrating from Migen.
whitequark [Mon, 23 Sep 2019 14:17:44 +0000 (14:17 +0000)]
lib.cdc: MultiReg→FFSynchronizer.
Fixes #229.
whitequark [Mon, 23 Sep 2019 13:39:31 +0000 (13:39 +0000)]
hdl.ast: cast Mux() selector to bool if it is not a 1-bit value.
Fixes #232.
whitequark [Mon, 23 Sep 2019 12:48:02 +0000 (12:48 +0000)]
back.rtlil: give predictable names to anonymous subfragments.
This is required for applying constraints to clocks in anonymous
subfragments in build.plat.
whitequark [Mon, 23 Sep 2019 12:27:59 +0000 (12:27 +0000)]
lib.fifo: handle depth=0, elaborating to a dummy FIFO with no logic.
whitequark [Mon, 23 Sep 2019 11:18:01 +0000 (11:18 +0000)]
hdl.mem,lib.fifo: use keyword-only arguments for memory geometry.
Fixes #230.
whitequark [Mon, 23 Sep 2019 11:16:29 +0000 (11:16 +0000)]
hdl.mem: simplify. NFC.
whitequark [Mon, 23 Sep 2019 11:08:43 +0000 (11:08 +0000)]
hdl.ast: make Signal(name=) a keyword-only argument.
Almost no code would specify Signal(_, name) as a positional argument
on purpose, but forgetting parens and accidentally placing signedness
into the name position is so common that we had a test for it.
whitequark [Mon, 23 Sep 2019 11:03:50 +0000 (11:03 +0000)]
lib.fifo: change FIFOInterface() diagnostics to follow Memory().
whitequark [Mon, 23 Sep 2019 10:57:30 +0000 (10:57 +0000)]
lib.fifo: round up AsyncFIFO{,Buffered} depth to lowest valid value.
Unless exact_depth=True is specified.
The logic introduced in this commit is idempotent: that is, if one
uses the depth of one AsyncFIFOBuffered in the constructor of another
AsyncFIFOBuffered, they will end up with the same depth. More naive
logic would result in an unbounded, quadratic growth with each such
step.
Fixes #219.
whitequark [Mon, 23 Sep 2019 08:45:58 +0000 (08:45 +0000)]
lib.fifo: make simulation read() and write() functions compat-only.
These functions were originally changed in
3ed51938, in an attempt
to make them take one cycle instead of two. However, this does not
actually work because of drawbacks of the simulator interface.
Avoid committing to any specific implementation for now, and instead
make them compat-only extensions.
whitequark [Sun, 22 Sep 2019 17:23:32 +0000 (17:23 +0000)]
hdl.rec: fix using Enum subclass as shape if direction is specified.
Also improves error messages.
Fixes #224.
whitequark [Sun, 22 Sep 2019 15:16:36 +0000 (15:16 +0000)]
hdl.rec: allow using Enum subclass as shape.
Fixes #223.
whitequark [Sun, 22 Sep 2019 11:56:03 +0000 (11:56 +0000)]
lib.fifo: add more compatibility shims.
Some downstream code was broken by renames in
da4b810f.
whitequark [Sun, 22 Sep 2019 07:18:37 +0000 (07:18 +0000)]
vendor.lattice_ice40: fix required tool list for iCECube2. NFC.
whitequark [Sun, 22 Sep 2019 07:17:12 +0000 (07:17 +0000)]
vendor.lattice_ecp5: simplify quoting. NFC.
See commit
ee1ad2da.
whitequark [Sun, 22 Sep 2019 06:57:28 +0000 (06:57 +0000)]
build.plat: restrict design names to alphanumeric to avoid quoting issues.
whitequark [Sat, 21 Sep 2019 14:27:35 +0000 (14:27 +0000)]
vendor.lattice_ice40: add iCECube support.
This also makes some iCE40 and ECP5 overrides more consistent.
whitequark [Sat, 21 Sep 2019 14:12:29 +0000 (14:12 +0000)]
build.res: simplify clock constraints.
Before this commit, it was possible to set and get clock constraints
placed on Pin objects. This was not a very good implementation, since
it relied on matching the identity of the provided Pin object to
a previously requested one. The only reason it worked like that is
deficiencies in nextpnr.
Since then, nextpnr has been fixed to allow setting constraints on
arbitrary nets. Correspondingly, backends that are using Synplify
were changed to use [get_nets] instead of [get_ports] in SDC files.
However, in some situations, Synplify does not allow specifying
ports in [get_nets]. (In fact, nextpnr had a similar problem, but
it has also been fixed.)
The simplest way to address this is to refer to the interior net
(after the input buffer), which always works. The only downside
of this is that requesting a clock as a raw pin using
platform.request("clk", dir="-")
and directly applying a constraint to it could fail in some cases.
This is not a significant issue.
whitequark [Sat, 21 Sep 2019 12:23:53 +0000 (12:23 +0000)]
build.plat: NMIGEN_<toolchain>_env→NMIGEN_ENV_<toolchain>
This is more consistent with other environment variables nMigen uses.
whitequark [Sat, 21 Sep 2019 06:53:39 +0000 (06:53 +0000)]
lib.fifo: update docs. NFC.
whitequark [Sat, 21 Sep 2019 06:53:13 +0000 (06:53 +0000)]
hdl.ast: update docs. NFC.
whitequark [Sat, 21 Sep 2019 06:09:30 +0000 (06:09 +0000)]
lib.fifo: simplify. NFC.
whitequark [Fri, 20 Sep 2019 19:50:43 +0000 (19:50 +0000)]
lib.fifo: fix doc typo. NFC.
whitequark [Fri, 20 Sep 2019 19:38:42 +0000 (19:38 +0000)]
lib.fifo: work around Yosys issue with handling of \TRANSPARENT.
Because of YosysHQ/yosys#1390, using a transparent port in AsyncFIFO,
instead of being a no-op (as the semantics of \TRANSPARENT would
require it to be in this case), results in a failure to infer BRAM.
This can be easily avoided by using a non-transparent port instead,
which produces the desirable result with Yosys. It does not affect
the semantics on Xilinx platforms, since the interaction between
the two ports in case of address collision is undefined in either
transparent (WRITE_FIRST) or non-transparent (READ_FIRST) case, and
the data out of the write port is not used at all.
Fixes #172.
whitequark [Fri, 20 Sep 2019 19:36:19 +0000 (19:36 +0000)]
hdl.mem: use 1 as reset value for ReadPort.en.
This is necessary for consistency, since for transparent read ports,
we currently do not support .en at all (it is fixed at 1) due to
YosysHQ/yosys#760. Before this commit, changing port transparency
would require adding or removing an assignment to .en, which is
confusing and error-prone.
Also, most read ports are always enabled, so this behavior is also
convenient.
whitequark [Fri, 20 Sep 2019 16:11:01 +0000 (16:11 +0000)]
vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.
Fixes #88.
whitequark [Fri, 20 Sep 2019 15:35:55 +0000 (15:35 +0000)]
hdl.ast: rename `nbits` to `width`.
Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.
This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)
Fixes #210.
Darrell Harmon [Fri, 20 Sep 2019 15:13:27 +0000 (09:13 -0600)]
vendor.xilinx_{7series,spartan3_6}: specialize MultiReg.
Vivado/ISE would otherwise infer an SRL16 from a MultiReg in some cases.
Emily [Fri, 20 Sep 2019 13:48:08 +0000 (14:48 +0100)]
setup: improve repository detection.
Emily [Fri, 20 Sep 2019 13:48:03 +0000 (14:48 +0100)]
setup: add setuptools dependency.
whitequark [Fri, 20 Sep 2019 11:53:05 +0000 (11:53 +0000)]
test.test_lib_fifo: fix typo.
whitequark [Fri, 20 Sep 2019 10:12:59 +0000 (10:12 +0000)]
back.pysim: fix simulation of Value.xor().
whitequark [Mon, 16 Sep 2019 18:59:28 +0000 (18:59 +0000)]
hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.
Fixes #207.
whitequark [Sat, 14 Sep 2019 21:06:12 +0000 (21:06 +0000)]
hdl.ast: add Value.matches(), accepting same language as Case().
Fixes #202.
whitequark [Sat, 14 Sep 2019 20:46:10 +0000 (20:46 +0000)]
hdl.dsl: improve error messages for Case().
whitequark [Fri, 13 Sep 2019 14:28:43 +0000 (14:28 +0000)]
hdl.ast: add Value.xor, mapping to $reduce_xor.
Fixes #147.
whitequark [Fri, 13 Sep 2019 13:14:52 +0000 (13:14 +0000)]
hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.
Refs #147.
whitequark [Thu, 12 Sep 2019 20:01:28 +0000 (20:01 +0000)]
lib.fifo: adjust for new CDC primitive conventions.
Fixes #97.
whitequark [Thu, 12 Sep 2019 19:51:01 +0000 (19:51 +0000)]
lib.fifo: adjust properties to have consistent naming.
whitequark [Thu, 12 Sep 2019 21:56:48 +0000 (21:56 +0000)]
build.plat: bypass tool detection if NMIGEN_*_env is set.
It's not practical to detect tools within the toolchain environment
for various reasons, so just assume the tools are there if the user
says they are.
Before this commit, the tools would be searched outside the toolchain
environment, which of course would always fail for Vivado, ISE, etc.
whitequark [Thu, 12 Sep 2019 21:49:08 +0000 (21:49 +0000)]
vendor.xilinx_7series: Vivado requires bash on *nix as well.
whitequark [Thu, 12 Sep 2019 20:03:48 +0000 (20:03 +0000)]
hdl.mem: use keyword-only arguments as appropriate.
whitequark [Thu, 12 Sep 2019 19:36:45 +0000 (19:36 +0000)]
lib.fifo: make fwft a keyword-only argument.
Because it accepts a boolean.
whitequark [Thu, 12 Sep 2019 19:14:56 +0000 (19:14 +0000)]
lib.fifo: remove SyncFIFO.replace.
This obscure functionality was likely only ever used in old MiSoC
code, and doesn't justify the added complexity. It was also not
provided (and could not be reasonably provided) in SyncFIFOBuffered,
which made its utility extremely marginal.
whitequark [Thu, 12 Sep 2019 14:33:38 +0000 (14:33 +0000)]
README: update Yosys version requirement.
whitequark [Thu, 12 Sep 2019 13:54:48 +0000 (13:54 +0000)]
lib.cdc: make domain properties private.
It is not correct to access domain properties from user code, because
it will not match the reality if DomainRenamer has been applied to
the module.
whitequark [Thu, 12 Sep 2019 13:51:18 +0000 (13:51 +0000)]
lib.io: style. NFC.
whitequark [Thu, 12 Sep 2019 13:48:45 +0000 (13:48 +0000)]
lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions.
Refs #97.
whitequark [Thu, 12 Sep 2019 13:48:24 +0000 (13:48 +0000)]
lib.cdc: adjust MultiReg for new CDC primitive conventions.
Refs #97.
whitequark [Wed, 11 Sep 2019 23:35:43 +0000 (23:35 +0000)]
build.plat,vendor: allow clock constraints on arbitrary signals.
Currently only done for Synopsys based toolchains (i.e. not nextpnr).
Refs #88.
whitequark [Wed, 11 Sep 2019 23:14:00 +0000 (23:14 +0000)]
back: return name map from convert_fragment().
whitequark [Tue, 10 Sep 2019 07:25:28 +0000 (07:25 +0000)]
hdl.ast: warn if reset value is truncated.
Fixes #183.
Darrell Harmon [Tue, 10 Sep 2019 03:32:36 +0000 (21:32 -0600)]
vendor.lattice_ecp5: pass ecppack_opts to ecppack.
whitequark [Sun, 8 Sep 2019 23:55:05 +0000 (23:55 +0000)]
hdl.ast: check type of Sample(domain=...).
Fixes #199.
whitequark [Sun, 8 Sep 2019 12:24:18 +0000 (12:24 +0000)]
hdl.dsl: add Default(), an alias for Case() with no arguments.
Fixes #197.
whitequark [Sun, 8 Sep 2019 12:19:13 +0000 (12:19 +0000)]
hdl.mem,lib,examples: use Signal.range().
whitequark [Sun, 8 Sep 2019 12:10:31 +0000 (12:10 +0000)]
hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...).
Fixes #196.
whitequark [Fri, 6 Sep 2019 06:47:27 +0000 (06:47 +0000)]
Remove nmigen.lib from prelude.
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
whitequark [Fri, 6 Sep 2019 05:30:22 +0000 (05:30 +0000)]
Fix .gitignore.
whitequark [Fri, 6 Sep 2019 05:11:41 +0000 (05:11 +0000)]
setup: replace versioneer with setuptools_scm.
Has the same problems with git-archive but is much less invasive.
whitequark [Tue, 3 Sep 2019 01:32:24 +0000 (01:32 +0000)]
hdl.ast,back.rtlil: implement Cover.
Fixes #194.
whitequark [Sat, 31 Aug 2019 22:05:48 +0000 (22:05 +0000)]
hdl.cd: add negedge clock domains.
Fixes #185.
Emily [Fri, 30 Aug 2019 23:27:22 +0000 (00:27 +0100)]
_toolchain,build.plat,vendor.*: add required_tools list and checks.
whitequark [Fri, 30 Aug 2019 10:10:13 +0000 (10:10 +0000)]
vendor.lattice_ecp5: drive GSR synchronous to user clock by default.
Fixes #167.
whitequark [Fri, 30 Aug 2019 08:35:52 +0000 (08:35 +0000)]
build.dsl: allow both str and int resource attributes.
Emily [Wed, 28 Aug 2019 11:52:16 +0000 (12:52 +0100)]
test.tools: use _toolchain.get_tool.
whitequark [Wed, 28 Aug 2019 11:32:18 +0000 (11:32 +0000)]
_toolchain: new module, for injecting dependencies in e.g. Nix.
whitequark [Mon, 26 Aug 2019 09:35:37 +0000 (09:35 +0000)]
back.verilog: bump Yosys version requirement to 0.9.
Fixes #55.
whitequark [Sun, 25 Aug 2019 08:07:00 +0000 (08:07 +0000)]
vendor.lattice_ecp5: revert default toolchain to Trellis.
This was unintentionally changed in
7fc1058e.
whitequark [Fri, 23 Aug 2019 08:53:48 +0000 (08:53 +0000)]
back.pysim: implement sim.add_clock(if_exists=True).
whitequark [Fri, 23 Aug 2019 08:37:59 +0000 (08:37 +0000)]
back.pysim: don't crash when trying to drive a nonexistent domain clock.
whitequark [Fri, 23 Aug 2019 01:10:51 +0000 (01:10 +0000)]
build.run: add BuildPlan.digest(), useful for caching.
whitequark [Tue, 20 Aug 2019 12:27:19 +0000 (12:27 +0000)]
vendor.lattice_ecp5: add Diamond support.
whitequark [Thu, 22 Aug 2019 20:54:42 +0000 (20:54 +0000)]
vendor: eliminate unnecessary LUT instantiation.
Fixes #165.
Reto Kramer [Thu, 22 Aug 2019 19:28:40 +0000 (12:28 -0700)]
examples/basic/uart: document `divisor` parameter.
whitequark [Thu, 22 Aug 2019 04:42:30 +0000 (04:42 +0000)]
back.rtlil: print real parameters with maximum precision.
Darrell Harmon [Thu, 22 Aug 2019 04:13:05 +0000 (22:13 -0600)]
back.rtlil: add support for real (float) parameters on Instances.
Required for Xilinx MMCME2_BASE, etc.
Darrell Harmon [Wed, 21 Aug 2019 22:25:55 +0000 (16:25 -0600)]
vendor.xilinx_series7: use STARTUPE2, not STARTUPE3.
STARTUPE3 is for Ultrascale.
whitequark [Wed, 21 Aug 2019 21:32:12 +0000 (21:32 +0000)]
vendor.lattice_ice40: remove `--placer heap` default option.
It is not the place of nMigen to decide on this default, since both
SA and HeAP have valid uses that are not covered by the other.
whitequark [Wed, 21 Aug 2019 21:31:19 +0000 (21:31 +0000)]
vendor: style. NFC.
whitequark [Wed, 21 Aug 2019 21:02:05 +0000 (21:02 +0000)]
build.plat: remove TemplatedPlatform.unix_interpreter.
Vendor toolchains generally require far more workarounds than this,
and we already have a perfectly fine way of overriding templates.
whitequark [Wed, 21 Aug 2019 03:28:48 +0000 (03:28 +0000)]
back.pysim: allow coroutines as processes.
This is a somewhat obscure use case, but it is possible to use async
functions with pysim by carefully using @asyncio.coroutine. That is,
async functions can call back into pysim if they are declared in
a specific way:
@asyncio.coroutine
def do_something(self, value):
yield self.reg.eq(value)
which may then be called from elsewhere with:
async def test_case(self):
await do_something(0x1234)
This approach is unfortunately limited in that async functions
cannot yield directly. It should likely be improved by using async
generators, but supporting coroutines in pysim is unobtrustive and
allows existing code that made use of this feature in oMigen to work.
William D. Jones [Mon, 5 Aug 2019 01:52:23 +0000 (21:52 -0400)]
test.test_examples: Convert pathlib-specific class to string.
subprocess.check_call iterates over its arguments to check for spaces
and tabs, and on Windows, the pathlib-specific WindowsPath is not
iterable.
whitequark [Mon, 19 Aug 2019 23:28:33 +0000 (23:28 +0000)]
back.verilog: parse output of `yosys -V`.
See #55.
whitequark [Mon, 19 Aug 2019 23:14:41 +0000 (23:14 +0000)]
Fix nmigen.__version__ to work on git-archive artifacts.
Fixes #137.
whitequark [Mon, 19 Aug 2019 22:32:50 +0000 (22:32 +0000)]
build.plat, hdl.ir: coordinate missing domain creation.
Platform.prepare() was completely broken after addition of local
clock domains, and only really worked before by a series of
accidents because there was a circular dependency between creation
of missing domains, fragment preparation, and insertion of pin
subfragments.
This commit untangles the dependency by adding a separate public
method Fragment.create_missing_domains(), used in build.plat.
It also makes DomainCollector consider both used and defined domains,
such that it will work on fragments before domain propagation, since
create_missing_domains() can be called by user code before prepare().
The fragment driving missing clock domain is not flattened anymore,
because flattening does not work well combined with local domains.
whitequark [Mon, 19 Aug 2019 21:46:44 +0000 (21:46 +0000)]
vendor.lattice_ice40: use a local clock domain in create_missing_domain().