yosys.git
3 years agosv: extended support for integer types
Zachary Snow [Sun, 28 Feb 2021 20:49:16 +0000 (15:49 -0500)]
sv: extended support for integer types

- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths

3 years agoUpdate issue_template.md
Claire Xen [Sat, 27 Feb 2021 15:52:30 +0000 (16:52 +0100)]
Update issue_template.md

3 years agoAdd tests for $countbits
Michael Singer [Thu, 25 Feb 2021 00:21:36 +0000 (01:21 +0100)]
Add tests for $countbits

3 years agoImplement $countones, $isunknown and $onehot{,0}
Michael Singer [Tue, 23 Feb 2021 00:19:06 +0000 (01:19 +0100)]
Implement $countones, $isunknown and $onehot{,0}

3 years agoImplement $countbits function
Michael Singer [Mon, 22 Feb 2021 23:55:55 +0000 (00:55 +0100)]
Implement $countbits function

3 years agoExtend simplify() recursion warning
Zachary Snow [Thu, 25 Feb 2021 21:02:55 +0000 (16:02 -0500)]
Extend simplify() recursion warning

3 years agoBump version
Marcelina Kościelnicka [Thu, 25 Feb 2021 23:24:33 +0000 (00:24 +0100)]
Bump version

3 years agoMerge pull request #2554 from hzeller/master
whitequark [Thu, 25 Feb 2021 21:54:16 +0000 (13:54 -0800)]
Merge pull request #2554 from hzeller/master

Fix digit-formatting calculation for small numbers.

3 years agobtor, smt2, smv: Add a hint on how to deal with funny FF types.
Marcelina Kościelnicka [Tue, 23 Feb 2021 11:06:21 +0000 (12:06 +0100)]
btor, smt2, smv: Add a hint on how to deal with funny FF types.

3 years agoFix handling of unique/unique0/priority cases in the frontend.
Marcelina Kościelnicka [Mon, 22 Feb 2021 18:19:42 +0000 (19:19 +0100)]
Fix handling of unique/unique0/priority cases in the frontend.

Basically:

- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)

Fixes #2596.

3 years agoExtend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off...
TimRudy [Wed, 24 Feb 2021 20:48:15 +0000 (15:48 -0500)]
Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566)

3 years agoMerge pull request #2607 from zachjs/logger-error-atexit
whitequark [Wed, 24 Feb 2021 19:12:56 +0000 (19:12 +0000)]
Merge pull request #2607 from zachjs/logger-error-atexit

Fix double-free on unmatched logger error pattern

3 years agoFix double-free on unmatched logger error pattern
Zachary Snow [Wed, 24 Feb 2021 01:39:13 +0000 (20:39 -0500)]
Fix double-free on unmatched logger error pattern

When an expected logger error pattern is unmatched, the logger raises
another (hidden) error. Because of the previous ordering of actions,
`logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()`
twice, causing a double-free.

3 years agoAdd tests for some common techmap files.
Marcelina Kościelnicka [Tue, 23 Feb 2021 20:23:26 +0000 (21:23 +0100)]
Add tests for some common techmap files.

3 years agoFix syntax error in adff2dff.v
Marcelina Kościelnicka [Tue, 23 Feb 2021 11:12:37 +0000 (12:12 +0100)]
Fix syntax error in adff2dff.v

Fixes #2600.

3 years agofrontend: Make helper functions for printing locations.
Marcelina Kościelnicka [Tue, 23 Feb 2021 18:22:53 +0000 (19:22 +0100)]
frontend: Make helper functions for printing locations.

3 years agoMerge pull request #2594 from zachjs/func-arg-width
whitequark [Tue, 23 Feb 2021 21:46:16 +0000 (21:46 +0000)]
Merge pull request #2594 from zachjs/func-arg-width

verilog: fix sizing of constant args for tasks/functions

3 years agoint -> bool
Robert Baruch [Mon, 22 Feb 2021 04:00:31 +0000 (20:00 -0800)]
int -> bool

3 years agoAdds is_wire to SigBit and SigChunk
Robert Baruch [Sat, 20 Feb 2021 19:46:30 +0000 (11:46 -0800)]
Adds is_wire to SigBit and SigChunk

Useful for PYOSYS because Python can't easily check wire against NULL.

3 years agomachxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.
William D. Jones [Sun, 21 Feb 2021 14:14:37 +0000 (09:14 -0500)]
machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.

3 years agomachxo2: Update tribuf test to reflect active-low OE.
William D. Jones [Wed, 10 Feb 2021 23:50:17 +0000 (18:50 -0500)]
machxo2: Update tribuf test to reflect active-low OE.

3 years agomachxo2: Add experimental status to help.
William D. Jones [Mon, 8 Feb 2021 22:31:58 +0000 (17:31 -0500)]
machxo2: Add experimental status to help.

3 years agomachxo2: Add DCCA and DCMA blackbox primitives.
William D. Jones [Mon, 1 Feb 2021 04:57:13 +0000 (23:57 -0500)]
machxo2: Add DCCA and DCMA blackbox primitives.

3 years agomachxo2: Fix reversed interpretation of REG_SD config bits.
William D. Jones [Mon, 1 Feb 2021 00:05:15 +0000 (19:05 -0500)]
machxo2: Fix reversed interpretation of REG_SD config bits.

3 years agomachxo2: Tristate is active-low.
William D. Jones [Sun, 31 Jan 2021 16:33:20 +0000 (11:33 -0500)]
machxo2: Tristate is active-low.

3 years agomachxo2: Fix typos in FACADE_FF sim model.
William D. Jones [Sun, 31 Jan 2021 04:55:00 +0000 (23:55 -0500)]
machxo2: Fix typos in FACADE_FF sim model.

3 years agomachxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.
William D. Jones [Fri, 29 Jan 2021 23:14:13 +0000 (18:14 -0500)]
machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.

3 years agomachxo2: Improve help_mode output in synth_machxo2.
William D. Jones [Sun, 13 Dec 2020 05:34:01 +0000 (00:34 -0500)]
machxo2: Improve help_mode output in synth_machxo2.

3 years agomachxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO...
William D. Jones [Sat, 12 Dec 2020 23:09:52 +0000 (18:09 -0500)]
machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells.

3 years agomachxo2: Add missing OSCH oscillator primitive.
William D. Jones [Tue, 8 Dec 2020 03:29:36 +0000 (22:29 -0500)]
machxo2: Add missing OSCH oscillator primitive.

3 years agomachxo2: Add believed-to-be-correct tribuf test.
William D. Jones [Fri, 27 Nov 2020 03:34:46 +0000 (22:34 -0500)]
machxo2: Add believed-to-be-correct tribuf test.

3 years agomachxo2: Add passing fsm, mux, and shifter tests.
William D. Jones [Fri, 27 Nov 2020 03:30:48 +0000 (22:30 -0500)]
machxo2: Add passing fsm, mux, and shifter tests.

3 years agomachxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.
William D. Jones [Fri, 27 Nov 2020 02:58:20 +0000 (21:58 -0500)]
machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.

3 years agomachxo2: Add -noiopad option to synth_machxo2.
William D. Jones [Fri, 27 Nov 2020 02:23:13 +0000 (21:23 -0500)]
machxo2: Add -noiopad option to synth_machxo2.

3 years agomachxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.
William D. Jones [Fri, 27 Nov 2020 01:18:15 +0000 (20:18 -0500)]
machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.

3 years agomachxo2: Fix cells_sim typo where OFX1 was multiply-driven.
William D. Jones [Thu, 26 Nov 2020 23:47:11 +0000 (18:47 -0500)]
machxo2: Fix cells_sim typo where OFX1 was multiply-driven.

3 years agomachxo2: synth_machxo2 now maps ports to FACADE_IO.
William D. Jones [Thu, 26 Nov 2020 18:39:40 +0000 (13:39 -0500)]
machxo2: synth_machxo2 now maps ports to FACADE_IO.

3 years agomachxo2: Add initial value for Q in FACADE_FF.
William D. Jones [Sat, 21 Nov 2020 23:44:42 +0000 (18:44 -0500)]
machxo2: Add initial value for Q in FACADE_FF.

3 years agomachxo2: Add FACADE_IO simulation model. More comments on models.
William D. Jones [Sat, 21 Nov 2020 16:58:30 +0000 (11:58 -0500)]
machxo2: Add FACADE_IO simulation model. More comments on models.

3 years agomachxo2: Add FACADE_SLICE simulation model.
William D. Jones [Sat, 21 Nov 2020 16:53:30 +0000 (11:53 -0500)]
machxo2: Add FACADE_SLICE simulation model.

3 years agomachxo2: Improve FACADE_FF simulation model.
William D. Jones [Sat, 21 Nov 2020 02:24:39 +0000 (21:24 -0500)]
machxo2: Improve FACADE_FF simulation model.

3 years agomachxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.
William D. Jones [Fri, 20 Nov 2020 23:53:09 +0000 (18:53 -0500)]
machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.

3 years agomachxo2: Add dffe test.
William D. Jones [Fri, 20 Nov 2020 23:16:45 +0000 (18:16 -0500)]
machxo2: Add dffe test.

3 years agomachxo2: Add dff.ys test, fix another cells_map.v typo.
William D. Jones [Tue, 17 Nov 2020 19:35:17 +0000 (14:35 -0500)]
machxo2: Add dff.ys test, fix another cells_map.v typo.

3 years agomachxo2: Fix more oversights in machxo2 models. logic.ys test passes.
William D. Jones [Tue, 17 Nov 2020 19:22:44 +0000 (14:22 -0500)]
machxo2: Fix more oversights in machxo2 models. logic.ys test passes.

3 years agomachxo2: Add test/arch/machxo2 directory (test does not pass).
William D. Jones [Tue, 17 Nov 2020 18:01:57 +0000 (13:01 -0500)]
machxo2: Add test/arch/machxo2 directory (test does not pass).

3 years agomachxo2: Fix typos. test/arch/run-test.sh passes.
William D. Jones [Tue, 17 Nov 2020 17:49:15 +0000 (12:49 -0500)]
machxo2: Fix typos. test/arch/run-test.sh passes.

3 years agomachxo2: Create basic techlibs and synth_machxo2 pass.
William D. Jones [Mon, 16 Nov 2020 20:07:32 +0000 (15:07 -0500)]
machxo2: Create basic techlibs and synth_machxo2 pass.

3 years agofrontend: json: parse negative values
Karol Gugala [Wed, 27 Jan 2021 19:34:00 +0000 (20:34 +0100)]
frontend: json: parse negative values

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
3 years agoassertpmux: Fix crash on unused $pmux output.
Marcelina Kościelnicka [Mon, 22 Feb 2021 21:02:48 +0000 (22:02 +0100)]
assertpmux: Fix crash on unused $pmux output.

Fixes #2595.

3 years agoMerge pull request #2586 from zachjs/tern-recurse
whitequark [Sun, 21 Feb 2021 20:56:04 +0000 (20:56 +0000)]
Merge pull request #2586 from zachjs/tern-recurse

verilog: support recursive functions using ternary expressions

3 years agoMerge pull request #2591 from zachjs/verilog-preproc-unapplied
whitequark [Sun, 21 Feb 2021 20:53:56 +0000 (20:53 +0000)]
Merge pull request #2591 from zachjs/verilog-preproc-unapplied

verilog: error on macro invocations with missing argument lists

3 years agoverilog: fix sizing of constant args for tasks/functions
Zachary Snow [Sun, 21 Feb 2021 19:45:21 +0000 (14:45 -0500)]
verilog: fix sizing of constant args for tasks/functions

- Simplify synthetic localparams for normal calls to update their width
    - This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
    - `eval_const_function` never correctly handled this, but the issue
      was not exposed in the existing tests until the recent change to
      always attempt constant function evaluation when all-const args
      are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases

3 years agoverilog: error on macro invocations with missing argument lists
Zachary Snow [Thu, 18 Feb 2021 17:04:02 +0000 (12:04 -0500)]
verilog: error on macro invocations with missing argument lists

This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.

3 years agoBump version
Yosys Bot [Thu, 18 Feb 2021 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2590 from RobertBaruch/fix_fast_sop_mode
Claire Xen [Wed, 17 Feb 2021 15:30:12 +0000 (16:30 +0100)]
Merge pull request #2590 from RobertBaruch/fix_fast_sop_mode

Fixes command line for abc pass in -fast -sop mode

3 years agoFixes command line for abc pass in -fast -sop mode
Robert Baruch [Wed, 17 Feb 2021 00:34:09 +0000 (16:34 -0800)]
Fixes command line for abc pass in -fast -sop mode

3 years agoBump version
Yosys Bot [Tue, 16 Feb 2021 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2574 from dh73/master
Claire Xen [Mon, 15 Feb 2021 16:49:11 +0000 (17:49 +0100)]
Merge pull request #2574 from dh73/master

Accept disable case for SVA liveness properties.

3 years agoBump version
Yosys Bot [Sat, 13 Feb 2021 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agoverilog: support recursive functions using ternary expressions
Zachary Snow [Fri, 12 Feb 2021 19:25:34 +0000 (14:25 -0500)]
verilog: support recursive functions using ternary expressions

This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.

3 years agoMerge pull request #2585 from YosysHQ/dave/nexus-dotproduct
gatecat [Fri, 12 Feb 2021 12:07:12 +0000 (12:07 +0000)]
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct

nexus: Add MULTADDSUB9X9WIDE sim model

3 years agoGanulate Verific support
Miodrag Milanovic [Fri, 12 Feb 2021 09:08:43 +0000 (10:08 +0100)]
Ganulate Verific support

3 years agoBump version
Yosys Bot [Fri, 12 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2573 from zachjs/repeat-call
whitequark [Thu, 11 Feb 2021 19:56:41 +0000 (19:56 +0000)]
Merge pull request #2573 from zachjs/repeat-call

verilog: refactored constant function evaluation

3 years agoMerge pull request #2578 from zachjs/genblk-port
Zachary Snow [Thu, 11 Feb 2021 15:26:49 +0000 (10:26 -0500)]
Merge pull request #2578 from zachjs/genblk-port

verlog: allow shadowing module ports within generate blocks

3 years agoMerge pull request #2584 from antmicro/atom_type_signedness
Zachary Snow [Thu, 11 Feb 2021 15:26:06 +0000 (10:26 -0500)]
Merge pull request #2584 from antmicro/atom_type_signedness

verilog_parser: fix missing is_signed attribute in type_atom

3 years agoAdd missing is_signed to type_atom
Kamil Rakoczy [Thu, 11 Feb 2021 11:53:07 +0000 (12:53 +0100)]
Add missing is_signed to type_atom

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
3 years agoverlog: allow shadowing module ports within generate blocks
Zachary Snow [Sun, 7 Feb 2021 04:54:17 +0000 (23:54 -0500)]
verlog: allow shadowing module ports within generate blocks

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.

3 years agoBump version
Yosys Bot [Sun, 7 Feb 2021 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2576 from zachjs/port-bind-sign-uniop
whitequark [Sat, 6 Feb 2021 19:25:32 +0000 (19:25 +0000)]
Merge pull request #2576 from zachjs/port-bind-sign-uniop

genrtlil: fix signed port connection codegen failures

3 years agogenrtlil: fix signed port connection codegen failures
Zachary Snow [Sat, 6 Feb 2021 00:38:10 +0000 (19:38 -0500)]
genrtlil: fix signed port connection codegen failures

This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.

3 years agoBump version
Yosys Bot [Sat, 6 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2572 from antmicro/check-labels
whitequark [Fri, 5 Feb 2021 06:49:34 +0000 (06:49 +0000)]
Merge pull request #2572 from antmicro/check-labels

verilog_parser: add label check to gen_block

3 years agoBump version
Yosys Bot [Fri, 5 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoAccept disable case for SVA liveness properties.
Diego H [Thu, 4 Feb 2021 21:35:35 +0000 (15:35 -0600)]
Accept disable case for SVA liveness properties.

3 years agoAdd check of begin/end labels for genblock
Kamil Rakoczy [Thu, 4 Feb 2021 11:12:59 +0000 (12:12 +0100)]
Add check of begin/end labels for genblock

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
3 years agoverilog: refactored constant function evaluation
Zachary Snow [Wed, 27 Jan 2021 18:21:13 +0000 (13:21 -0500)]
verilog: refactored constant function evaluation

Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.

3 years agoMerge pull request #2529 from zachjs/unnamed-genblk
whitequark [Thu, 4 Feb 2021 09:57:28 +0000 (09:57 +0000)]
Merge pull request #2529 from zachjs/unnamed-genblk

verilog: significant block scoping improvements

3 years agoBump version
Yosys Bot [Thu, 4 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2436 from dalance/fix_generate
whitequark [Wed, 3 Feb 2021 09:43:23 +0000 (09:43 +0000)]
Merge pull request #2436 from dalance/fix_generate

Fix begin/end in generate

3 years agoProvide an integer implementation of decimal_digits().
Henner Zeller [Mon, 1 Feb 2021 19:23:44 +0000 (11:23 -0800)]
Provide an integer implementation of decimal_digits().

Signed-off-by: Henner Zeller <h.zeller@acm.org>
3 years agoverilog: significant block scoping improvements
Zachary Snow [Wed, 27 Jan 2021 18:30:22 +0000 (13:30 -0500)]
verilog: significant block scoping improvements

This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493

3 years agoBump version
Yosys Bot [Sun, 31 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoRequire latest Verific build
Miodrag Milanovic [Sat, 30 Jan 2021 08:23:46 +0000 (09:23 +0100)]
Require latest Verific build

3 years agoBump version
Yosys Bot [Sat, 30 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoast: fix dump_vlog display of casex/casez
Marcelina Kościelnicka [Wed, 27 Jan 2021 23:31:50 +0000 (00:31 +0100)]
ast: fix dump_vlog display of casex/casez

The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.

3 years agoMerge pull request #2564 from whitequark/flatten-improve-error
whitequark [Fri, 29 Jan 2021 02:55:51 +0000 (02:55 +0000)]
Merge pull request #2564 from whitequark/flatten-improve-error

flatten: clarify confusing error message

3 years agoBump version
Yosys Bot [Fri, 29 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2569 from zachjs/macro-arg-surrounding-spaces
whitequark [Thu, 28 Jan 2021 21:32:27 +0000 (21:32 +0000)]
Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces

verilog: strip leading and trailing spaces in macro args

3 years agoMerge pull request #2535 from Ravenslofty/scc-specify
Claire Xen [Thu, 28 Jan 2021 18:01:29 +0000 (19:01 +0100)]
Merge pull request #2535 from Ravenslofty/scc-specify

scc: Add -specify option to find loops in boxes

3 years agoverilog: strip leading and trailing spaces in macro args
Zachary Snow [Thu, 28 Jan 2021 16:26:21 +0000 (11:26 -0500)]
verilog: strip leading and trailing spaces in macro args

3 years agoBump version
Yosys Bot [Wed, 27 Jan 2021 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agoxilinx_dffopt: Don't crash on missing IS_*_INVERTED.
Marcelina Kościelnicka [Mon, 25 Jan 2021 12:01:18 +0000 (13:01 +0100)]
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.

The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll.  Just assume false if the
parameter doesn't exist.

Fixes #2559.

3 years agoxilinx: Add FDRSE_1, FDCPE_1.
Marcelina Kościelnicka [Mon, 25 Jan 2021 12:01:24 +0000 (13:01 +0100)]
xilinx: Add FDRSE_1, FDCPE_1.

3 years agoMerge pull request #2563 from whitequark/cxxrtl-msvc
whitequark [Tue, 26 Jan 2021 21:55:12 +0000 (21:55 +0000)]
Merge pull request #2563 from whitequark/cxxrtl-msvc

cxxrtl: do not use `->template` for non-dependent names

3 years agoMerge pull request #2544 from modwizcode/fix-clock
whitequark [Tue, 26 Jan 2021 21:18:06 +0000 (21:18 +0000)]
Merge pull request #2544 from modwizcode/fix-clock

CXXRTL: Fix sliced bits as clock inputs

3 years agoflatten: clarify confusing error message.
whitequark [Tue, 26 Jan 2021 18:29:16 +0000 (18:29 +0000)]
flatten: clarify confusing error message.

3 years agocxxrtl: do not use `->template` for non-dependent names.
whitequark [Tue, 26 Jan 2021 17:42:23 +0000 (17:42 +0000)]
cxxrtl: do not use `->template` for non-dependent names.

This breaks build on MSVC but not GCC/Clang.

3 years agoscc: Add -specify option to find loops in boxes
Dan Ravensloft [Mon, 11 Jan 2021 18:37:27 +0000 (18:37 +0000)]
scc: Add -specify option to find loops in boxes