iris: Implement new way for setting streamout buffers.

For gen12 we set the streamout buffers using 4 separate
commands instead of 3DSTATE_SO_BUFFER.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructions

For gen12 we set the streamout buffers using 4 separate
commands instead of 3DSTATE_SO_BUFFER.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

freedreno/a6xx: add a618 support

Signed-off-by: Rob Clark <robdclark@chromium.org>

freedreno/a6xx: cleanup magic registers

Extract out values for the handful of unknown registers which have
different values across different a6xx models, to simplify adding
support for new a6xx's.

Signed-off-by: Rob Clark <robdclark@chromium.org>

freedreno/a6xx: remove some left over dead code

These registers don't exist, just remnants of initial port from a5xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>

anv: Set depthBounds to true in anv_GetPhysicalDeviceFeatures.

Add depth bounds testing to the list of supported
physical device features.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

genxml: Change 3DSTATE_DEPTH_BOUNDS bias.

The bias for the 3DSTATE_DEPTH_BOUNDS instruction
should be 2 not 1.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

gitlab-ci: Only run the pipeline if any files affecting it have changed

E.g. documentation-only changes cannot affect the outcome of the
pipeline, so don't waste resources on running it.

The thing we need to be careful about here is that the container stage
jobs must always run if any later stage jobs using the corresponding
docker images run. We're currently using the same .ci-run-policy
template for all jobs, so this is trivially true.

v2:
* Add bin/ and common.py (Eric Engestrom)

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> # v1
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

gallium/swr: Enable GL_ARB_gpu_shader5: multiple streams

Added support for geometry shader multiple streams (part of
GL_ARB_gpu_shader5 extension).

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>

panfrost: Remove unused definitions in mali-job.h

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Cleanup _shader_upper -> shader

I don't believe this is actually a tagged pointer; warn if it is.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

meson: define _GNU_SOURCE on FreeBSD

_mesa_strtod() needs this to use strtod_l(), which behaves correctly
wrt `,` vs `.` decimal separator.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2008
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

intel/perf: update ICL configurations

A few equations/programming changes for ICL.

v2: Fix a couple of issues in naming and floating/integer operations (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

gitlab-ci: Update required libdrm version

Commit 9edcce2a32ed bumped the required libdrm-amdgpu version to
2.4.100. Update the version we use in our CI scripts to avoid CI
build failures.

Also bump the debian image name for this change to take effect.
Note that amdgpu is only built with the debian-buster image,
so only this image requires an update.

Fixes: 9edcce2a ("ac: get tcc_harvested from the kernel")
Signed-off-by: Alexandros Frantzis <alexandros.frantzis@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>

travis: fix scons build after deprecation warning

Fixes: 54053bc8d0dad89a38e2 ("scons: Print a deprecation warning about using scons on not windows")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

anv: Fix output of INTEL_DEBUG=bat for chained batches

The anv_batch_bo contents are linked one to another, and when printing
we have to start with the first of those.  Since in `u_vector` new
elements are added to the head, to get the first element we need the
vector's tail.

Fixes: 32ffd90002b ("anv: add support for INTEL_DEBUG=bat")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

winsys/amdgpu: use the new GPU reset query

ac: get tcc_harvested from the kernel

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: initialize shader compilers in threads on demand

It takes a noticable amount of time with piglit.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: don't print diagnostic LLVM remarks and notes

We don't use them.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

aco: Introduce vgpr_limit to keep track of available VGPRs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: Implement subgroup shuffle in GFX10 wave64 mode.

Previously subgroup shuffle was implemented using the bpermute
instruction, which only works accross half-waves, so by itself it's
not suitable for implementing subgroup shuffle when the shader is
running in wave64 mode.

This commit adds a trick using shared VGPRs that allows to implement
subgroup shuffle still relatively effectively in this mode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: Remove dead code in reduction lowering.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: Fix reductions on GFX10.

Fixes p_reduce (all cluster sizes), p_inclusive_scan and p_exclusive_scan
with all reduction operations.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

loader: default to iris for all future PCI IDs

The existing "fallback" code didn't actually do anything, so this
removes it, and instead we just always fallback to `iris` for future
PCI IDs.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: add a couple printflike() annotations

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>

st/mesa: lower global vars to local after lowering clip

When this code was merged, this wasn't necessary because the
state-tracker would do it later anyway. But this recently got changed,
without changing the code that depended on this.

Arguably, this was a mistake in the lowering pass to begin with. Either
way, let's fix it by not assuming that the lowering code gets called
later when it's not needed.

This fixed user-defined clip-planes in Zink.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: eaffdad1082 ("st/mesa: don't lower_global_vars_to_local for VS if there are no dead inputs")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

iris: Create resource with aux_usage MCS_CCS

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Support lossless compression with multisamples

GEN12 adds the ability to losslessly compress each sample plane in a
multisampled buffer that uses MCS compression.

v2: Remove unnecessary assertion (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Get correct resource aux usage for copy

Add case for MCS_CCS so that we get the correct aux usage while copy
operation.

v2: Fix commit subject (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/blorp: Use isl_aux_usage_has_mcs instead of comparing

Depending on MCS_CSS or MCS we can emit blorp blit shaders.

As we support MCS_CSS and MCS, it makes sense to use
isl_aux_usage_has_mcs function.

v2: Fix commit message (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Define MCS_CCS state transitions and usages

v2: 1) Fix assertion check (Nanley Chery)
    2) Correct commit subject (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

iris: Initialize CCS to fast clear while using with MCS

v2: Explain Bsepc quotes properly (Nanley Chery)

v3: 1) Fix comment format (Nanley Chery)
    2) Fix typo in comment (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Don't reconfigure aux surfaces for MCS

If aux for MCS is already configured, don't configure again.

v2: Fix missing period in commit message (Nanley Chery)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

zink: emulate optional depth-formats

The Vulkan spec says that an implementation has to support one of
VK_FORMAT_X8_D24_UNORM_PACK32 and VK_FORMAT_D32_SFLOAT, as well of
one of VK_FORMAT_D24_UNORM_S8_UINT and VK_FORMAT_D32_SFLOAT_S8_UINT.

So let's keep track which one is supported of earch pair, and emulate
one on top of the other one.

This won't give the exact result for comparisons, or when mapping and
unmapping the resources. But it's better than flat out failing to create
the resource, and we can fix the map/unmap issue later if needed.

Tested-by: Duncan Hopkins <duncan@thefoundry.co.uk>

zink: error if VK_KHR_maintenance1 isn't supported

While we're at it, remove the VK_-prefix from the extension bool; all
extensions have this so it's kinda superfluous.

iris: Disallow incomplete resource creation

If a modifier specifies an aux, it must be created.

Fixes: 75a3947af46 ("iris/resource: Fall back to no aux if creation fails")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Don't leak the resource for unsupported modifier

Make sure the res struct is free'd before returning.

Fixes: 2dce0e94a3d ("iris: Initial commit of a new 'iris' driver for Intel Gen8+ GPUs.")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Enable HIZ_CCS sampling

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Satisfy clear color rules for HIZ_CCS

Store the converted depth value into two dwords. Avoids regressing the
piglit test "fbo-depth-array depth-clear", when HIZ_CCS sampling is
enabled in a later commit.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Fix and use HIZ_CCS write through mode

Write through to the CCS if the surface is used as a texture and can be
sampled by the HW with CCS.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Start using blorp_can_hiz_clear_depth()

Check that the alignment requirements for HIZ_CCS are satisfied by using
this function.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Satisfy HIZ_CCS fast-clear alignments

Prevent the piglit test,
amd_vertex_shader_layer-layered-depth-texture-render, from regressing in
in a future commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Refactor blorp_can_hiz_clear_depth()

Prepare this function to be used in iris and to handle new Gen12 behavior.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

isl: Add isl_surf_supports_hiz_ccs_wt()

Add a helper to determine if an ISL surface supports the write-through
mode of HIZ_CCS.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Enable HIZ_CCS in depth buffer instructions

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Define initial HIZ_CCS state and transitions

Make it match those of HIZ.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Create an unusable secondary aux surface

The HIZ_CCS and MCS_CCS auxiliary surface modes require that drivers
store information about two aux buffers. We choose to represent this as
HiZ/MCS being the primary aux surface and the CCS as an secondary/extra
aux surface. This representation has the effect of placing most of the
code that will have to choose between the two aux surfaces around the
aux-map entry points.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Don't guess the aux_usage

Instead of guessing an aux_usage, then confirming it if the
isl_surf_get_*_surf functions are successful, just call the ISL
functions up-front. This will help us to more easily determine if a
depth buffer supports HIZ_CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Treat HIZ_CCS like HiZ

Allow it in depth buffer instructions but disable it for blits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Assert against HiZ in surface states

Avoid unexpected behavior if the caller happens to pass in a HiZ aux
usage.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Support HIZ_CCS in isl_surf_get_ccs_surf

Add an extra aux parameter which will be filled out with CCS if the
first two isl_surf parameters fit the requirements for HiZ_CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

isl: Reduce assertions during aux surf creation

Return false more often to reduce the burden on the caller.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+

While this format isn't listed in BSpec: 53911, other documentation and
empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
filed a bug for the BSpec page.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnable

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz

v2. Remove undocumented CCS_E-only mode for depth. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Use RENDER_SURFACE_STATE::DepthStencilResource

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Update alignment restrictions for HiZ surfaces.

v2 (Nanley):
* Maintain a chronological ordering for HiZ alignments. Suggested by
  Ken.

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Clear ::has_hiz when disabling aux

Fixes: 2cddc953cd0 ("iris: some initial HiZ bits")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/blorp: Disable depth testing for slow depth clears

We'll start doing slow depth clears more often on HIZ_CCS buffers in a
future commit. Reduce the performance impact by making them use less
bandwidth.

From the Depth Test section of the BSpec:

   This function is enabled by the Depth Test Enable state variable. If
   enabled, the pixel's ("source") depth value is first computed. After
   computation the pixel's depth value is clamped to the range defined
   by Minimum Depth and Maximum Depth in the selected CC_VIEWPORT state.
   Then the current ("destination") depth buffer value for this pixel is
   read.

and from the Depth Buffer Updates section of the BSpec:

   If depth testing is disabled or the depth test passed, the incoming
   pixel's depth value is written to the Depth Buffer.

Taken together, it's clear that depth testing isn't necessary to perform
a depth buffer clear. Mark Janes and I analyzed this patch with
frameretrace and a depthrange piglit test. I disabled HiZ to ensure we'd
get slow depth clears. We've observed the bandwidth consumption by the
depth buffer access to be cut ~50% on BDW and SKL during depth clears.
On a more graphically intensive workload, the Shadowmapping Sascha
benchmark, I took the average of 3 runs on a BDW with a display
resolution of about 1920x1200 (minus some desktop environment
decorations). I measured a 22.61% FPS improvement when HiZ is disabled.

v2. The BSpec doesn't mandate this behavior, update comment accordingly.
    (Ken)

Fixes: bc4bb5a7e30 ("intel/blorp: Emit more complete DEPTH_STENCIL state")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel: Enable CCS_E for some formats on Gen12

In ISL:
   Update the format table to add CCS_E support for some 8BPP formats,
   some 16BPP formats, and R10G10B10A2_UNORM_SRGB.

   In the helper for determining CCS_E support, we return false for some
   16BPP formats because they aren't properly handled in blorp_copy().

In BLORP:
   Allow the new and non-problematic formats for CCS_E-enabled copies.

v2. Update other fields for A1B5G5R5_UNORM and A4B4G4R4_UNORM in table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)

isl: Redefine the CCS layout for Gen12

The CCS could be described in a number of ways, but this format was
chosen to minimize churn in the drivers. We may decide on an different
direction in the future.

v2. Increase alignment for display surfaces. (Nanley)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

isl: Add and use isl_tiling_flag_to_enum()

Use a helper that will automatically handle Gen12's CCS tiling when
creating a CCS isl_surf.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

iris: Allow for non-Y-tiled aux allocation

The Gen12 CCS is not Y-tiled.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

isl/drm: Map HiZ and CCS tilings to Y

In the function which translates ISL tilings to i915 tilings, map ISL's
HiZ and CCS tilings to Y instead of NONE (linear). The HW docs describe
HiZ and pre-Gen12 CCS surfaces as being Y-tiled in memory.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/isl: Update surf_fill_state for gen12

v2 (Nanley):
* Avoid driver churn for now.
* Include some media compression changes.

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/isl/fill_state: Separate aux_mode handling from aux_surf

v2. Avoid driver churn for now. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/isl: Add new aux modes available on gen12

v2. Add media compression. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965/miptree: Avoid -Wswitch for the Gen12 aux modes

Avoid the compiler warnings for the new enums that will be introduced in
a future commit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv/private: Modify aux slice helpers for Gen12 CCS

The isl_surf structs for Gen12's CCS won't describe how many slices in
the main surface can be compressed. All slices will be compressable if
CCS is enabled, so lookup the main surface's logical dimension.

v2. Add a space before a `?`. (Jordan)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp: Don't assert aux slices match main slices

This isn't accurate enough for HiZ which can have a discontiguous range
of supported aux slices. This also won't work with the plan to represent
Gen12 CCS as a single slice surface.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp: Use surf instead of aux_surf for image dimensions

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp: Halve the Gen12 fast-clear/resolve rectangle

Update their dimensions according to the Bspec.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

intel/blorp/gen12: Set FWCC when storing the clear color.

From "Render Target Fast Clear" description for Gen12:

   "SW must store clear color using MI_STORE_DATA_IMM with
   ForceWriteCompletionCheck bit set."

From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1):

   "Following the last write from this command, Command Streamer
   will wait for all previous writes are completed and in global
   observable domain before moving to next command."

We use 4 SDIs to store the clear color (one per channel). From the
description, it looks to me that setting that flag only on the last SDI
should be enough.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

isl: Round up some pitches to 512B for Gen12's CCS

Gen12's CCS requires that the main surface have a pitch aligned to 512B.

v2. Provide a BSpec citation. (Ken)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris: Don't assume CCS_E includes CCS_D

There's no longer a clear-only compression mode of CCS on Gen12+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv/cmd_buffer: Don't assume CCS_E includes CCS_D

There's no longer a clear-only compression mode of CCS on Gen12+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv/image: Disable CCS_D on Gen12+

Clear-only compression no longer exists on TGL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

isl: Disable CCS_D on Gen12+

Clear-only compression no longer exists on TGL.

v2. Add BSpec reference. (Sagar)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

iris: Drop support for I915_FORMAT_MOD_Y_TILED_CCS on TGL+

The format of the CCS has changed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv/formats: Disable I915_FORMAT_MOD_Y_TILED_CCS on TGL+

The format of the CCS has changed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

anv: Properly allocate aux-tracking space for CCS_E

add_aux_state_tracking_buffer() actually checks the aux usage when
determining how many dwords to allocate for state tracking. Move the
function call to the point after the CCS_E aux usage is assigned.

Fixes: de3be618016 ("anv/cmd_buffer: Rework aux tracking")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv/blorp: Use BLORP_BATCH_NO_UPDATE_CLEAR_COLOR

Avoid failing the `info->use_clear_address` assertion in ISL on Gen12+.

Fixes: 6c9f9a82d78 ("intel/genxml,isl: Add gen12 render surface state changes")
Reported-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: Add support for depth bounds testing.

In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction
to enable depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

iris: Add support for depth bounds testing.

In gen12 we use the 3DSTATE_DEPTH_BOUNDS instruction
to enable depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.

In gen12 we add the 3DSTATE_DEPTH_BOUNDS instruction
which enables support for depth bounds testing.

Signed-off-by: Plamena Manolova <plamena.manolova@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Initialize all fields of ir_variable in constructor

Better be safe, even if we could technically avoid this for
some fields.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1999
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

util: remove LIST_IS_EMPTY macro

Just use the inlined function directly. The new function was introduced
in addcf410.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: rename list_empty() to list_is_empty()

This makes it clear that it's a boolean test and not an action
(eg. "empty the list").

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_DEL macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_DELINIT macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_REPLACE macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_ADD macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_ADDTAIL macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

util: remove LIST_INITHEAD macro

Just use the inlined function directly. The macro was replaced with
the function in ebe304fa540f.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>

gitlab-ci: fixup debian tags

When resolving a merge-conflict, I accidentally only updated the
ARM64-tag tag. Let's correct this.

Fixes: 3d529c17393 ("gitlab-ci: also build Zink on CI")

intel/compiler: Fix C++ one definition rule violations

When building with "-flto" brw::block_data definitions
were colliding.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gitlab-ci: also build Zink on CI

This prevents accidentally breaking the driver-build while working on
other drivers.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>

zink: simplify gl-to-vulkan lowering

Acked-by: Jordan Justen <jordan.l.justen@intel.com>

zink/spirv: more complete sampler-dim handling

Acked-by: Jordan Justen <jordan.l.justen@intel.com>