nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capability

Prefer blit-based texture transfers only if the chip has dedicated VRAM
since it would translate to a copy into the same memory on shared-memory
chips.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: reset the source packing when creating temp transfer image

Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced
proper transferops handling, but in updating the source to the newly
allocated temporary image neglected to reset the source packing. Set it
to the default which should be appropriate for the floats used.

Fixes: 4b249d2ee (mesa: Handle transferOps in texstore_rgba)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

nvc0: create screen fence objects with coherent attribute

This is required on non-coherent architectures to ensure the value of
the fence is correct at all times. Failure to do this results in the
display freezing for a few seconds every now and then on Tegra.

The NOUVEAU_BO_COHERENT is a no-op for coherent architectures, so behavior
on x86 should not be affected by this patch.

Also bump the required libdrm version to 2.4.62, which introduced this
flag.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Martin Peres <martin.peres@free.fr>

i965/gen9: use an unreserved surface alignment value

Although the horizontal and vertical alignment fields are ignored here,
0 is a reserved value for them and may cause undefined behavior. Change
the default value to an abitrary valid one.

v2: add comment about chosen value (Topi).

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>

i965/fs: Use the builder directly for the gen6 interpolation add(32)

Now that we can create builders with a bigger width than their parent as
long as it's exec_all, we don't need to create the instruction manually.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Relax fs_builder channel group assertion when force_writemask_all is on.

This assertion was meant to catch code inadvertently escaping the
control flow jail determined by the group of channel enable signals
selected by some caller, however it seems useful to be able to
increase the default execution size as long as force_writemask_all is
enabled, because force_writemask_all is an explicit indication that
there is no longer a one-to-one correspondence between channels and
SIMD components so the restriction doesn't apply.

In addition reorder the calls to fs_builder::group and ::exec_all in a
couple of places to make sure that we don't temporarily break this
invariant in the future for instructions with exec_size higher than
the dispatch width.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

nouveau: rename var name for nouveau_vieux to avoid conflict with nouveau

We want to require different versions for nouveau and nouveau_vieux.
autoconf will only check for NOUVEAU once if both drivers are enabled,
meaning both version checks don't get executed. Rename the nouveau_vieux
one to NVVIEUX to avoid the issue.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Martin Peres <martin.peres@free.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

glsl: create program resource list after LinkShader

Resource list can be created properly  only after LinkShader hook
has been called to make sure all dead variables have been removed.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90925

glsl: expose build_program_resource_list function

This is required so that we can move resource list creation
to happen later.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>

glsl: build stageref mask using IR, not symbol table

Instead of using symbol table, build mask by inspecting IR. This
change is required by further patches to move resource list creation
to happen later when symbol table does not exist anymore.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>

ilo: remove ilo_image_params

It suffices to use ilo_image_layout directly.

ilo: add image_init_gen6_transfer_layout()

It replaces img_init_for_transfer().

ilo: add image_set_gen6_bo_size()

It replaces img_calculate_bo_size().

ilo: add image_set_gen6_{hiz,mcs}

They replace img_calculate_{hiz,mcs}_size().

ilo: add image_get_gen6_monolithic_size()

It replaces img_align().

ilo: add image_get_gen6_lods()

It replaces img_init_lods() and img_init_layer_height().

ilo: add image_get_gen{6,7}_alignment()

They replace img_init_alignments().

ilo: add image_get_gen6_{hiz,mcs}_enable()

They replace img_init_aux().

ilo: add image_get_gen6_tiling()

It replaces img_init_tiling().

ilo: add image_get_gen6_layout()

It replaces only img_init_walk() right now.  It will replace all img_init_*().

nv50/ir: copy joinAt when splitting both before and after

The current implementation only moves the joinAt when splitting after
the given instruction, not before it. So if you have a BB with

  foo
  instr
  bar
  joinat

and thus with joinAt set, we end up first splitting before instr, at
which point the instr's bb is updated to the new bb. Since that bb
doesn't have a joinAt set (despite containing one), when splitting after
the instr, there is nothing to copy over. Since the joinat will be in
the "split" bb irrespective of whether we're splitting before or after
the instruction, move it over in either case.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91124
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>

docs: update for llvmpipe fp64 support

Signed-off-by: Dave Airlie <airlied@redhat.com>

gallivm: add fp64 support. (v2.1)

This adds support for ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit to
llvmpipe.

Two things that don't mix well are SoA and doubles, see
emit_fetch_double, and emit_store_double_chan in this.

I've also had to split emit_data.chan, to add src_chan,
which can be different for doubles.

It handles indirect double fetches from temps, inputs, constants
and immediates. It doesn't handle double stores to indirects,
however it appears the mesa/st doesn't currently emit these,
it always does UARL/MOV combos, which will work fine.

tested with piglit, no regressions, all the fp64 tests seem to pass.

v2:
switch to using shuffles for fetch/store (Roland)
assert on indirect double stores - mesa/st never emits these (it uses MOV)
fix indirect temp/input/constant/immediates (Roland)
typos/formatting fixes (Roland)

v2.1:
cleanup some long lines, emit_store_double_chan cleanups.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

tgsi: add infer support for double opcodes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

freedreno: use consistent version string format

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

glsl: use consistent version string format

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

i965/fs: Fix PIXEL_X/Y in regs_read()

PIXEL_X/Y takes a vec2 in the first argument

i965/fs: Remove the width field from fs_reg

As of now, the width field is no longer used for anything.  The width field
"seemed like a good idea at the time" but is actually entirely redundant
with the instruction's execution size.  Initially, it gave us the ability
to easily set the instructions execution size based entirely on register
widths.  With the builder, we can easiliy set the sizes explicitly and the
width field doesn't have as much purpose.  At this point, it's just
redundant information that can get out of sync so it really needs to go.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs_generator: Use inst->exec_size for determining hardware reg widths

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Use exec_size instead of dst.width for computing component size

There are a variety of places where we use dst.width / 8 to compute the
size of a single logical channel.  Instead, we should be using exec_size.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Use the builder dispatch_width for computing register offsets

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Use the builder dispatch width instead of dst.width for pull constants

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Remove exec_size guessing from fs_inst::init()

Now that all of the non-explicit constructors are gone, we don't need to
guess anymore.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs_builder: Use the dispatch width for setting exec sizes

Previously we used dst.width but the two *should* be the same.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Use exec_size for determining regs read/written and partial writes

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Remove fs_inst constructors that don't take an explicit exec_size

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Make better use of the builder in shader_time

Previously, we were just depending on register widths to ensure that
various things were exec_size of 1 etc.  Now, we do so explicitly using the
builder.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Add a builder argument to offset()

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Move offset(fs_reg, unsigned) to brw_fs.h

Shortly, offset() will depend on the builder so we need it moved to some
place where it has access to that.

Reviewed-by: Iago Toral Quiroga <itoral@igali.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/blorp: Explicitly set execution sizes for new'd instructions

This doesn't affect instructions allocated using the builder.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Set the builder group for emitting FB-write stencil/AA alpha

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Explicitly set the exec_size on the add(32) in interpolation setup

Soon we will start using the builder to explicitly set all the execution
sizes.  We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a reasonable assumption.  Since this one
instruction is a bit of an odd-ball, we just set the exec_size explicitly.

v2: Explicitly new the fs_inst instead of using the builder and setting
    exec_size after the fact.

v3: Set force_writemask_all with the builder instead of directly.  The
    builder over-writes it if we set it manually.  Also, if we don't have
    force_writemask_all in the builder it will assert-fail on SIMD32.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Properly handle LOAD_PAYLOAD in fs_inst::regs_read

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Report the right value in fs_inst::regs_read() for PIXEL_X/Y

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Fix fs_inst::regs_read() for uniform pull constant loads

Previously, fs_inst::regs_read() fell back to depending on the register
width for the second source.  This isn't really correct since it isn't a
SIMD8 value at all, but a SIMD4x2 value.  This commit changes it to
explicitly be always one register.

v2: Use mlen for determining the number of registers read

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>

i965/fs: Actually set/use the mlen for gen7 uniform pull constant loads

Previously, we were allocating the payload with different sizes per gen and
then figuring out the mlen in the generator based on gen.  This meant,
among other things, that the higher level passes knew nothing about it.

Acked-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Use a switch statement in fs_inst::regs_read()

This makes things a little simpler, more efficient, and quite a bit more
readable.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

nir: remove parent_instr from nir_register

It's no longer used.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

nir: remove nir_src_get_parent_instr()

It's now unused.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/fs: emit constants only once

Before, we would lazily emit a MOV whenever we encountered a use of a
constant. Now that we have a dedicated file for SSA values, we can
instead only emit the MOV's once, which is more consistent and prevents
us from relying on CSE to re-combine the constants when they aren't
absorbed into the instruction.

total instructions in shared programs: 6078991 -> 6073118 (-0.10%)
instructions in affected programs:     402221 -> 396348 (-1.46%)
helped:                                1527
HURT:                                  0
GAINED:                                8
LOST:                                  2

v2: split this out from the previous commit (Jason)

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/fs: use SSA values directly

Before, we would use registers, but set a magical "parent_instr" field
to indicate that it was actually purely an SSA value (i.e., it wasn't
involved in any phi nodes). Instead, just use SSA values directly, which
lets us get rid of the hack and reduces memory usage since we're not
allocating a nir_register for every value. It also makes our handling of
load_const more consistent compared to the other instructions.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

nir/from_ssa: add a flag to not convert everything from SSA

We already don't convert constants out of SSA, and in our backend we'd
like to have only one way of saying something is still in SSA.

The one tricky part about this is that we may now leave some undef
instructions around if they aren't part of a phi-web, so we have to be
more careful about deleting them.

v2: rename and flip meaning of flag (Jason)

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

egl/x11: handle when invalid drawable is passed in create_surface

0 is not used as a valid drawable id, as such there is no point in
attempting to query its geometry. Just bail out early and provide the
more meaningful EGL_BAD_NATIVE_WINDOW to the user.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

egl/wayland: cleanup dri2_wl_create_surface error path

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

egl/wayland: handle NULL native_window in create_surface

Raise EGL_BAD_NATIVE_WINDOW instead of crashing.

v2: s/Rise/Raise/ (spotted by Michel)

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

egl/drm:  plug memory leak

Free the memory for dri2_surf in the unlikely case that one provides
NULL for native_window. Also set the relevant EGL_ERROR to provide
feedback to the user.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/ttn: don't upset nir_validate w/ BRK's

Previously we were unconditionally doing ttn_get_src() even for
instructions with no src's.  Which created a lot of unnecessary
load_const instructions.  These were mostly harmless since NIR opt
passes would strip them back out.  But for an ENDIF following a
BRK, it would result in load_const instructions created after the
NIR break instruction.  Which nir_validate dislikes.

But we can actually just dtrt by using NumSrcRegs instead.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium/ttn: add TXB2

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium/ttn: partial fix for output arrays

It isn't quite yet practical to enable TGSI_ANY_INOUT_DECL_RANGE shader
cap yet, at least not in drivers that need lower_to_scalar pass (which
right now is all of the ttn users), since the register arrays do not get
converted to SSA, which angers nir_lower_alu_to_scalar.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

nir: cleanup open-coded instruction casts

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

freedreno/ir3: cache defining instruction

It is silly to traverse back to find first instruction that writes part
of a larger "virtual" register many times per instruction (plus per use
as a src to later instructions).  Cache this information so we only
figure it out once.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix RA issue with fanin

The fanin source could be grouped, for example with shaders like:

    VERT
    DCL IN[0]
    DCL IN[1]
    DCL OUT[0], POSITION
    DCL OUT[1], GENERIC[9]
    DCL SAMP[0]
    DCL SVIEW[0], 2D, FLOAT
    DCL TEMP[0], LOCAL
      0: MOV TEMP[0].xy, IN[1].xyyy
      1: MOV TEMP[0].w, IN[1].wwww
      2: TXF TEMP[0], TEMP[0], SAMP[0], 2D
      3: MOV OUT[1], TEMP[0]
      4: MOV OUT[0], IN[0]
      5: END

The second arg to the isaml is IN[1].w, so we need to look at the fanin
source to get the correct offset.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: add ir3_shader_disasm()

Split out most of dump_info() from ir3_cmdline compiler into a function
that can be used both by cmdline compiler and also for the disasm debug
option.  This way, for FD_MESA_DEBUG=disasm we also get to see intput/
output registers, etc.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: fix for sparse-samplers

Some piglit tests, like arb_fragment_program-sparse-samplers, result in
having a null samp#0 but valid samp#1.

TODO: a3xx probably needs similar fix

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix crash in fail path

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix crash in RA

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fixes for indirect writes

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/ir3: fix constlen in case of load_uniform_indirect

We can't rely on what we get from the assembler if we have indirect
addressing of constant file, since the assembler doesn't know the array
index.  This got lost in the transition to NIR.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

glsl: validate sampler array indexing for 'constant-index-expression'

Desktop GLSL < 130 and GLSL ES < 300 allow sampler array indexing where
index can contain a loop induction variable. This extra check will warn
during linking if some of the indexes could not be turned in to constant
expressions.

v2: warning instead of error for backends that did not enable
    EmitNoIndirectSampler option (have dynamic indexing)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "10.5" and "10.6" <mesa-stable@lists.freedesktop.org>

mesa/st: use EmitNoIndirectSampler if !ARB_gpu_shader5

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "10.5" and "10.6" <mesa-stable@lists.freedesktop.org>

i915: use EmitNoIndirectSampler

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "10.5" and "10.6" <mesa-stable@lists.freedesktop.org>

i965: use EmitNoIndirectSampler for gen < 7

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "10.5" and "10.6" <mesa-stable@lists.freedesktop.org>

mesa/glsl: new compiler option EmitNoIndirectSampler

Patch provides new compiler option for backend to force unroll loops
that have non-constant expression indexing on sampler arrays.

This makes sure that we can never end up with a shader that uses loop
induction variable as sampler array index but does not unroll because
of having too much instructions. This would not work without dynamic
indexing support.

v2: change option name as EmitNoIndirectSampler

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "10.5" and "10.6" <mesa-stable@lists.freedesktop.org>

glsl: Allow dynamic sampler array indexing with GLSL ES < 3.00

Dynamic indexing of sampler arrays is prohibited by GLSL ES 3.00.
Earlier versions allow 'constant-index-expression' indexing, where
index can contain a loop induction variable.

Patch allows dynamic indexing for sampler arrays when GLSL ES < 3.00.
This change makes 'sampler-array-index.frag' parser test in Piglit
pass + fishgl.com works when running Chrome on OpenGL ES 2.0 backend

v2: small change and some more commit message (Tapani)
v3: refactor checks to make it more readable (Ian Romanick)
v4: change warning comment in GLSL ES case (Curro)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: "10.5" and "10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84225

nv50/ir: fix emission of address reg in 3rd source

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91056
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>

i965: Don't use GCC extension for ?: with only two operands.

From the "apparently I don't know C" files...GCC apparently supports:

    x ?: y

which is equivalent to

    x ? x : y

except that it doesn't cause side-effects to occur twice.  See:
https://gcc.gnu.org/onlinedocs/gcc/Conditionals.html#Conditionals

This was confusing and looked like a typo.  It doesn't really buy us
anything, so just write the obvious code in normal C.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

egl/haiku: fix Mesa build under Haiku

Performing a goto crosses the initialization of 'BWindow* win'
breaking the build. We also fix a missing semicolon.

nv30: align transfer stride to 64, required by blit, sifm transfer impls

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv30: allow vertex state creation with 0 elements

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv30: reset fragprog bufctx at bind time

A clear will do a partial validate, which will in turn reference all the
buffers in the bufctx again. However the fragprog last validated might
have already been deleted. So reset the bufctx when updating state.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv30: modernize fp upload logic

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv30: provide a minimum map buffer alignment

Otherwise we return 0, which is out of spec. Return 64 like all the
other nouveau drivers.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965/skl: Extract the blit command setup in to a helper

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()

This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
It can be later turned on for other tiling patterns (X,Y) too.

V3: Flush in between sequential fast copy blits.
    Fix src/dst alignment requirements.
    Make can_fast_copy_blit() helper.
    Use ffs(), is_power_of_two()
    Move overlap computation inside intel_miptree_blit().

V4: Use _mesa_regions_overlap() function.
    Add check for src_buffer == dst_buffer.
    Simplify horizontal and vertical alignment computations.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

mesa/swrast: Use global function _mesa_regions_overlap()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa/st: Use global function _mesa_regions_overlap()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add a new helper function _mesa_regions_overlap()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965/gen9: Allocate YF/YS tiled buffer objects

In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
libdrm need not know about the tiling format because these buffers
don't have hardware support to be tiled or detiled through a fenced
region. libdrm still need to know buffer alignment value for its use
in kernel when resolving the relocation.

Using drm_intel_bo_alloc_for_render() for YF/YS tiled buffers
satisfy both the above conditions.

V2: Delete min/max buffer size restrictions not valid for i965+.
    Remove redundant align to tile size statements.
    Remove some redundant code now when there are no min/max buffer size.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Make a helper function intel_miptree_can_use_tr_mode()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Make a helper function intel_miptree_release_levels()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965/gen9: Plugin the code for selecting YF/YS tiling on skl+

Buffers with Yf/Ys tiling end up using meta upload / download
paths or the blitter for cases where they used tiled_memcpy paths
in case of Y tiling. This has exposed some bugs in meta path. To
avoid any piglit regressions on SKL this patch keeps the Yf/Ys
tiling disabled at the moment.

V3: Make brw_miptree_choose_tr_mode() actually choose TRMODE. (Ben)
    Few cosmetic changes.
V4: Get rid of brw_miptree_choose_tr_mode().
    Take care of all tile resource modes {Yf, Ys, none} for all
    generations at one place.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

i965: Make a helper function intel_miptree_set_alignment()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

mesa/main: free locale at exit

In order to save a small leak if mesa is continously loaded and
unloaded, let's free the locale when the shared object is unloaded.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

util: port _mesa_strto[df] to C

_mesa_strtod and _mesa_strtof are only used from the GLSL compiler and
the ARB_[vertex|fragment]_program code, meaning that the locale doesn't
need to be initialized before the first OpenGL context gets initialized.

So let's use explicit initialization from the one-time init code instead
of depending on a C++ compiler to initialize at image-load time.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

glsl: No need to lock in _mesa_glsl_release_types

This function only gets called while mesa is unloading, so there's
no potential of racing or multiple calls at the same time. So let's
just get rid of the locking.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa/main: only call _mesa_destroy_shader_compiler once on exit

There's no point in calling _mesa_destroy_shader_compiler multiple
times on exit; the resources will only be released once anyway.

So let's move the atexit-call into the part that is only called
once.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

dri: don't touch the shader compiler

This function is for deleting per-screen resources, and the shader
compiler resources are not of such nature. Besides, dri shouldn't
need to even know about the presence of a shader compiler.

These resources will already be released when mesa gets unloaded,
and that should be sufficient.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa/main: Get rid of outdated GDB-hack

All of these enums are now in use around in the code, so there's no need
to explicitly use them here any more.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

clover: implement CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE

Work-group size should always be aligned to subgroup size; this is a
basic requirement, otherwise some work-items will be no-operation.

It might make sense to refine the value according to a kernel's
resource usage, but that's a possible optimization for the future.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

gallium: add PIPE_COMPUTE_CAP_SUBGROUP_SIZE

We need this to implement OpenCL's
CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>