sim: Optionally pass "position" to GuestABI::Result::store.

This will let it get at information about the signature as a whole.

Also, put result storing and argument getting behind functions to hide
some of the templating involved in those mechanisms.

Change-Id: Ib9f26ff69495f8891435f68d3d2f9dfa761a0274
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24105
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Split up the guest_abi.hh header.

This header was getting pretty long, and could be broken up into a few
headers which logically grouped related definitions and concepts.

To maintain compatibility and keep things simple for users of the
mechanism, there is still a top level header with the original name
which defines the interface for using ABIs. It includes all the other
new headers, and so can also be used when defining ABIs.

Change-Id: I62a051b9bd982e0fcecfceeb3d658d1ff4d30c5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24104
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Generalize the GuestABI Result::allocate() mechanism.

This change generalizes the GuestABI Result template family's
allocate() mechanism so that it can also be used with arguments. This
is useful in cases like the 32 bit ARM ISA which says that variadic
functions treat their floating point arguments differently than
non-variadic functions do. This mechanism will give the ABI a chance
to detect that the function is variadic (by checking for VarArgs) and
then to behave differently in that case.

This also makes the GuestABI mechanism a little more regular by
supporting allocate() on both arguments and return values instead of
just return values.

Change-Id: I67050a0ad7ccf15ee75b800dca4eae4fdc0e564e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Implement the AAPCS64 ABI.

This implementation has been tested a tiny bit by intercepting a call
which passed an argument of this type to a function.

struct Test
{
    int32_t a;
    float *b;
};

The gem5 intercept printed out the value of a, the value of b, and the
value of the float it pointed to.

I was able to get things to work by commenting out the panic in
fixFuncEventAddr and making it return its argument unmodified, and by
calling addFuncEvent instead of addKernelFuncEvent which injects the
kernel symbol table. I substitured the Process's debugSymbolTable which
had the right symbols.

Note that this implementation is not completely correct. First of all,
I used a dummy type in place of the Short Vector type which is just
a byte array with the appropriate alignment forced on it. It sounds
like this type would be something the compiler would need an intrinsic
and architecture specific type for to behave correctly, and so in
gem5 we'd have to define our own type for ARM which could feed in here.

Also, strictly speaking, it sounds like HVA and HFA category of types,
the Homogeneous Short-Vector Aggregates and Homogeneous Floating-point
Aggregates, are supposed to apply to any type which is an aggregate of
all the same type (short vector for one, floating point for the other)
with 4 or fewer members.

In this implementation, I capture any *array* of 4 or fewer elements of
the appropriate type as an HVA or HFA, but I believe these structures
would also count and are not included in my implementation.

struct {
    float a;
    float b;
    float c;
};

struct {
    ShortVector a;
    ShortVector b;
};

This only matters if those sorts of structures are passed by value as
top level arguments to a function, ie they are not included in some
larger structure.

Also, rule B.6 talks about what to do with an "aignment adjusted type",
and I have no idea what that's supposed to be. Those may not be handled
correctly either.

Change-Id: I5a599a03d38075d7c0a06988c05e7fb5423c68c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23751
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

kern: Stop using a pseudo instruction to quiesce the ThreadContext.

The pseudo instruction implementation is very short, and so doing the
work it was doing directly doesn't really add much to the
implementation of the udelay events. By not calling the pseudo
instruction we also uncouple these unrelated mechanisms and don't,
for instance, cause pseudo instruction debug output every time udelay
executes.

Change-Id: I5c9b32509562487e53b2acfa1a3f6226d33d1cfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23748
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

arm: Delete the unused onKvmExitHypercall method.

The KVM_EXIT_HYPERCALL KVM exit is now unused, and so even if this
exit handler was plumbed to receive these exits, they would probably
never come.

Change-Id: Ic3ecc789102e761a6dbe80caaf57d61dd95f70a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23746
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Get rid of the now unused setSyscallReturn method.

Change-Id: I61741ab2eca4c77a2c8884e2b5c328479e2b3c90
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23505
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Use the new returnInto method in cloneFunc.

This gets rid of the final use of setSyscallReturn.

Change-Id: I1108df0c5c72b5dec60128dced48ac0fd0356d24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23504
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Add a returnInto function to the SyscallDesc class.

This method lets system call implementations return values into
ThreadContexts other than the one they were called from. That's useful
for, for instance, clone() which creates new ThreadContexts.

By making it a virtual function in the SyscallDesc, we can delegate the
actual implementation to the SyscallDescABI subclass which knows the
ABI and how to use it to set the return value.

Change-Id: I61c6e60e4c2a8863c885cd818e4ff053fc3312ee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23503
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Get rid of the now unused getSyscallArg method.

Change-Id: I2f78420d8687da7530feb66784fe3e6d2357baf8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23462
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Rework the SyscallDesc to use the dumpSimcall mechanism.

This greatly simplifies the doSyscall method, removes a use of
getSyscallArg, and will only print arguments the target syscall is
going to use.

Change-Id: Id8c9c995a2506468fd99fd865f2eb31c40db8b55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23461
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Get rid of the no longer needed DefaultSyscallABI.

All ISAs now have their own ABI definitions.

Change-Id: I20484b024227658bed7093c232ebf7d64f29bdb6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23458
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Convert the various flavors of pipe to GuestABI.

Change-Id: I44aaff417ea6a3ce311208b084fe4013bb93a48e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23457
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim,gpu: Make ioctl unconditionally take an address parameter.

The definition of ioctl is not actually variadic, it just doesn't
specify what the type of the pointer is that it takes as its third
argument. The man page says that that's because it predates void *
being valid C.

By passing this address around (even if it's unused), we avoid having
to extract system call arguments further down the call stack.

Change-Id: I62541237baafaec30bbe3df06b3284dd286a4051
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23456
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Clean up some constants used in some syscalls.

Having readable constants for these large numbers is good, but they
used incorrect style, were at global scope, and were only used in one
place.

This change centralizes them where they're used, fixes their style, and
rewrites the actual constants in a way that makes it clear what they're
values are.

Change-Id: Ib89c46fce133d4180296d384a61d51d1fe1f8d20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23455
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Convert ftruncate64 to GuestABI.

This function was specifying a particular width to getSyscallArg. The
new ISA specific ABIs now handle that automatically.

Change-Id: I141655d3bcb78f56c2a9278d140dfbc0d69e1ff4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23454
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Use a riscv specific GuestABI for riscv system calls.

Change-Id: Ia6ac34dfb38b71eff7b573b3c9ce477fef0ef5f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23453
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Use a power specific GuestABI for power system calls.

Change-Id: I39cf64c025c284b63980f3c2e48fbd8b6c355d2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23452
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Use a mips specific GuestABI for mips system calls.

Change-Id: Ice9fb867b47e56bc00b171399a82b2892b16c9e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23451
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Remove the get*PseudoFunc handlers.

These were used in Alpha which has been removed.

Change-Id: I801ef71972b0c3d2aa04d682a3a94acfb27ac7ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23449
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Use an ARM specific GuestABI for ARM system calls.

Change-Id: I2d0d0a563355f43ed791ba2f2a1894e303cca994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23448
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Use a SPARC specific GuestABI for system calls.

Change-Id: I41996cada5ccde7b265e5315829ac6690da8902f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23447
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Introduce a BitUnion for the CCR register.

This avoids opaque masks when accessing fields of this register.

Change-Id: If20d82c7c6401e6b1b35bb6d2c69542a56e2fb45
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23446
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Introduce constants for pseudo integer registers.

These are "integer" registers which are renamed, but which aren't
normally considered integer registers by the ISA. They had been indexed
by adding an opaque constant to the number of official integer
registers which obscured what they were, and was also fragile and
invited mistakes.

Change-Id: Idab8cf4d889682b98c7c81a00d9a92d8e3bb3a05
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23445
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Get rid of some commented out constants.

Change-Id: Ie2a223f5f969402a03b924ef767eddbcc14bf312
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23444
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Define a local ABI for system calls.

These ABIs (one 32 bit and one 64 bit) take advantage of the
GenericSyscallABI and X86Linux::SyscallABI partial ABIs set up earlier.

This removes x86's dependence on the getSyscallArg and setSyscallReturn
Process methods.

Change-Id: Ia07834cea1afa827d77e590af5397e2a1e0e2099
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23443
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: In X86 linux, system calls simply return their result in a register.

We can partially define an x86 linux system call ABI which handles the
return value. Argument gathering would be handled elsewhere.

Change-Id: Id2841dea39aa2ea3fc42e1a0fb70ff4e477b3671
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23442
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add GenericSyscallABI structs which can be used by the ISAs.

It's very common for system call arguments to be passed in a sequence
of registers, one argument per register. To avoid having that
implementation repeated over and over across the various ISAs and OSes,
these partial ABI implementations provide that mechanism they can just
pull in. They would need to define the sequence of registers to use,
and these would take care of the rest.

Unlike the temporary DefaultSyscallABI which defers to the Process
classes, these read registers from the ThreadContext directly.

Change-Id: Ic72eb8d784ecf4711b5eec76d958a87c70850fce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23441
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Make SyscallReturn handle extra/"pseudo" return registers.

Avoid special casing them in the system calls themselves.

Change-Id: I735f8e6fdff164c66e3f1386aed3fc9b107ea45f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23440
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Convert MIPS specific syscalls to Guest ABI.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I7e7c49e885a8c3395f2e6ca361c228bce3691dbe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23205
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Convert POWER specific syscalls to Guest ABI.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Icdf41a0e2bf910813250249eff7a9f1b54c60b22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23204
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Convert SPARC specific syscalls to Guest ABI.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I144fc3fb0e408380294ea91fefa881494f44098b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23203
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Convert RISCV specific syscalls to Guest ABI.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I1a7041ba890f5f69d5506583c658ae6a777b5daf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23202
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Convert x86 specific syscalls to GuestABI.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I2ad9c0ac72eb875f30ece27d58549244de84e191
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23201
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Convert ARM specific syscalls to GuestABI.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I1055b72f34ea9e0bcce465492bd45b6fb0c36eef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23200
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Remove ISA specific KVM handling of the return from clone.

When the new thread context ctc is created, it should have a copy of
all the state in the original tc, including the original PC. This code
used to specially handle the KVM case by explicitly making this new
context return from the system call immediately by jumping right to
RCX which (assuming a particular instruction was used) is where user
mode should resume.

The first problem with this approach as far as I can tell is that the
CPU will still be in CPL0, ie supervisor mode, and will not have been
forced back into CPL3, ie user mode. This may not have any immediately
visible effect, but may down the line.

Second, this seems unnecessary. The non-special case code will advance
the PC beyond the instruction which triggered the system call. Then
once the new thread starts executing again, it will execute sysret and
return to rcx naturally, just like the original thread will.

The only observed difference is that when executing a gem5 instruction,
the IP is set to the currently executing instruction, and so to avoid
the new context from re-executing the system call, the PC needs to be
advanced. When calling in from KVM, the instruction has already been
"completed", and so the IP should *not* be advanced.

Also note that when reading the PCState object in KVM, it doesn't
figure out where the next instruction is and so NPC is just one
ExtMachInst sized blob later on. Advancing the PC will just move to
an address 8 bytes later, which is very unlikely to be what you want.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0d97f66e64ce39b13d6700dcf3d7da88d6fe0048
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23199
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Convert clone to GuestABI and define a cloneBackwardsFunc.

cloneBackwardsFunc takes its arguments in the order specified for
ARM and RISCV. Because of the new GuestABI mechanism, it can be a
simple wrapper around the normal clone implementation without the need
for #ifdefs.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Iff1ffd6774b9162185a124585e9507a5bdbc46f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23198
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Use variadic GuestABI arguments in a few additional syscalls.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ib2f193e7409859469c853e11f121eba82b3c0ddc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23196
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Implement translateFunctional.

Change-Id: I039a09879a50a7d50329c01c337cfa5674c34fae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26549
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

mips: Implement translateFunctional.

Change-Id: I32df1b3b12a0adee4457b78c735936c4c73da048
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26548
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

config,arch,cpu,kern,sim: Extract kernel information from System.

Information about what kernel to load and how to load it was built
into the System object and its subclasses. That overloaded the System
object and made it responsible for too many things, and also was
somewhat awkward when working with SE mode which doesn't have a kernel.

This change extracts the kernel and information related to it from the
System object and puts into into a OsKernel or Workload object.
Currently the idea of a "Workload" to run and a kernel are a bit
muddled, an unfortunate carry-over from the original code. It's also an
implication of trying not to make too sweeping of a change, and to
minimize the number of times configs need to change, ie avoiding
creating a "kernel" parameter which would shortly thereafter be
renamed to "workload".

In future changes, the ideas of a kernel and a workload will be
disentangled, and workloads will be expanded to include emulated
operating systems which shephard and contain Process-es for syscall
emulation.

This change was originally split into pieces to make reviewing it
easier. Those reviews are here:

https: //gem5-review.googlesource.com/c/public/gem5/+/22243
https: //gem5-review.googlesource.com/c/public/gem5/+/24144
https: //gem5-review.googlesource.com/c/public/gem5/+/24145
https: //gem5-review.googlesource.com/c/public/gem5/+/24146
https: //gem5-review.googlesource.com/c/public/gem5/+/24147
https: //gem5-review.googlesource.com/c/public/gem5/+/24286

Change-Id: Ia3d863db276a023b6a2c7ee7a656d8142ff75589
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26466
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Correct the Ids and names of the PMU events

0x0C is the PC_WRITE_RETIRED event and 0x21 is the RetiredBranches.

Change-Id: I5f1173ff06f67b6a46e8a914c8acb9639edf67ec
Signed-off-by: Andriani Mappoura <andriani.mappoura@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26485
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove unnecessary RegIndex set for VSTR VFP inst

vd index is already set at the beginning of the
decodeExtensionRegLoadStore function.

Change-Id: Ic8cea43cf3a60881823195ef6da0bbda6940f1cf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23950
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch-arm: GenericTimer arch regs, perms/trapping

This patch enhances the Generic Timer architected registers handling:

- Reordering of miscregs for easier switch/case ranges
- Implement _EL12 reg versions for E2H environments
- AArch32/64 EL0/EL1/EL2 arch compliant trapping for all registers
    + Rely on CNTKCTL and CNTHCTL access controls
- UNDEFINED behaviour from EL0(NS)
- EL1(S) timer traps to EL3 when SCR.ST == 0

Change-Id: I4f018e103cf8f7323060516121838f90278b1c3e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25307
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Refactor GenericTimer

The GenericTimer specification includes a global component for
a universal view of time: the System Counter.

If both per-PE architected and memory-mapped timers are instantiated
in a system, they must both share the same counter. SystemCounter is
promoted to be an independent SimObject, which is now shared by
implementations.

The SystemCounter may be controlled/accessed through the memory-mapped
counter module in the system level implementation. This provides
control (CNTControlBase) and status (CNTReadBase) register frames. The
counter module is now implemented as part of GenericTimerMem.

Frequency changes occur through writes to an active CNTFID or to
CNTCR.EN as per the architecture. Low-high and high-low transitions are
delayed until suitable thresholds, where the counter value is a divisor
of the increment given the new frequency.
Due to changes in frequency, timers need to be notifies to be
rescheduled their counter limit events based on CompareValue/TimerValue.
A new SystemCounterListener interface is provided to achieve
correctness.

CNTFRQ is no longer able to modify the global frequency. PEs may
use this to modify their register view of the former, but they should
not affect the global value. These two should be consistent.

With frequency changes, counter value needs to be stored to track
contributions from different frequency epochs. This is now handled
on epoch change, counter disable and register access.

References to all GenericTimer model components are now provided as
part of the documentation.

VExpress_GEM5_Base is updated with the new model configuration.

Change-Id: I9a991836cacd84a5bc09e5d5275191fcae9ed84b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25306
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Hint the compiler to inline getArmSystem

By defining it in the header we are hinting the compiler to inline
the method

Change-Id: I132964bf8b8c0b5d5eb28868f15723177d049d38
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26323
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

arch-arm: Speedup ARM execution by avoiding expensive RTTI check

getArmSystem is the building block for a lot of ArmSystem getters
a client can use to check for a specific feature.
This method is called very often during simulation and it is basically
casting a System pointer into an ArmSystem pointer.
To do so, it is using dynamic casting to check if the system is really
an ArmSystem. This is very expensive and usually not needed.

The only chance arm code would use a non ArmSystem is when in SE mode.
But if that's the case, we can just replace the assertion with a

assert(FullSystem).

Testing Linux boot with this patch provides a speedup of nearly 2x!
(atomic mode).

This is partially related to:

JIRA: https://gem5.atlassian.net/browse/GEM5-337

Since the PAuth patch changed the purifyTagged helper (on the critical
path of simulation) to rely more heavilly on getArmSystem (via
ArmSystem:: static methods)

Change-Id: Idbf079548ffe03513b4fc58c76f0d69613952a50
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25964
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: python3 "/" will always produce a float

"/" was ambiguous in python2 and was producing a floor (integer)
division if the operands were int or long.
In python3 "/" will always produce a float which makes it unsuitable
in cases where an integer is expected

PEP238: https://www.python.org/dev/peps/pep-0238/

Change-Id: I481cf1e9c0f95a6f47ecf6539eee0c9bcaf31e17
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26247
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Replace basestring with six.string_types

Change-Id: I914adb545fe82efed386085d2f191ec54efccbf3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26246
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Replace __metaclass__ with six.add_metaclass

Change-Id: I45f73b71266c1edf9c4ec521d58db779b16bd591
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26245
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: string.join has been removed in python3

In general string methods are deprecated in favour of str ones

Change-Id: Ifba04e0b70be29e5a82a67cf11837f740de57e32
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26244
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: The new module has been removed in python3

new.instance was used to instantiate a method bypassing the __init__
interface This patch is doing things properly by importing the LRTable
so that the LRParser interface is respected

Change-Id: I0b0ce184ef5ac297af40289a2896962c9a967a71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26243
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Make meta class declarations Python 3 safe

Python 2.x and Python 3 use different meta class syntax. Fix this by
implementing meta classes using the add_metaclass decorator in the six
Python library.

Due to the way meta classes are implemented in six,
MetaParamValue.__new__ seems to be called twice for some classes. This
triggers an assertion which when param that checks that Param types
have only been registered once. I have turned this assertion into a
warning.

The assertion was triggered in params.CheckedInt and params.Enum. It
seems like the cause of the issue is that these classes have their own
meta classes (CheckedIntType and MetaEnum) that inherit from
MetaParamValue and a base class (ParamValue) that also inherits from
MetaParamValue.

Change-Id: I5dea08bf0558cfca57897a124cb131c78114e59e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26083
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem: Change some default values in the Request class.

These values are more abnormal than the 0s they replace, and so it
would be more obvious when something is accidentally left
uninitialized.

Change-Id: Ie7f14abe9e22f9df1ff238f29d4a783c890f4a20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26237
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch: Remove the "process.hh" switching header file.

This file is not included anywhere in gem5.

Change-Id: I936ac482b9b1d527f141267d0dfb86dda3de34df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26235
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Fix relative import in non-package in configs

Fix "ValueError: Attempted relative import in non-package"

Python "compilation" fails when running, among other configs:
    ./build/X86/gem5.fast ./configs/example/ruby_random_test.py

The files in the configs/folder_name folder that are not named
"folder_name.py" are not packages, and thus Python does not allow
relative imports in them.

This fixes the bug reported in
    https://gem5.atlassian.net/projects/GEM5/issues/GEM5-188

Change-Id: Ic8befc30e4cff1d6e8d2f5db1b7f9b89b0fc1395
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24163
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base,cpu,sim: Stop including arch/vtophys.hh when not using vtophys.

These #includes are leftovers from when vtophys was used much more
prevalently in the simulator.

Change-Id: Ib2e947bc95f1e21acc9eff8e856f38b31d3fd933
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26225
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu: Get rid of unused/unimplemented vtophys variants.

The version of vtophys which didn't take a ThreadContext had only been
implemented on Alpha which has since been removed, so this version of
the function was completely unimplemented and never used.

This change also gets rid of the dbg_vtophys which was sometimes
implemented but also never used, and takes the opportunity to fix up
some style problems in some of the vtophys arch files.

Change-Id: Ie10f881f8ce08c7188e71805357cf3264be4c81a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26224
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Implement translateFunctional in the TLB class.

This is a slightly munged version of vtophys, but which returns faults
like the normal translate functions if the address is malformed. It
attempts to return an approximately correct fault if the translation
isn't found, but since SPARC doesn't have hardware managed TLBs that
has to be an approximation.

translateFunctional also ignores permissions type checks (unless
they're built into the "lookup" method?) in line with vtophys type
semantics. The idea is that translateFunctional is used in conjunction
with functional accesses, and those are intended to reach beyond
normal barriers/boundaries to give unfettered access to the system for
debugging or setup purposes.

Change-Id: I000d9c31877b82043489792de037e7d664914fa9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26404
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Clean up condcodes.hh slightly.

Correct some minor style issues, make the functions static, and use the
single bit version of bits.

Change-Id: I4708961745a33caabecfbb06f8113ce8980e399e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26424
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Delete some commented out code in the TLB.

Change-Id: I80c455403422ec35bafa1f3ed86628f8327d1da0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26403
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

arch,cpu,gpu-compute,mem: Remove asid from Request objects.

This is passed around a lot and set all over the place (usually to 0),
but it's never actually used for anything.

Change-Id: I38ca08387beabeaf9e339b4915ec7eba9e19eecb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26232
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Merge the virtual Request constructors.

The only difference was whether the the atomic op functor was accepted
as an argument. If it wasn't, setVirt would be called without an op
functor argument where it will default to nullptr.

This change deletes the constructor which doesn't take an atomic op
functor and in the other defaults the functor to nullptr. Functionally
nothing changes, but the code is now simpler.

Change-Id: Iff06543b1046594df297344e16961ee9d0f0a373
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26231
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Get rid of one more unused Request constructor.

Also collapse setPhys, which is private, into the only caller which is
the Request constructor which takes a physical address.

Change-Id: I872c489cd168d7c364a57e26efce2350a3632c82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26230
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Get rid of another unused Request constructor.

This one took an explicit "time" value instead of using curTick().

Change-Id: I935ba1dfc194dcf156d7defedb6ce540db461ce4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26228
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Add default initializers to the fields in Request.

This avoids having to have bunches of uninteresting initializers in the
Request constructors, and accidentally forgetting to initialize any of
them.

Change-Id: If7a91fdf4aa6cd774f6f53474f55034ed6eda5f0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26227
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

base: Disable a warning in hdf5.cc which comes from an external header.

This warning comes from an external header which we don't have the
ability to fix directly. We can disable it in hdf5.cc specifically
which should keep things building without defeating the warning in
cases where we could fix it.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-365

Change-Id: Ie1f4d91340e68cee7514beab9d03bba1d1c9bb38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26325
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Optimize and otherwise fix a couple of functions in intmath.hh.

As described in the Jira issue, this replaces the implementation of
isPowerOf2() and power(). It also revamps floorLog2 so that there only
needs to be one implementation and no assumptions about how big certain
types are.

The way power() used to work was to raise a number n to an exponent e
by multiplying n times itself e times. As a warning in this function
explains, this can be quite slow for large e. A much more efficient
way to raise a number to an exponent is to square n over and over, and
to multiply in the current square if that bit of e is set.

n ^ 15 = (n^1) * (n^2) * (n^4) * (n^8)
n^8 = (n^4)^2
n^4 = (n^2)^2
n^2 = n^2
n^1 = n

So that takes 6 multiplications, n^2, (n^2)^2, (n^4)^2, and then each
multipy to compute the final result, instead of 14.

The difference is more pronounced for larger exponents, although you'd
quickly start to overflow a uint64_t.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-140

Change-Id: I0ae05aeba1b5882d2a616613b1679e6206b4cbfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26164
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Get rid of an unused Request constructor.

This constructor took a physical address and a PC. After deleting it
all ISAs still compile.

Change-Id: I25f404f80ce7e995688165dc86ac8899da7aa919
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26226
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Switch away from some fringe Request constructors.

These are only used in these two files, one each, and pass one dummy
argument with a default value and one extra argument with an actual
value compared to the more common constructors.

Instead, switch to constructors without those two arguments and set the
one extra value explicitly after construction.

The constructor will likely be inlined, and merged with this additional
assignment.

Change-Id: I75ca539d5ca95b57b4f4322ffa050af2031544dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26229
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem: Remove the version of the FS translating port proxy with no tc.

This version is not used and is the only remaining consumer of the
vtophys variant with no ThreadContext.

Change-Id: I8cb870b841fe064cee121e4930cb163d2ec7628f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26223
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove unused getArmSystem helper

Change-Id: Ifbb1619fa1cfd6c6cda5c390889c423dbe62dc7e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25963
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Minor Ruby Prefetcher fixes

Minor fixes to the Ruby stride prefetcher. This includes removing unused
statistics and changing where/when some statistics are updated.

Change-Id: If758bf009f53fad277cb3cd754d57a0b10737599
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24363
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Track message based interrupt cleanup functions in sender state.

This makes sure the completion function follows the packet, and allows
multiple packets to be in flight at once without the functions
overwritting each other.

Change-Id: Ic49c7b646d56b32c0453931942ee22ae07828bb6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26163
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu,mem: Replace the mmmapped IPR mechanism with local accesses.

The new local access mechanism installs a callback in the request which
implements what the mmapped IPR was doing. That avoids having to have
stubs in ISAs that don't have mmapped IPRs, avoids having to encode
what to do to communicate from the TLB and the mmapped IPR functions,
and gets rid of another global ISA interface function and header files.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I772c2ae2ca3830a4486919ce9804560c0f2d596a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23188
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Disable the unused-value warning in clang for pybind.

pybind internally uses a construct which initializes an array of bools
as a way to run a function on each member of a parameter pack. It then
discards the array since it was just trying to run the function. This
triggers a warning in clang 11 called unused-value which breaks the
build.

This change adds some pragmas to the pybind11.h header which disable
that warning while in pybind11 which is less intrusive than trying to
fix the false positive warning, and better than disabling the warning
universally. Since g++ and clang++ will complain if they see this
pragma guarded by the other's name, these pragmas are also surrounded
by ifdefs which should make them only visible to clang.

Change-Id: Ie9b5c65e8cadc8b96fbc1bd7971bed4a61c4340d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25228
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

tests,misc: Created presubmit.yaml Google Cloud Build files

This will replicate kokoro on Google Cloud services. At present, this
can be run via execution of `gcloud builds submit--config
cloudbuild_presubmit.yaml`.

Jira: https://gem5.atlassian.net/browse/GEM5-271
Change-Id: I5a71ef7fdbe5546b4e6970e4f4641f9e14cc640b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24543
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: simple_ruby_test's valid_host is X86 only

This is because the binary is dynamically linked thus it can run
on a x86 host only.

Change-Id: I7391414fdcd8f861f62e54c4d681e29360eb7443
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

python: Add a warning if pydot is not available.

Silently failing makes it hard to debug what happened. Add a warning.

Change-Id: Ia61b8de937bb254898726ad551fb5c894104d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26045
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Fix corrupted rename map in vector mode switching

This patch fixes the AArch32-AArch64 interprocessing issue introduced in
3d15150d cpu, arch, arch-arm: Wire unused VecElem code in the O3 model.

When O3CPU switches vector renaming mode, architectural-physical mapping
and physical free list are switched in the following way so that content
of vectors has no change from software view:

Case 1. Full mode -> Elem mode (AArch64 -> AArch32):
1.1. Split vector-vector mapping into element-element mapping.
1.2. Split vectors in free list into elements.

Case 2. Elem mode -> Full mode (AArch32 -> AArch64):
2.1. Move content of all N*M mapped physical elements to first N*M
     physical elements in architectural order (N = number of
     architectural vectors, M = number of elements per vector).
2.2. Map N architectural vectors to first N physical vectors (i.e.
     initial mapping in full mode).
2.3. Place remaining physical vectors in free list (i.e. initial free
     list in full mode).

Previous gem5 revision misses step 2.2 when AArch32->AArch64 switch.
The wrong mapping will lead to the situation in which a physical vector
is assigned twice to a same architectural vector without being freed.
Once this occurs, the physical vector will not be freed anymore, since
it is treated as a special register (e.g. zero or misc) by O3CPU's
renaming logic. Eventually O3CPU will either stall forever when all
physical vectors get stuck, or trigger the panic condition "The free
list has lost vector registers" when AArch64->AArch32 switch. This patch
adds the missing step and fixes the issue.

Change-Id: I32233635c28763260bcbb776b52ed198a9abace9
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Signed-off-by: Howard Wang <Howard.Wang@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25743
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added MIPS ISA test to learning_gem5/part1_tests.py

Running these tests on the MIPS ISA was part of the old scons-based
scripts and was not present in the Python testlib framework (those
executed via `tests/main.py`). This has been migrated.

Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: Id87022e99ea83768710fb96b55136f777182fd43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25803
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Updated 'hello_se' to include other CPU types

Some tests are ignored due to bugs in the test executables. This has
been logged in the Jira issue here:
https://gem5.atlassian.net/browse/GEM5-356

Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: Idd2db04175333d1c24604e736df7833c1e441480
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25063
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

cpu: update info related direction into BP if mispredicted.

Update direction info of a branch into BP if, the branch is not
found in the target buffer. Therefore, this  updated direction is
used to squash the branch later on. Previously, some mispredicted
branches were not sqaushed as the BP had old info.

Reported-by: Dimitrios Chasapis
Change-Id: I4be2eb706edc5ffa9935948fb52a01667286c721
jira-issue: https://gem5.atlassian.net/browse/GEM5-355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25903
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Dimitrios Chasapis <k4s4s.heavener@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add missing UARTs (PL011) to VExpress_GEM5 platform

This uarts are present in the VE RS1 memory map

Change-Id: I894f401bf524dfd46f6a663980436d8e12e0cd69
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25986
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add trusted SP805 to VExpress_GEM5 platform

This watchdog is present in the VE RS2 memory map when security is
enabled.

Change-Id: I732debf4d3e987a351cc09ca7206ef40b52ada41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25985
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add trusted SRAM memory to VExpress_GEM5 platform

This memory is present in the VE RS1 memory map when security is enabled

Change-Id: I2e4fb95c2124d6e60b556903acb17fc4b1dba1a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25984
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add flash0 memory to VExpress_GEM5 platform

This memory is present in the VE RS1 memory map

Change-Id: Ia00c802f137d8a82c93b984f4043ba9f7fd8027a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25983
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix argument handling sweep.py

Change-Id: I6dacbda19971e1c940d1798febb54d20f971c2bc
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25710
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Remove unnecessary exports from pybind enums

According to pybind documentation [1], enum entries use
.export_values() to export the enum entries into the parent
scope. However, strongly typed C++11 class enums are in their own
scope and therefore do not need to be exported.

[1]: https://pybind11.readthedocs.io/en/stable/classes.html#enume
rations-and-internal-types

Change-Id: I6181306b530d59eaedcb3daf9cab0a03d01d56f4
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25709
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Migrated 51.memcheck scons-based tests to testlib

"configs/example/memcheck.py" has been modified to keep the generated
"memcheck.cfg" in the "configs/example" directory. This generated file
is now ignored by git.

Change-Id: I19fab96419aa29e851139e759cc88b96465dd668
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25943
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: PL031, fix AMBA ID and clock names

This patch fixes the AMBA ID of the PL031 RTC. It also adds the
"clock-names" property to its auto-DTB generation. This fixes and
enables correct probing from Linux.

Change-Id: I331bfa81664f57a35f21f35d658772eb40380e35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25432
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

learning-gem5: Use zero initialization in hello_goodbye test

This is likely fixing:

JIRA: https://gem5.atlassian.net/browse/GEM5-328

the exitCause method was randomically printing an invalid string coming
from a non 0 terminated char buffer, whose pointer is provided via the
exitSimLoop.
By doing zero-initialization we make sure last character is '\0'.

Change-Id: I514a9bd240a0d5489ce9652ad14289f834752abe
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25987
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Fixed .testignore from 'arch64' to 'aarch64'

Entries in `tests/gem5/.testignore` which were ignoring insttest tests,
were stating the host system as 'arch64' instead of 'aarch64'. This has
been fixed.

Change-Id: Ib90bd89e0544d225afc012fefca98db0ea2d8dd0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25845
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arm: Expose the constants which select a semihosting operation.

Give these constants meaningful names instead of opaque constants only
visible in the .cc file.

Change-Id: Ib88912dae79960f785099c236c337db52a69d563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25945
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Use a const ThreadContext * and readMiscRegNoEffect in places.

Unlike readMiscReg, readMiscRegNoEffect won't have any read related
side effects and so can be used on a const ThreadContext. Also, using
a const ThreadContext * in a few functions which don't actually intend
to change state makes them usable in more situations.

Change-Id: I4fe538ba1158b25f512d3cccd779e12f6c91da6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25944
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,arch: Move code that waits for a GDB connection to startup().

Currently the System class has a mechanism to wait for a GDB connection
for each CPU which has requested it through one of its parameters.
Unfortunately, not every thread context/CPU will be ready for GDB at
that point, particularly considering that in an FS simulation the
kernel won't have been read so there will be no symbols, none of the
registers or the entry point will have been set.

Also in the fast models, the CPUs haven't had a chance to initialize
themselves enough by that point to respond to the API calls which are
used to implement GDB support.

Change-Id: If27cb3e0259a1f67599ab0493695b2f8af640d8e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24963
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: change the location of BTBlookup

BTBlookup should be done only if BTB is used, previously
this stat was updated for indirector predictor as well.

https: //gem5.atlassian.net/browse/GEM5-338
Change-Id: I20695dc7a8677d4fd0c4ae9f4f7d279387d5ad62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25625
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Updated tests/.gitignore to ignore test resources

Tests run via main.py create some temp resources. These are now ignored.

Change-Id: I63e2b7e1d70f8813e12c2e538a633046d614f1d2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24324
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

Merge "misc: merge branch 'release-staging-v19.0.0.0' into develop" into develop

tests: Removed unneeded 02.insttest data

This test has been migrated to be run via `./main.py`.

Change-Id: I3608306da62c301bf0ebea6c5fbd1eebac703467
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25844
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>