Florent Kermarrec [Tue, 2 Jun 2020 13:05:46 +0000 (15:05 +0200)]
CHANGES: update and change added features order.
Florent Kermarrec [Tue, 2 Jun 2020 11:51:44 +0000 (13:51 +0200)]
test: update.
Florent Kermarrec [Tue, 2 Jun 2020 11:44:23 +0000 (13:44 +0200)]
targets: rename gateware-toolchain parameter to toolchain.
Florent Kermarrec [Tue, 2 Jun 2020 11:34:44 +0000 (13:34 +0200)]
targets/arty: integrate symbiflow changes to avoid duplication.
Florent Kermarrec [Tue, 2 Jun 2020 11:34:09 +0000 (13:34 +0200)]
build/generic_platform: add default_clk constraints only when used.
Florent Kermarrec [Tue, 2 Jun 2020 10:36:02 +0000 (12:36 +0200)]
build/xilinx/symbiflow: reuse .xdc generation from Vivado to avoid duplication, fix copyright.
Florent Kermarrec [Tue, 2 Jun 2020 10:18:12 +0000 (12:18 +0200)]
boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform.
Florent Kermarrec [Tue, 2 Jun 2020 10:15:38 +0000 (12:15 +0200)]
xilinx/simbiflow: add simple symbiflow_device re-mapping.
enjoy-digital [Tue, 2 Jun 2020 09:55:33 +0000 (11:55 +0200)]
Merge pull request #551 from antmicro/mglb/symbiflow-toolchain-xilinx-7-support
Add Symbiflow toolchain support for Xilinx 7-series
Tim Ansell [Mon, 1 Jun 2020 22:23:03 +0000 (15:23 -0700)]
Merge pull request #552 from ozbenh/memspeed-long
sdram: Use unsigned long for memory test
Benjamin Herrenschmidt [Mon, 1 Jun 2020 22:08:42 +0000 (08:08 +1000)]
sdram: Use unsigned long for memory test
This makes it twice as fast on 64-bit CPUs when using a 64-bit bus :-)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Mariusz Glebocki [Mon, 1 Jun 2020 11:58:44 +0000 (13:58 +0200)]
test/test_targets: add arty_symbiflow
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
Mariusz Glebocki [Mon, 1 Jun 2020 11:41:49 +0000 (13:41 +0200)]
targets: add arty_symbiflow
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
Mariusz Glebocki [Mon, 1 Jun 2020 11:40:32 +0000 (13:40 +0200)]
platforms: add arty_symbiflow
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
Mariusz Glebocki [Mon, 1 Jun 2020 11:39:33 +0000 (13:39 +0200)]
build/xilinx: add Symbiflow toolchain support
Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
enjoy-digital [Mon, 1 Jun 2020 19:17:40 +0000 (21:17 +0200)]
Merge pull request #550 from antmicro/jboc/spd-read
bios/litedram: Add command to verify SPD contents with the one used during generation
enjoy-digital [Mon, 1 Jun 2020 17:58:01 +0000 (19:58 +0200)]
Merge pull request #549 from antmicro/mglb/fix-vivado-yosys
build/xilinx: do not assume build name is "top"
Mariusz Glebocki [Sat, 23 May 2020 10:57:55 +0000 (12:57 +0200)]
build/xilinx: do not assume build name is "top"
enjoy-digital [Mon, 1 Jun 2020 09:37:05 +0000 (11:37 +0200)]
Merge pull request #547 from gsomlo/gls-fix-sdcard-status
soc/software/litesdcard: update for response register back to 128 bits
Florent Kermarrec [Mon, 1 Jun 2020 09:03:08 +0000 (11:03 +0200)]
interconnect/wishbone/DownConverter: skip accesses on slave when sel==0 and simplify.
Improve efficiency for 64-bit CPU accessing only the 32-bit LSBs/MSBs.
Florent Kermarrec [Mon, 1 Jun 2020 08:58:45 +0000 (10:58 +0200)]
soc/interconnect/axi: generate wishbone.sel for reads.
Florent Kermarrec [Mon, 1 Jun 2020 08:01:14 +0000 (10:01 +0200)]
soc/software: only keep 32-bit CSR alignment support.
64-bit support was added for 64-bit CPU because of limitation of the hardware
on CSR accesses. Now that the Wihhbone2CSR bus handles wishbone.sel, this is no
longer required.
Gabriel Somlo [Sat, 30 May 2020 00:42:49 +0000 (20:42 -0400)]
soc/software/litesdcard: update for response register back to 128 bits
The additional (17th) byte returned via the response register was
ignored by software (bios and kernel), so LiteSDCard was updated
to only return the (original, useful) 128 bits.
This patch updates the LiteSDCard code in the LiteX bios to only
expect those 128 bits, and to do so in a manner that's portable
across CSR data widths and alignments.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Sat, 30 May 2020 13:21:32 +0000 (15:21 +0200)]
wishbone/wishbone2csr: use wishbone.sel on CSR write.
CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.
Florent Kermarrec [Fri, 29 May 2020 18:15:02 +0000 (20:15 +0200)]
soc/software/litesdcard: use new send register to send command and remove CSR8_CMD_FIX.
Florent Kermarrec [Fri, 29 May 2020 17:36:33 +0000 (19:36 +0200)]
platforms/nexys_video: add spisdcard pins.
Florent Kermarrec [Fri, 29 May 2020 17:26:29 +0000 (19:26 +0200)]
targets/nexys_video: add spi-sdcard and sdcard support.
Florent Kermarrec [Fri, 29 May 2020 17:26:03 +0000 (19:26 +0200)]
plaforms/nexys_video: keep up to date with litex-boards.
Florent Kermarrec [Fri, 29 May 2020 17:22:35 +0000 (19:22 +0200)]
targets: simplify Ethernet/Etherbone integration on targets with both.
Florent Kermarrec [Fri, 29 May 2020 16:51:24 +0000 (18:51 +0200)]
bios/cmds/cmd_litesdcard: rewrite comments/descriptions.
Florent Kermarrec [Fri, 29 May 2020 16:40:54 +0000 (18:40 +0200)]
bios/main: replace / with -.
enjoy-digital [Fri, 29 May 2020 16:32:30 +0000 (18:32 +0200)]
Merge pull request #545 from gsomlo/gls-fix-mmptr
csr: fix simple accessor alignment
Gabriel Somlo [Fri, 29 May 2020 15:54:10 +0000 (11:54 -0400)]
csr: fix simple accessor alignment
MMPTR should always follow CSR alignment, NOT CSR data width.
(the latter merely indicates how many bits within a MMPTR are
actually populated).
Fixup for commit #
4a5072a.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Fri, 29 May 2020 15:15:20 +0000 (17:15 +0200)]
software/liblitesdcard: replace hexdump with dump_bytes already available in the BIOS.
Florent Kermarrec [Fri, 29 May 2020 14:07:08 +0000 (16:07 +0200)]
soc/add_sdcard: add with_emulator parameter to use SDCard emulator (from Google Project Vault) and integrate it in litex_sim.
Jędrzej Boczar [Fri, 29 May 2020 13:14:54 +0000 (15:14 +0200)]
bios/litedram: add option to verify SPD EEPROM memory contents
Jędrzej Boczar [Fri, 29 May 2020 12:56:56 +0000 (14:56 +0200)]
build/sim/spdeeprom: use hex format when loading from file
Florent Kermarrec [Fri, 29 May 2020 08:40:17 +0000 (10:40 +0200)]
setup.py: add litex_jtag_uart and litex_crossover_uart to console_scripts.
enjoy-digital [Thu, 28 May 2020 14:46:34 +0000 (16:46 +0200)]
Merge pull request #543 from antmicro/jboc/eeprom-sim
litex/build/sim: add module for simulating SPD EEPROM
Florent Kermarrec [Thu, 28 May 2020 13:31:33 +0000 (15:31 +0200)]
targets/nexys4ddr: fix sdcard assert.
Florent Kermarrec [Thu, 28 May 2020 13:05:24 +0000 (15:05 +0200)]
bios: add main bus and csr bus infos, use KiB/GiB.
Jędrzej Boczar [Thu, 28 May 2020 10:10:25 +0000 (12:10 +0200)]
litex/build/sim: add module for simulating SPD EEPROM
Florent Kermarrec [Wed, 27 May 2020 21:26:26 +0000 (23:26 +0200)]
integration/soc/add_sdcard: always use 32-bit/512bytes memories (not sure this will change?) and allocate sdwrite/sdread regions dynamically.
Florent Kermarrec [Wed, 27 May 2020 21:18:15 +0000 (23:18 +0200)]
integration/soc: add add_sdcard method with integration code from nexys4ddr.
Even if not cleaned up yet, having it there will avoid duplications in targets.
Benjamin Herrenschmidt [Fri, 22 May 2020 07:53:20 +0000 (17:53 +1000)]
csr: Fix definition(s) of CSR_BASE in generated headers
CSR_BASE is currently defined twice. Once in mem.h as the base
of the CSR region in the SoC address space, and once in csr.h
as the base address for all CSRs.
This fixes two issues with those definitions:
- The mem.h one is unconditional which prevents an external
redefinition (which is useful under some circumstances such as
when using an address decoder outside of LiteX with a standalone
core).
- The csr.h one is actually the origin of the first CSR region
rather than the origin of the CSR region in the SoC space. They
are usually the same ... unless you don't have CSR bank 0 in
which case the csr.h one becomes different. This causes conflicts
with the mem.h definition and breaks projects using a standalone
cores.
The first one is fixed by adding the #ifndef/#endif around the
definition of the memory regions, the second one by passing the
csr_base to use to get_csr_header()
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 22 May 2020 07:37:37 +0000 (17:37 +1000)]
liblitedram/sdram: Add option to disable cdelay()
When running in sim, those delays can take a *long* time, which
isn't always necessary with the simulated litedram PHY.
This allows system.h to optionally set CONFIG_SIM_DISABLE_DELAYS
which causes cdelay to do nothing.
This is especially useful when using a verilated litedram inside
a bigger/slower simulated design as to not spend a huge amount
of time going through the initializations.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Florent Kermarrec [Wed, 27 May 2020 18:00:10 +0000 (20:00 +0200)]
cpu/serv: add variants.
Florent Kermarrec [Wed, 27 May 2020 17:59:54 +0000 (19:59 +0200)]
soc/integration/export: add optional csr_base parameter.
Florent Kermarrec [Wed, 27 May 2020 17:54:52 +0000 (19:54 +0200)]
build/sim/verilator: add regular_comb parameter (that defaults to False) and pass it to get_verilog.
enjoy-digital [Wed, 27 May 2020 17:04:18 +0000 (19:04 +0200)]
Merge pull request #542 from gsomlo/gls-sdcard-followup
software/bios: fixup sdclk command
enjoy-digital [Wed, 27 May 2020 17:03:50 +0000 (19:03 +0200)]
Merge pull request #541 from antmicro/jboc/spd-read
Add support for I2C to read SPD EEPROM
Florent Kermarrec [Wed, 27 May 2020 16:45:07 +0000 (18:45 +0200)]
CHANGES: document deprecated/moved modules.
Florent Kermarrec [Wed, 27 May 2020 16:40:45 +0000 (18:40 +0200)]
soc/core/uart: move WishboneStreamingBridge in it and rename to Stream2Wishbone.
Gabriel Somlo [Wed, 27 May 2020 16:38:59 +0000 (12:38 -0400)]
software/bios: fixup sdclk command
Florent Kermarrec [Wed, 27 May 2020 16:15:05 +0000 (18:15 +0200)]
interconnect/wishbone: integrate Wishbone2CSR.
Florent Kermarrec [Wed, 27 May 2020 16:13:57 +0000 (18:13 +0200)]
interconnect/csr_bus: add separators.
Florent Kermarrec [Wed, 27 May 2020 16:04:08 +0000 (18:04 +0200)]
interconnect/wishbone: remove CSRBank (probably not used by anyone).
Florent Kermarrec [Wed, 27 May 2020 15:59:05 +0000 (17:59 +0200)]
interconnect/wishbone: add separators and move SDRAM/Cache.
Florent Kermarrec [Wed, 27 May 2020 15:18:31 +0000 (17:18 +0200)]
interconnect/wishbone: simplify DownConverter.
Jędrzej Boczar [Wed, 27 May 2020 13:13:16 +0000 (15:13 +0200)]
bios: move I2C from liblitedram to libbase
Florent Kermarrec [Wed, 27 May 2020 13:26:56 +0000 (15:26 +0200)]
interconnect/wishbone: remove UpConverter (probably not used by anyone and would need to be rewritten).
We'll provide a better implementation if this is useful.
Florent Kermarrec [Wed, 27 May 2020 13:16:30 +0000 (15:16 +0200)]
tools/litex_sim: switch to SoCCore/add_sdram instead of SoCSDRAM.
Florent Kermarrec [Wed, 27 May 2020 12:09:05 +0000 (14:09 +0200)]
targets/nexys4ddr: update add_sdcard method.
Tested with:
sdinit
sdtestwrite 0x10 foobar
sdtestread 0x10
Jędrzej Boczar [Wed, 27 May 2020 06:52:24 +0000 (08:52 +0200)]
bios/sdram: expose I2C functions
Florent Kermarrec [Wed, 27 May 2020 07:00:43 +0000 (09:00 +0200)]
CHANGES: add JTAG UART.
Florent Kermarrec [Wed, 27 May 2020 06:59:12 +0000 (08:59 +0200)]
tools/litex_jtag_uart: add openocd config and telnet port parameters.
Florent Kermarrec [Tue, 26 May 2020 07:36:44 +0000 (09:36 +0200)]
cpus: remove common cpu variants/extensions definition and simplify variant check.
Having common cpu variants/extensions has no real additional value since we are supporting
very various CPUs where minimal/standard/full have different meanings. Checking against
common variants/extensions has also cause more issues recently when adding new CPUs than
the additional value it was supported to provide.
So let's just simplify things: a CPU provide the supported variants and we just check
against that.
Florent Kermarrec [Tue, 26 May 2020 06:51:33 +0000 (08:51 +0200)]
cpu/microwatt: add standard+ghdl variant that uses GHDL Yosys plugin.
Florent Kermarrec [Mon, 25 May 2020 10:20:01 +0000 (12:20 +0200)]
tools/litex_client/RemoteClient: add base_address parameter.
Useful when address translation is done in the SoC.
Florent Kermarrec [Mon, 25 May 2020 08:46:53 +0000 (10:46 +0200)]
cores/uart/RS232PHYTX: fix startbit duration by pre-loading phase_accumulator_tx to tuning_word.
enjoy-digital [Mon, 25 May 2020 08:33:58 +0000 (10:33 +0200)]
Merge pull request #539 from dayjaby/pr-fix_uart_startbit
Fix UART startbit: 1 cycle later
Florent Kermarrec [Mon, 25 May 2020 08:21:06 +0000 (10:21 +0200)]
tools: add litex_jtag_uart to create a virtual uart for the jtag uart.
Florent Kermarrec [Mon, 25 May 2020 08:19:16 +0000 (10:19 +0200)]
tools: rename litex_crossover poc to litex_crossover_uart, remove from setup for now.
David Jablonski [Sun, 24 May 2020 14:12:07 +0000 (16:12 +0200)]
fix uart startbit: 1 cycle later
Florent Kermarrec [Sun, 24 May 2020 08:55:25 +0000 (10:55 +0200)]
tools: add litex_crossover to be able to use lxterm (and serialboot) over a crossover UART (bridged over UART/Ethernet/PCIe/USB, etc...).
This is still a proof of concept but can be used/tested with:
lxsim --with-etherbone --uart-name=crossover --csr-csv=csr.csv
lxserver --udp --udp-ip=192.168.1.51
lxcrossover (will indicate the virtual_tty)
lxterm virtual_tty
Florent Kermarrec [Sun, 24 May 2020 07:52:56 +0000 (09:52 +0200)]
litex_sim: override uart_name to sim only for serial.
Using uart_name=crossover is useful to simulate crossover mode.
Florent Kermarrec [Sat, 23 May 2020 16:56:51 +0000 (18:56 +0200)]
CHANGES: update.
Florent Kermarrec [Sat, 23 May 2020 16:54:04 +0000 (18:54 +0200)]
integration/soc: remove TODO in header.
Florent Kermarrec [Sat, 23 May 2020 16:53:03 +0000 (18:53 +0200)]
cpu/cv32e40p: fix copyright year.
Florent Kermarrec [Fri, 22 May 2020 13:55:35 +0000 (15:55 +0200)]
cpu/cv32e40p: add copyright and improve indentation.
Florent Kermarrec [Fri, 22 May 2020 13:43:00 +0000 (15:43 +0200)]
litex_setup/pythondata-cpu-cv32e40p: clone in recursive mode.
enjoy-digital [Fri, 22 May 2020 11:44:10 +0000 (13:44 +0200)]
Merge pull request #535 from antmicro/arty-cv32e40p
Add support for the CV32E40P RISC-V CPU
enjoy-digital [Fri, 22 May 2020 10:28:00 +0000 (12:28 +0200)]
Merge pull request #538 from antmicro/fix_libbase
libbase: Include missing uart header
Mateusz Hołenko [Fri, 22 May 2020 09:43:18 +0000 (11:43 +0200)]
libbase: Include missing uart header
This fixes compilation on mor1kx.
Florent Kermarrec [Fri, 22 May 2020 06:42:02 +0000 (08:42 +0200)]
test/test_targets: update build_test.
Jędrzej Boczar [Thu, 21 May 2020 14:19:28 +0000 (16:19 +0200)]
litex_sim: load SPD data from files in hexdump format as printed in BIOS
Jędrzej Boczar [Thu, 21 May 2020 12:09:46 +0000 (14:09 +0200)]
bios/sdram: add BIOS command for reading SPD
Jędrzej Boczar [Thu, 21 May 2020 12:07:42 +0000 (14:07 +0200)]
bios/sdram: add firmware for reading SPD EEPROM
Florent Kermarrec [Thu, 21 May 2020 07:14:33 +0000 (09:14 +0200)]
platforms/targets: keep in sync with litex-boards.
- LedChaser.
- use of soc.build_name in load/flash bitstream.
Florent Kermarrec [Thu, 21 May 2020 07:06:29 +0000 (09:06 +0200)]
build/sim: rename dut to sim (for consistency with other builds).
Florent Kermarrec [Thu, 21 May 2020 07:05:45 +0000 (09:05 +0200)]
integration/soc: set build_name to platform.name when not specified.
Florent Kermarrec [Wed, 20 May 2020 21:20:45 +0000 (23:20 +0200)]
software/liblitespi: fix #endif location.
enjoy-digital [Wed, 20 May 2020 17:49:42 +0000 (19:49 +0200)]
Merge pull request #516 from antmicro/i2s_support_arty
Add I2S support to Arty
enjoy-digital [Wed, 20 May 2020 17:49:04 +0000 (19:49 +0200)]
Merge pull request #534 from fjullien/fix_litex_sim_warn
litex/sim: fix compiler warnings
Franck Jullien [Wed, 20 May 2020 13:34:19 +0000 (15:34 +0200)]
litex/sim: fix compiler warnings
Pawel Sagan [Thu, 12 Mar 2020 13:54:41 +0000 (14:54 +0100)]
Extend I2S capabilities
This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.
This required to rework the FSM.
Piotr Binkowski [Tue, 19 May 2020 15:05:25 +0000 (17:05 +0200)]
cores/cpu: add cv32e40p
Piotr Binkowski [Wed, 20 May 2020 11:35:18 +0000 (13:35 +0200)]
software/bios/isr: add support for cv32e40p
Piotr Binkowski [Wed, 20 May 2020 11:46:13 +0000 (13:46 +0200)]
litex_setup: add pythondata for cv32e40p
enjoy-digital [Wed, 20 May 2020 10:54:09 +0000 (12:54 +0200)]
Merge pull request #533 from antmicro/fix-dummy-bits-function-name
software/liblitespi/spiflash: fix dummy bits setup function name