Brian Paul [Mon, 3 Aug 2015 21:06:42 +0000 (15:06 -0600)]
mesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()
If the new texture unit is the current texture unit, we can return
before error checking.
Reviewed-by: Eric Anholt <eric@anholt.net>
Francisco Jerez [Tue, 4 Aug 2015 16:07:19 +0000 (19:07 +0300)]
i965/fs: Lower arithmetic instructions with register regions of unsupported width.
This extends the SIMD lowering pass to enforce the hardware limitation
that no directly-addressed source may read more than 2 physical GRFs.
One can easily go over this limit when doing 64-bit arithmetic
(e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice
to be able to just emit an instruction of the intended execution size
from the visitor and let the lowering pass deal with this restriction
transparently.
Some hardware arithmetic instructions are not handled here, including
all instructions that use the accumulator implicitly (which the SIMD
lowering pass deliberately doesn't handle), instructions with
non-per-channel sources (e.g. LINE or PLANE) and SEND-like
instructions, which need special handling most likely as virtual
opcodes.
Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Wed, 5 Aug 2015 13:29:30 +0000 (16:29 +0300)]
i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.
Otherwise it would crash on Gen8 with scalar VS. The issue can easily
be reproduced with the following patch, but I don't see any reason why
it wouldn't be possible to end up with an ATTR argument here even
without it.
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Connor Abbott <connor.w.abbott@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Tue, 4 Aug 2015 16:08:45 +0000 (19:08 +0300)]
i965/fs: Implement nir_op_imul/umul_high in terms of MULH.
And get rid of another no16() call.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Thu, 6 Aug 2015 11:04:00 +0000 (14:04 +0300)]
i965/fs: Lower the MULH virtual instruction.
Translate MULH into the MUL/MACH sequence. This does roughly the same
thing that nir_emit_alu() used to do but we can now handle 16-wide by
taking advantage of the SIMD lowering pass. The force_sechalf
workaround near the bottom is required because the SIMD lowering pass
will emit instructions with non-zero quarter control and we need to
make sure we avoid that on integer arithmetic instructions with
implicit accumulator access due to a known hardware bug on IVB.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 5 Aug 2015 13:47:18 +0000 (16:47 +0300)]
i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.
In order to make room for the code that will lower the MULH virtual
instruction. Also move the hardware generation and execution type
checks into the same branch, they are going to have to be different
for MULH.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 5 Aug 2015 13:43:37 +0000 (16:43 +0300)]
i965/fs: Lower 32x32 bit multiplication on BXT.
AFAIK BXT has the same annoying alignment limitation as CHV on the
source register regions of 32x32 bit MULs, give it the same treatment.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Tue, 4 Aug 2015 16:04:55 +0000 (19:04 +0300)]
i965: Define virtual instruction to calculate the high 32 bits of a multiply.
This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply. Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Michel Dänzer [Wed, 5 Aug 2015 09:17:14 +0000 (18:17 +0900)]
glsl: Initialize patch member of glsl_struct_field
There is apparently a subtle difference in C++ between
F f;
and
F f();
The former will use the default constructor. If there is no default
constructor specified, the compiler provides one that simply invokes the
default constructor for each field. For built-in basic types, the
default constructor does nothing. The later will, according to
http://stackoverflow.com/questions/
2417065/does-the-default-constructor-initialize-built-in-types)
perform value-initialization of the type. For built-in types this means
initializing to zero.
The per_vertex_accumulator constructor is:
per_vertex_accumulator::per_vertex_accumulator()
: fields(),
num_fields(0)
{
}
This is the second form of constructor, so the glsl_struct_field
objects were previously zero initialized. With the addition of an empty
default constructor in commit
7ac946e5, per_vertex_accumulator::fields
receive no initialization.
Fixes a bunch of random (mostly tessellation related) piglit failures
since commit
7ac946e5 ("glsl: Add constuctors for the common cases of
glsl_struct_field").
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91544
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Wed, 5 Aug 2015 10:27:24 +0000 (20:27 +1000)]
nir: add missing type to type_size_vec4()
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Eduardo Lima Mitev [Wed, 29 Jul 2015 14:01:27 +0000 (16:01 +0200)]
mesa: Add missing check of format and type in glTexSubImageXD on GLES 3.0
Argument validation for glTexSubImageXD is missing a check of format and type
against texture object's internal format when profile is OpenGL-ES 3.0+.
This patch also groups together all format and type checks on GLES into a
new function texture_format_error_check_gles(), to factorize similar
code in texture_format_error_check().
Fixes 2 dEQP tests:
* dEQP-GLES3.functional.negative_api.texture.texsubimage2d
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Eduardo Lima Mitev [Wed, 29 Jul 2015 14:01:28 +0000 (16:01 +0200)]
mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal format
Page 161 of the OpenGL-ES 3.1 (PDF) spec, and page 207 of the OpenGL 4.5 (PDF),
both on section '8.6. ALTERNATE TEXTURE IMAGE SPECIFICATION COMMANDS', states:
"An INVALID_ENUM error is generated if an invalid value is specified for
internalformat".
It is currently returning INVALID_OPERATION error because
_mesa_get_read_renderbuffer_for_format() is called before the internalformat
argument has been validated. To fix this, we move this call down the validation
process, after _mesa_base_tex_format() has been called. _mesa_base_tex_format()
effectively serves as a validator for the internal format.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.texture.copyteximage2d_invalid_format
Fixes 1 piglit test:
* spec@oes_compressed_etc1_rgb8_texture@basic
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Eduardo Lima Mitev [Wed, 29 Jul 2015 14:01:26 +0000 (16:01 +0200)]
mesa: Validate target before resolving tex obj in glTex(ture)SubImageXD
Currently, glTexSubImageXD attempt to resolve the texture object
(by calling _mesa_get_current_tex_object()) before validating the given
target. However, that method explicitly states that target must have been
validated before calling it, so it never returns a user error.
The target validation occurs later when texsubimage_error_check() is called.
This patch reorganizes target validation, taking it out from the error check
function and into a point before the texture object is resolved.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Eduardo Lima Mitev [Wed, 29 Jul 2015 14:01:23 +0000 (16:01 +0200)]
mesa: Fix errors values returned by glShaderBinary()
Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1,
and page 88 of the OpenGL 4.5 specs state:
"An INVALID_VALUE error is generated if count or length is negative.
An INVALID_ENUM error is generated if binaryformat is not a supported
format returned in SHADER_BINARY_FORMATS."
Currently, an INVALID_OPERATION error is returned for all cases.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.shader.shader_binary
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Tapani Pälli [Tue, 4 Aug 2015 08:09:35 +0000 (11:09 +0300)]
mesa: do not modify args when errors with GetProgramResourceName
Original purpose of these lines was to be more friendly against
GUI tools using the extension. However conformance suite explicitly
checks that buffers are not modified in error conditions.
Fixes:
ES31-CTS.program_interface_query.buff-length
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Tapani Pälli [Mon, 3 Aug 2015 05:48:32 +0000 (08:48 +0300)]
glsl: add variable mode check to build_stageref
Currently stage reference mask is built using the variable name
only. However it can happen that input of one stage has same name
as output from another stage. Adding check of variable mode makes
sure we do not pick wrong variable.
Fixes some subcases from
ES31-CTS.program_interface_query.no-locations
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Frank Binns [Fri, 31 Jul 2015 08:11:47 +0000 (09:11 +0100)]
dri: set the __DRI_API_OPENGL bit based on max gl compat version
This matches similar behaviour for the __DRI_API_OPENGL_CORE bit.
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Frank Binns [Fri, 31 Jul 2015 08:11:45 +0000 (09:11 +0100)]
egl: Add eglQuerySurface surface type check for EGL_LARGEST_PBUFFER attrib
Calling eglQuerySurface on a window or pixmap with the EGL_LARGEST_PBUFFER
attribute resulted in the contents of the 'value' parameter being modified.
This is the wrong behaviour according to the EGL spec, which states:
"Querying EGL_LARGEST_PBUFFER for a pbuffer surface returns the
same attribute value specified when the surface was created with
eglCreatePbufferSurface. For a window or pixmap surface, the
contents of value are not modified."
Avoid this from happening by checking that the surface type is EGL_PBUFFER_BIT
before modifying the contents of the parameter.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Frank Binns [Fri, 31 Jul 2015 08:11:46 +0000 (09:11 +0100)]
egl/dri: Add error info needed for EGL_EXT_image_dma_buf_import extension
Update the DRI image interface error codes to reflect the needs of the
EGL_EXT_image_dma_buf_import extension. This means updating the existing error
code documentation and adding a new __DRI_IMAGE_ERROR_BAD_ACCESS error code
so that drivers can correctly reject unsupported pitches and offsets. Hook
the new error code up in EGL to return EGL_BAD_ACCESS.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Tue, 4 Aug 2015 00:36:47 +0000 (17:36 -0700)]
vc4: Use nir_lower_load_const_to_scalar().
Eric Anholt [Tue, 4 Aug 2015 00:20:33 +0000 (17:20 -0700)]
nir: Add a nir_lower_load_const_to_scalar() pass.
This is useful to increase the CSE opportunities for a scalar backend. It
avoids regressions when dropping vc4's custom CSE implementation.
v2: Cleanups by Matt (decl in the for loop, and unreachable()).
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Anholt [Tue, 4 Aug 2015 02:08:37 +0000 (19:08 -0700)]
vc4: Don't bother de-SSAing values that aren't part of phi webs.
We can just support them the same way we do load_const's SSA values.
Eric Anholt [Fri, 31 Jul 2015 16:12:48 +0000 (09:12 -0700)]
nir: Add algebraic opt for no-op iand.
I lazily generated some of these in VC4 NIR lowering.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Eric Anholt [Sat, 1 Aug 2015 00:08:46 +0000 (17:08 -0700)]
vc4: Don't bother saturating the dst color for blending.
Since we just pulled it out of the destination as 8-bit unorm, we know
it's in [0, 1] already.
shader-db:
total instructions in shared programs: 100040 -> 98208 (-1.83%)
instructions in affected programs: 14084 -> 12252 (-13.01%)
Eric Anholt [Fri, 31 Jul 2015 18:46:56 +0000 (11:46 -0700)]
vc4: Make r4-writes implicitly move to a temp, and allocate temps to r4.
Previously, SFU values always moved to a temporary, and TLB color reads
and texture reads always lived in r4. Instead, we can have these results
just be normal temporaries, and the register allocator can leave the
values in r4 when they don't interfere with anything else using r4.
shader-db results:
total instructions in shared programs: 100809 -> 100040 (-0.76%)
instructions in affected programs: 42383 -> 41614 (-1.81%)
Eric Anholt [Fri, 31 Jul 2015 17:02:45 +0000 (10:02 -0700)]
vc4: Drop a dead prototype.
Eric Anholt [Wed, 5 Aug 2015 00:18:43 +0000 (17:18 -0700)]
Revert "nir: Use a single bit for the dual-source blend index"
This reverts commit
ab5b7a0fe659ff6f9c1885d5cb047b6531959506. We use more
than one bit of value in tgsi_to_nir.
Rob Clark [Sat, 1 Aug 2015 20:17:49 +0000 (16:17 -0400)]
freedreno/a4xx: add independent blend function support
needed for MRT
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 31 Jul 2015 19:32:58 +0000 (15:32 -0400)]
freedreno/a4xx: MRT support
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 31 Jul 2015 18:34:19 +0000 (14:34 -0400)]
freedreno: move the half-precision logic into core
Both a3xx and a4xx need the same logic to decide if half-precision can
be used for blit shaders. So move it to core and simplify things a bit
with a helper that considers all render targets.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 31 Jul 2015 16:07:24 +0000 (12:07 -0400)]
freedreno: simplify/cleanup resource status tracking
Collapse dirty/reading bools into status bitmask (and drop writing which
should really be the same as dirty). And use 'used_resources' list for
all tracking, including zsbuf/cbufs, rather than special casing the
color and depth/stencil buffers.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 31 Jul 2015 14:54:23 +0000 (10:54 -0400)]
freedreno: fix stream-out caps vec4->components
Should be in units of components, not vec4's
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 31 Jul 2015 13:36:31 +0000 (09:36 -0400)]
freedreno: small bit of cleanup about max rendertargets
We hard-coded 4 or 8 as the max in various places. Switch it all to a
define since the limit will go up with a4xx (and maybe even again in the
future?)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Matt Turner [Mon, 13 Jul 2015 01:05:58 +0000 (18:05 -0700)]
glx: Use _mesa_lroundevenf() in glPixelStoref().
Functional change in which way half-way cases are rounded from towards
positive-infinity to even. The spec says "the passed value is rounded to
the nearest integer". Removes another case of bad half-up rounding.
Matt Turner [Mon, 29 Jun 2015 16:38:34 +0000 (09:38 -0700)]
util: Use SSE intrinsics in _mesa_lroundeven{f,}.
gcc actually generates this for us now that we use -fno-math-errno
(which is weird, since lrintf()/lrint() don't set errno) but clang still
does not. Presumably helps MSVC as well.
Reduced .text size by 8.5k with gcc before -fno-math-errno.
text data bss dec hex filename
4935850 195136 26192
5157178 4eb13a i965_dri.so before
4927225 195128 26192
5148545 4e8f81 i965_dri.so after
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Matt Turner [Fri, 26 Jun 2015 04:43:30 +0000 (21:43 -0700)]
mesa: Use _mesa_lroundevenf() in some more places.
Vinson Lee [Thu, 30 Jul 2015 03:32:41 +0000 (20:32 -0700)]
vl/mpeg12: Silence GCC unused-variable warning.
vl/vl_mpeg12_bitstream.c: In function 'decode_slice':
vl/vl_mpeg12_bitstream.c:928:19: warning: unused variable 'extra' [-Wunused-variable]
unsigned extra = vl_vlc_get_uimsbf(&bs->vlc, 1);
^
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Alejandro Seguí [Mon, 3 Aug 2015 00:15:20 +0000 (02:15 +0200)]
glsl: replace old hash table with new and faster one
The util/hash_table was intended to be a fast hash table
replacement for the program/hash_table see
35fd61bd99c1 and
72e55bb6888ff.
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Ian Romanick [Thu, 30 Jul 2015 13:00:56 +0000 (06:00 -0700)]
glsl: Add constuctors for the common cases of glsl_struct_field
Fixes a giant pile of GCC warnings:
builtin_types.cpp:60:1: warning: missing initializer for member 'glsl_struct_field::stream' [-Wmissing-field-initializers]
I had to add a default constructor because a non-default constructor
was added. Otherwise the only constructor would be the one with
parameters, and all the plases like
glsl_struct_field foo;
would fail to compile.
I wanted to do this in two patches. All of the initializers of
glsl_struct_field structures had to be converted to use the
constructor because C++ apparently forces you to do one or the other:
builtin_types.cpp:61:1: error: could not convert '{glsl_type::float_type, "near", -1, 0, 0, 0, GLSL_MATRIX_LAYOUT_INHERITED, 0, -1}' from '<brace-enclosed initializer list>' to 'glsl_struct_field'
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Thu, 25 Jun 2015 17:45:34 +0000 (10:45 -0700)]
i965: Make gen7_upload_ps_state static
It is only ever called from within the same file.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Thu, 25 Jun 2015 15:43:13 +0000 (08:43 -0700)]
i965: Remove extern declaration for nonexistent state atom
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in gen7_vs_state.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in gen6_multisample_state.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in brw_misc_state.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Thu, 25 Jun 2015 15:20:01 +0000 (08:20 -0700)]
i965: Trivial formatting changes in brw_draw_upload.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Fri, 19 Jun 2015 01:45:44 +0000 (18:45 -0700)]
i965: Trivial formatting changes in brw_draw.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Ian Romanick [Thu, 11 Jun 2015 00:09:16 +0000 (17:09 -0700)]
i965: Trivial formatting changes in brw_wm.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Iago Toral Quiroga [Wed, 15 Jul 2015 07:32:17 +0000 (09:32 +0200)]
i965/nir: Do not scalarize phis in non-scalar setups
Significantly reduces register pressure in some piglit tests.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 8 Jul 2015 14:08:17 +0000 (16:08 +0200)]
i965/vec4: Handle uniform and GRF array access on vertex programs (NIR)
When the NIR-vec4 pass is enabled, handles uniform and GRF array access
on ARB_vertex_program like it is done on vertex shaders.
When the old IR-vec4 pass is used, emit_program_code() emits pull constant
loads directly instead of using relative addressing, hence to call to
move_uniform_array_access_to_pull_constants() is not needed and it is enough
to call to split_uniform_registers().
The patch also calls to move_grf_array_access_to_scratch() like it is
done for shaders, however I suspect this is a no-op for vertex programs and
we could remove it.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Mon, 29 Jun 2015 12:21:38 +0000 (14:21 +0200)]
i965/nir/vec4: Handle uniforms on vertex programs
The implementation takes into account that on ARB_vertex_program
only a single nir variable is generated to support all the uniform data.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 8 Jul 2015 10:44:15 +0000 (12:44 +0200)]
i965/vec4: Enable NIR-vec4 pass on ARB_vertex_programs
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Iago Toral Quiroga [Wed, 1 Jul 2015 08:12:10 +0000 (10:12 +0200)]
i965/nir/gs: Implement support for gl_InvocationID system value
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Samuel Iglesias Gonsalvez [Mon, 13 Jul 2015 13:51:17 +0000 (15:51 +0200)]
i965/gs/gen6: Refactor ir_emit_vertex and ir_end_primitive for gen6
So the implementation is independent of GLSL IR and the visit methods of the
gen6 GS visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Iago Toral Quiroga [Mon, 29 Jun 2015 12:08:11 +0000 (14:08 +0200)]
i965/nir/gs: Implement EmitVertex and EndPrimitive
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Iago Toral Quiroga [Mon, 29 Jun 2015 11:52:30 +0000 (13:52 +0200)]
i965/nir/gs: Handle geometry shaders inputs
Outputs from the vertex shader become array inputs in the geomtry shader,
but the arrays are interleaved, so we need to map our inputs accordingly.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Iago Toral Quiroga [Mon, 29 Jun 2015 11:37:31 +0000 (13:37 +0200)]
i965/gs: Refactor ir_emit_vertex and ir_end_primitive
So the implementation is independent of GLSL IR and the visit methods of the
vec4 visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Iago Toral Quiroga [Wed, 1 Jul 2015 07:51:25 +0000 (09:51 +0200)]
i965/nir: Enable NIR-vec4 pass on geometry shaders
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Samuel Iglesias Gonsalvez [Thu, 11 Jun 2015 10:32:26 +0000 (12:32 +0200)]
nir: Fix output swizzle in get_mul_for_src
Avoid copying an overwritten swizzle, use the original values.
Example:
Former swizzle[] = xyzw
src->swizzle[] = zyxx
The expected output swizzle = zyxx but if we reuse swizzle in the loop,
then output swizzle would be zyzz.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Alejandro Piñeiro [Mon, 6 Jul 2015 13:08:15 +0000 (15:08 +0200)]
i965/nir/vec4: Add implementation of nir_emit_texture()
Uses the nir structure to get all the info needed (sources,
dest reg, etc), and then it uses the common
vec4_visitor::emit_texture to emit the final code.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Alejandro Piñeiro [Mon, 6 Jul 2015 12:33:21 +0000 (14:33 +0200)]
i965/ir/vec4: Refactor visit(ir_texture *ir)
Splitted in two. The emission is moved to a new vec4_visitor
method, vec4_visitor::emit_texture, ir order to be reused
on the nir path.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Alejandro Piñeiro [Sat, 23 May 2015 21:42:58 +0000 (23:42 +0200)]
i965/vec4: Add a new dst_reg constructor accepting a brw_reg_type
This is useful for the upcoming texture support in NIR->vec4 pass,
as we found several cases where the brw_type is available, but not
the glsl_type.
Without this new constructor, the alternative would be:
dst_reg reg(MRF, <reg>)
reg.type = <brw_type>
reg.writemask = <mask>
Adding a new constructor makes code easier to read.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Alejandro Piñeiro [Mon, 6 Jul 2015 11:31:05 +0000 (13:31 +0200)]
i965/vec4: Change vec4_visitor::swizzle_result() method to allow reuse
This patch changes the signature of swizzle_result() to accept lower
level arguments. The purpose is to reuse it in the upcoming NIR->vec4
pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Eduardo Lima Mitev [Thu, 18 Jun 2015 10:12:21 +0000 (12:12 +0200)]
i965/vec4: Change vec4_visitor::gather_channel() method to allow reuse
This patch changes the signature of gather_channel() to accept the gather
component directly instead of fetching it internally from ir_texture.
This will allow reuse in the upcoming NIR->vec4 pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Eduardo Lima Mitev [Thu, 18 Jun 2015 09:31:54 +0000 (11:31 +0200)]
i965/vec4: Change vec4_visitor::emit_mcs_fetch() method to allow reuse
This patch changes the signature of emit_mcs_fetch() to accept lower level
arguments. The purpose is to reuse it in the upcoming NIR->vec4 pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Eduardo Lima Mitev [Thu, 18 Jun 2015 07:37:33 +0000 (09:37 +0200)]
i965/vec4: Move is_high_sample() method to vec4_visitor class
The is_high_sample() method is currently accessible only in the implementation of
vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass, lets make
it a method of the class instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Eduardo Lima Mitev [Wed, 17 Jun 2015 08:59:10 +0000 (10:59 +0200)]
i965/nir: Add new utility method brw_glsl_base_type_for_nir_type()
This method returns the glsl_base_type corresponding to a nir_alu_type.
It will factorize code currently present in fs_nir, that can be reused
in vec4_nir on its upcoming emit_texture support.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Eduardo Lima Mitev [Wed, 17 Jun 2015 08:20:19 +0000 (10:20 +0200)]
i965/nir/vec4: Implement nir_emit_jump
This implementation is taken as-is from fs_nir.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 08:10:44 +0000 (10:10 +0200)]
i965/nir/vec4: Mark as unreachable ops that should be already lowered
NIR ALU operations:
* nir_op_fabs
* nir_op_iabs
* nir_op_fneg
* nir_op_ineg
* nir_op_fsat
should be lowered by lower_source mods
* nir_op_fdiv
should be lowered in the compiler by DIV_TO_MUL_RCP.
* nir_op_fmod
should be lowered in the compiler by MOD_TO_FLOOR.
* nir_op_fsub
* nir_op_isub
should be handled by ir_sub_to_add_neg.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 08:08:27 +0000 (10:08 +0200)]
i965/nir/vec4: Implement vector "any" operation
Adds NIR ALU operations:
* nir_op_bany2
* nir_op_bany3
* nir_op_bany4
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 08:06:44 +0000 (10:06 +0200)]
i965/nir/vec4: Implement the dot product operation
Adds NIR ALU operations:
* nir_op_fdot2
* nir_op_fdot3
* nir_op_fdot4
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 08:05:29 +0000 (10:05 +0200)]
i965/nir/vec4: Implement conditional select
Adds NIR ALU operations:
* nir_op_bcsel
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:52:43 +0000 (09:52 +0200)]
i965/nir/vec4: Implement linear interpolation
Adds NIR ALU operation:
* nir_op_flrp
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 08:01:07 +0000 (10:01 +0200)]
i965/vec4: Return the emitted instruction in emit_lrp()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:51:10 +0000 (09:51 +0200)]
i965/nir/vec4: Implement floating-point fused multiply-add
Adds NIR ALU operation:
* nir_op_ffma
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:49:31 +0000 (09:49 +0200)]
i965/nir/vec4: Implement "shift" operations
Adds NIR ALU operations:
* nir_op_ishl
* nir_op_ishr
* nir_op_ushr
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:47:41 +0000 (09:47 +0200)]
i965/nir/vec4: Implement the "sign" operation
Follows the vec4_visitor IR implementation but
sets the saturate value in addition.
Adds NIR ALU operations:
* nir_op_fsign
* nir_op_isign
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:44:25 +0000 (09:44 +0200)]
i965/nir/vec4: Implement bit operations
Same implementation than the IR case.
Adds NIR ALU operations:
* nir_op_bitfield_reverse
* nir_op_bit_count
* nir_op_ufind_msb
* nir_op_ifind_msb
* nir_op_find_lsb
* nir_op_ubitfield_extract
* nir_op_ibitfield_extract
* nir_op_bfm
* nir_op_bfi
* nir_op_bitfield_insert
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:29:04 +0000 (09:29 +0200)]
i965/nir/vec4: Implement pack/unpack operations
* Lowered floating-point pack and unpack operations are not valid in VS.
* Pack and unpack 2x16 operations should be handled by lower_packing_builtins.
* Adds NIR ALU operations:
* nir_op_pack_half_2x16
* nir_op_unpack_half_2x16
* nir_op_unpack_unorm_4x8
* nir_op_unpack_snorm_4x8
* nir_op_pack_unorm_4x8
* nir_op_pack_snorm_4x8
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:23:10 +0000 (09:23 +0200)]
i965/nir/vec4: "noise" ops should already be lowered
Marked them as unreachable.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:21:30 +0000 (09:21 +0200)]
i965/nir/vec4: Implement "bool<->int,float" format conversion
Used the same implementation than the vec4_visitor NIR.
Adds NIR ALU operations:
* nir_op_b2i
* nir_op_b2f
* nir_op_f2b
* nir_op_i2b
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:07:20 +0000 (09:07 +0200)]
i965/nir/vec4: Implement logical operators
Adds NIR ALU operations:
* nir_op_inot
* nir_op_ixor
* nir_op_ior
* nir_op_iand
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Wed, 17 Jun 2015 07:01:28 +0000 (09:01 +0200)]
i965/nir/vec4: Implement non-equality ops on vectors
Adds NIR ALU operations:
* nir_op_bany_fnequal2
* nir_op_bany_inequal2
* nir_op_bany_fnequal3
* nir_op_bany_inequal3
* nir_op_bany_fnequal4
* nir_op_bany_inequal4
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:55:24 +0000 (00:55 +0200)]
i965/nir/vec4: Implement equality ops on vectors
Adds NIR ALU operations:
* nir_op_ball_fequal2
* nir_op_ball_iequal2
* nir_op_ball_fequal3
* nir_op_ball_iequal3
* nir_op_ball_fequal4
* nir_op_ball_iequal4
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:49:42 +0000 (00:49 +0200)]
i965/nir/vec4: Implement non-vector comparison ops
Adds NIR ALU operations:
* nir_op_flt
* nir_op_ilt
* nir_op_ult
* nir_op_fge
* nir_op_ige
* nir_op_uge
* nir_op_feq
* nir_op_ieq
* nir_op_fne
* nir_op_ine
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Fri, 17 Apr 2015 15:58:35 +0000 (17:58 +0200)]
i965/nir: Add utility method for comparisons
This method returns the brw_conditional_mod value used when emitting
comparative ALU operations.
It could be moved to brw_nir in the future to reuse it in fs_nir backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 14 Apr 2015 10:04:24 +0000 (12:04 +0200)]
i965/nir/vec4: Derivatives are not allowed in VS
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:34:57 +0000 (00:34 +0200)]
i965/nir/vec4: Implement min/max operations
Adds NIR ALU operations:
* nir_op_fmin
* nir_op_imin
* nir_op_umin
* nir_op_fmax
* nir_op_imax
* nir_op_umax
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:32:58 +0000 (00:32 +0200)]
i965/vec4: Return the emitted instruction in emit_minmax()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:25:02 +0000 (00:25 +0200)]
i965/nir/vec4: Implement various rounding functions
Adds NIR ALU operations:
* nir_op_ftrunc
* nir_op_fceil
* nir_op_ffloor
* nir_op_ffrac
* nir_op_fround_even
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:22:14 +0000 (00:22 +0200)]
i965/nir/vec4: Implement carry/borrow for addition/subtraction
Adds NIR ALU operations:
* nir_op_uadd_carry
* nir_op_usub_borrow
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:10:18 +0000 (00:10 +0200)]
i965/nir/vec4: Implement more math operations
Adds NIR ALU operations:
* nir_op_frcp
* nir_op_fexp2
* nir_op_flog2
* nir_op_fexp
* nir_op_flog
* nir_op_fsin
* nir_op_fcos
* nir_op_idiv
* nir_op_udiv
* nir_op_umod
* nir_op_ldexp
* nir_op_fsqrt
* nir_op_frsq
* nir_op_fpow
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 22:04:09 +0000 (00:04 +0200)]
i965/vec4: Return the last emitted instruction in emit_math()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 21:50:46 +0000 (23:50 +0200)]
i965/nir/vec4: Implement multiplication
Implementation based on the vec4_visitor IR implementation
for the operations ir_binop_mul and ir_binop_imul_high.
Adds NIR ALU operations:
* nir_op_fmul
* nir_op_imul
* nir_op_imul_high
* nir_op_umul_high
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 21:48:46 +0000 (23:48 +0200)]
i965/nir/vec4: Implement the addition operation
Adds NIR ALU operations:
* nir_op_fadd
* nir_op_iadd
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 21:04:32 +0000 (23:04 +0200)]
i965/nir/vec4: Implement int<->float format conversion ops
Adds NIR ALU operations:
* nir_op_f2i
* nir_op_f2u
* nir_op_i2f
* nir_op_u2f
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 20:58:15 +0000 (22:58 +0200)]
i965/nir/vec4: Lower "vecN" instructions and mark them unreachable
This enables NIR pass "lower_vec_to_movs" on shaders that work on vec4.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 20:52:29 +0000 (22:52 +0200)]
i965/nir/vec4: Implement single-element "mov" operations
Adds NIR ALU operations:
* nir_op_imov
* nir_op_fmov
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Alejandro Piñeiro [Thu, 25 Jun 2015 07:52:35 +0000 (09:52 +0200)]
i965/nir: Disable alu_to_scalar pass on non-scalar shaders
Disables nir_lower_alu_to_scalar when the shader stage being processed work
on vec4 vectors, like the upcoming NIR->vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 20:30:16 +0000 (22:30 +0200)]
i965/nir/vec4: Prepare source and destination registers for ALU operations
This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Antia Puentes [Tue, 16 Jun 2015 20:10:32 +0000 (22:10 +0200)]
i965/nir/vec4: Implement loading values from an UBO
Based on the vec4_visitor IR implementation for the ir_binop_load_ubo
operation. Notice that unlike the vec4_visitor IR, adding the !=0
comparison for UBO bools is not needed here because that comparison is
already added by the nir_visitor when processing the ir_binop_load_ubo
(in UBOs "true" is any value different from zero, but for us is ~0).
Adds NIR instrinsics:
* nir_intrinsic_load_ubo_indirect
* nir_intrinsic_load_ubo
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>