nmigen.git
5 years agoback.pysim: general clean-up.
whitequark [Fri, 14 Dec 2018 12:21:48 +0000 (12:21 +0000)]
back.pysim: general clean-up.

5 years agoback.pysim: accept any valid assignments from processes.
whitequark [Fri, 14 Dec 2018 12:18:41 +0000 (12:18 +0000)]
back.pysim: accept any valid assignments from processes.

5 years agoback.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.
whitequark [Fri, 14 Dec 2018 10:57:13 +0000 (10:57 +0000)]
back.pysim: robustly retrieve vcd names for clk/rst when writing gtkw.

5 years agofhdl.xfrm: implement DomainLowerer.
whitequark [Fri, 14 Dec 2018 10:56:53 +0000 (10:56 +0000)]
fhdl.xfrm: implement DomainLowerer.

5 years agoback.pysim: undriven comb signals should return to reset value.
whitequark [Fri, 14 Dec 2018 09:12:38 +0000 (09:12 +0000)]
back.pysim: undriven comb signals should return to reset value.

5 years agoast, back.pysim: allow specifying user-defined decoders for signals.
whitequark [Fri, 14 Dec 2018 09:02:29 +0000 (09:02 +0000)]
ast, back.pysim: allow specifying user-defined decoders for signals.

5 years agoback.pysim: fix completely broken codegen for Switch.
whitequark [Fri, 14 Dec 2018 08:51:36 +0000 (08:51 +0000)]
back.pysim: fix completely broken codegen for Switch.

5 years agoback.pysim: raise an exception if delta cycles blow a process deadline.
whitequark [Fri, 14 Dec 2018 08:10:21 +0000 (08:10 +0000)]
back.pysim: raise an exception if delta cycles blow a process deadline.

5 years agoback.pysim: if requested, write a gtkw file with a useful preset.
whitequark [Fri, 14 Dec 2018 08:04:29 +0000 (08:04 +0000)]
back.pysim: if requested, write a gtkw file with a useful preset.

5 years agoback.pysim: explain how delta cycles work.
whitequark [Fri, 14 Dec 2018 07:26:26 +0000 (07:26 +0000)]
back.pysim: explain how delta cycles work.

5 years agoback.pysim: delay clock processes by one half period.
whitequark [Fri, 14 Dec 2018 05:17:43 +0000 (05:17 +0000)]
back.pysim: delay clock processes by one half period.

Makes it easier to see initial delta cycles.

5 years agoback.pysim: implement "sync processes", like migen.sim generators.
whitequark [Fri, 14 Dec 2018 05:13:58 +0000 (05:13 +0000)]
back.pysim: implement "sync processes", like migen.sim generators.

5 years agoback.pysim: allow suspending processes until a tick in a domain.
whitequark [Fri, 14 Dec 2018 04:33:06 +0000 (04:33 +0000)]
back.pysim: allow suspending processes until a tick in a domain.

5 years agoback.pysim: use bare ints for signal values (-5% runtime).
whitequark [Fri, 14 Dec 2018 03:05:57 +0000 (03:05 +0000)]
back.pysim: use bare ints for signal values (-5% runtime).

5 years agosetup: add missing import.
whitequark [Fri, 14 Dec 2018 02:32:37 +0000 (02:32 +0000)]
setup: add missing import.

5 years agoback.pysim: collect handlers before running (-5% runtime).
whitequark [Thu, 13 Dec 2018 18:34:44 +0000 (18:34 +0000)]
back.pysim: collect handlers before running (-5% runtime).

5 years agoback.pysim: allow multiple registered handlers per signal.
whitequark [Thu, 13 Dec 2018 18:28:11 +0000 (18:28 +0000)]
back.pysim: allow multiple registered handlers per signal.

5 years agoback.pysim: fix handling of process termination.
whitequark [Thu, 13 Dec 2018 18:17:58 +0000 (18:17 +0000)]
back.pysim: fix handling of process termination.

5 years agoback.pysim: new simulator backend (WIP).
whitequark [Thu, 13 Dec 2018 18:00:05 +0000 (18:00 +0000)]
back.pysim: new simulator backend (WIP).

5 years agofhdl.cd: rename ClockDomain signals together with domain.
whitequark [Thu, 13 Dec 2018 15:24:55 +0000 (15:24 +0000)]
fhdl.cd: rename ClockDomain signals together with domain.

5 years agofhdl.ir: move Fragment prepare logic from back.rtlil.
whitequark [Thu, 13 Dec 2018 14:33:39 +0000 (14:33 +0000)]
fhdl.ir: move Fragment prepare logic from back.rtlil.

5 years agoback.verilog: remove debug code.
whitequark [Thu, 13 Dec 2018 13:42:54 +0000 (13:42 +0000)]
back.verilog: remove debug code.

5 years agofhdl.ir: record port direction explicitly.
whitequark [Thu, 13 Dec 2018 13:12:31 +0000 (13:12 +0000)]
fhdl.ir: record port direction explicitly.

No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.

5 years agocompat.genlib.fsm: import/wrap Migen code.
whitequark [Thu, 13 Dec 2018 12:40:14 +0000 (12:40 +0000)]
compat.genlib.fsm: import/wrap Migen code.

5 years agofhdl.ir: a subfragment's input that we don't drive is also our input.
whitequark [Thu, 13 Dec 2018 11:50:56 +0000 (11:50 +0000)]
fhdl.ir: a subfragment's input that we don't drive is also our input.

5 years agofhdl, back: trace and emit source locations of values.
whitequark [Thu, 13 Dec 2018 11:35:20 +0000 (11:35 +0000)]
fhdl, back: trace and emit source locations of values.

5 years agoback.rtlil: never give subfragment cells names starting with $.
whitequark [Thu, 13 Dec 2018 11:30:16 +0000 (11:30 +0000)]
back.rtlil: never give subfragment cells names starting with $.

5 years agofhdl.ir: don't crash propagataing ports in empty fragments.
whitequark [Thu, 13 Dec 2018 11:25:49 +0000 (11:25 +0000)]
fhdl.ir: don't crash propagataing ports in empty fragments.

5 years agofhdl.ir: implement clock domain propagation.
whitequark [Thu, 13 Dec 2018 11:01:03 +0000 (11:01 +0000)]
fhdl.ir: implement clock domain propagation.

5 years agofhdl.ir: remove iter_domains().
whitequark [Thu, 13 Dec 2018 10:18:57 +0000 (10:18 +0000)]
fhdl.ir: remove iter_domains().

5 years agofhdl: cd_name→domain.
whitequark [Thu, 13 Dec 2018 10:15:01 +0000 (10:15 +0000)]
fhdl: cd_name→domain.

5 years agofhdl.cd: add tests.
whitequark [Thu, 13 Dec 2018 09:19:16 +0000 (09:19 +0000)]
fhdl.cd: add tests.

5 years agofhdl.xfrm: implement DomainRenamer.
whitequark [Thu, 13 Dec 2018 08:57:14 +0000 (08:57 +0000)]
fhdl.xfrm: implement DomainRenamer.

5 years agofhdl.xfrm: add test for ControlInserter with subfragments.
whitequark [Thu, 13 Dec 2018 08:45:10 +0000 (08:45 +0000)]
fhdl.xfrm: add test for ControlInserter with subfragments.

5 years agofhdl.xfrm: add tests for ResetInserter, CEInserter.
whitequark [Thu, 13 Dec 2018 08:39:02 +0000 (08:39 +0000)]
fhdl.xfrm: add tests for ResetInserter, CEInserter.

5 years agofhdl.ir: add tests for port propagation.
whitequark [Thu, 13 Dec 2018 08:09:39 +0000 (08:09 +0000)]
fhdl.ir: add tests for port propagation.

5 years agoSet up Travis CI.
whitequark [Thu, 13 Dec 2018 07:50:12 +0000 (07:50 +0000)]
Set up Travis CI.

5 years agoAdd LICENSE.
whitequark [Thu, 13 Dec 2018 07:51:43 +0000 (07:51 +0000)]
Add LICENSE.

5 years agosetup: check Python version.
whitequark [Thu, 13 Dec 2018 07:47:07 +0000 (07:47 +0000)]
setup: check Python version.

5 years agofhdl.dsl: add tests for lowering. 99% branch coverage.
whitequark [Thu, 13 Dec 2018 07:33:56 +0000 (07:33 +0000)]
fhdl.dsl: add tests for lowering. 99% branch coverage.

5 years agofhdl.cd: rename ClockDomain.{reset→rst}.
whitequark [Thu, 13 Dec 2018 07:27:27 +0000 (07:27 +0000)]
fhdl.cd: rename ClockDomain.{reset→rst}.

5 years agofhdl.dsl: add tests for submodules.
whitequark [Thu, 13 Dec 2018 07:24:28 +0000 (07:24 +0000)]
fhdl.dsl: add tests for submodules.

5 years agofhdl.dsl: use less error-prone Switch/Case two-level syntax.
whitequark [Thu, 13 Dec 2018 07:11:06 +0000 (07:11 +0000)]
fhdl.dsl: use less error-prone Switch/Case two-level syntax.

5 years agofhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
whitequark [Thu, 13 Dec 2018 06:06:51 +0000 (06:06 +0000)]
fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.

5 years agofhdl.ast: fix Switch._?hs_signals() for switch without statements.
whitequark [Thu, 13 Dec 2018 05:00:44 +0000 (05:00 +0000)]
fhdl.ast: fix Switch._?hs_signals() for switch without statements.

5 years agoback.verilog: detect undriven public wires using Yosys.
whitequark [Thu, 13 Dec 2018 04:51:15 +0000 (04:51 +0000)]
back.verilog: detect undriven public wires using Yosys.

This should never happen, and is certainly a logic bug in nMigen.

5 years agoback.rtlil: fix swapped operands in sync assign.
whitequark [Thu, 13 Dec 2018 04:34:22 +0000 (04:34 +0000)]
back.rtlil: fix swapped operands in sync assign.

5 years agoback.rtlil: explain logic for CD reset insertion.
whitequark [Thu, 13 Dec 2018 03:51:00 +0000 (03:51 +0000)]
back.rtlil: explain logic for CD reset insertion.

5 years agoback.rtlil: explicitly set the top module.
whitequark [Thu, 13 Dec 2018 03:50:04 +0000 (03:50 +0000)]
back.rtlil: explicitly set the top module.

5 years agofhdl.ir: explain how port enumeration works.
whitequark [Thu, 13 Dec 2018 03:30:39 +0000 (03:30 +0000)]
fhdl.ir: explain how port enumeration works.

5 years agoback.rtlil: explain how RTLIL conversion works.
whitequark [Thu, 13 Dec 2018 03:22:01 +0000 (03:22 +0000)]
back.rtlil: explain how RTLIL conversion works.

5 years agofhdl.ir: make sure clocks and resets of used CDs appear as inputs.
whitequark [Thu, 13 Dec 2018 02:43:22 +0000 (02:43 +0000)]
fhdl.ir: make sure clocks and resets of used CDs appear as inputs.

5 years agoback.rtlil: give clocks and resets nicer names.
whitequark [Thu, 13 Dec 2018 02:43:02 +0000 (02:43 +0000)]
back.rtlil: give clocks and resets nicer names.

5 years agocompat.fhdl.module: implement finalization.
whitequark [Thu, 13 Dec 2018 02:36:15 +0000 (02:36 +0000)]
compat.fhdl.module: implement finalization.

5 years agoback.rtlil: match shape of $mux ports A/B/Y.
whitequark [Thu, 13 Dec 2018 02:35:46 +0000 (02:35 +0000)]
back.rtlil: match shape of $mux ports A/B/Y.

5 years agotracer: add support for Python 3.7.
whitequark [Thu, 13 Dec 2018 02:20:00 +0000 (02:20 +0000)]
tracer: add support for Python 3.7.

5 years agofhdl.ast: bits_sign→shape.
whitequark [Thu, 13 Dec 2018 02:06:49 +0000 (02:06 +0000)]
fhdl.ast: bits_sign→shape.

5 years agofhdl.ast: add tests for most logic.
whitequark [Thu, 13 Dec 2018 02:04:44 +0000 (02:04 +0000)]
fhdl.ast: add tests for most logic.

5 years agoMeasure test coverage.
whitequark [Thu, 13 Dec 2018 02:04:23 +0000 (02:04 +0000)]
Measure test coverage.

5 years agocompat.fhdl.{module,structure}: import/wrap Migen code (WIP).
whitequark [Wed, 12 Dec 2018 15:44:54 +0000 (15:44 +0000)]
compat.fhdl.{module,structure}: import/wrap Migen code (WIP).

5 years agocompat.fhdl.bitcontainer: import/wrap Migen code.
whitequark [Wed, 12 Dec 2018 14:11:19 +0000 (14:11 +0000)]
compat.fhdl.bitcontainer: import/wrap Migen code.

5 years agofhdl.ast.Signal: implement .like().
whitequark [Wed, 12 Dec 2018 14:43:03 +0000 (14:43 +0000)]
fhdl.ast.Signal: implement .like().

5 years agofhdl.ir: fix port threading code.
whitequark [Wed, 12 Dec 2018 13:00:50 +0000 (13:00 +0000)]
fhdl.ir: fix port threading code.

5 years agofhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
whitequark [Wed, 12 Dec 2018 12:38:24 +0000 (12:38 +0000)]
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.

5 years agofhdl.ast.Signal: fix typo.
whitequark [Wed, 12 Dec 2018 12:37:30 +0000 (12:37 +0000)]
fhdl.ast.Signal: fix typo.

5 years agofhdl.ast.Signal: implement attrs field.
whitequark [Wed, 12 Dec 2018 11:02:13 +0000 (11:02 +0000)]
fhdl.ast.Signal: implement attrs field.

5 years agogenlib.cdc.MultiReg: self.regs should be a private field.
whitequark [Wed, 12 Dec 2018 10:52:32 +0000 (10:52 +0000)]
genlib.cdc.MultiReg: self.regs should be a private field.

5 years agofhdl.ast.Signal: implement width derivation from min/max.
whitequark [Wed, 12 Dec 2018 10:43:09 +0000 (10:43 +0000)]
fhdl.ast.Signal: implement width derivation from min/max.

5 years agogenlib.cdc.MultiReg: pull in from Migen.
whitequark [Wed, 12 Dec 2018 10:12:35 +0000 (10:12 +0000)]
genlib.cdc.MultiReg: pull in from Migen.

5 years agofhdl.ast.Signal: implement reset_less signals.
whitequark [Wed, 12 Dec 2018 10:11:16 +0000 (10:11 +0000)]
fhdl.ast.Signal: implement reset_less signals.

5 years agofhdl.ast.Signal: assign an internal name if tracer fails.
whitequark [Wed, 12 Dec 2018 10:08:56 +0000 (10:08 +0000)]
fhdl.ast.Signal: assign an internal name if tracer fails.

5 years agofhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.
whitequark [Wed, 12 Dec 2018 10:00:00 +0000 (10:00 +0000)]
fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.

5 years agoClockDomain.{rst→reset}, for consistency with ResetInserter.
whitequark [Wed, 12 Dec 2018 09:49:02 +0000 (09:49 +0000)]
ClockDomain.{rst→reset}, for consistency with ResetInserter.

nmigen.compat.ClockDomain would alias this, for Migen compatibility.

5 years agoInitial commit.
whitequark [Tue, 11 Dec 2018 20:50:56 +0000 (20:50 +0000)]
Initial commit.