Andreas Sandberg [Thu, 16 Oct 2014 09:49:38 +0000 (05:49 -0400)]
sim: Add typedefs for PMU probe points
In order to show make PMU probe points usable across different PMU
implementations, we want a common probe interface. This patch the
namespace ProbePoins that contains typedefs for probe points that are
shared between multiple SimObjects. It also adds typedefs for the PMU
probe interface.
Andreas Sandberg [Thu, 16 Oct 2014 09:49:37 +0000 (05:49 -0400)]
sim: Add support for serializing BitUnionXX
BitUnion instances can normally not be used with the SERIALIZE_SCALAR
and UNSERIALIZE_SCALAR macros due to the way they are converted
between their storage type and their actual type. This changeset adds
a set of parm(In|Out) functions specifically for gem5 bit unions to
work around the issue.
Andreas Hansson [Thu, 16 Oct 2014 09:49:37 +0000 (05:49 -0400)]
config: Add the ability to read a config file using C++ and Python
This patch adds the ability to load in config.ini files generated from
gem5 into another instance of gem5 built without Python configuration
support. The intended use case is for configuring gem5 when it is a
library embedded in another simulation system.
A parallel config file reader is also provided purely in Python to
demonstrate the approach taken and to provided similar functionality
for as-yet-unknown use models. The Python configuration file reader
can read both .ini and .json files.
C++ configuration file reading:
A command line option has been added for scons to enable C++ configuration
file reading: --with-cxx-config
There is an example in util/cxx_config that shows C++ configuration in action.
util/cxx_config/README explains how to build the example.
Configuration is achieved by the object CxxConfigManager. It handles
reading object descriptions from a CxxConfigFileBase object which
wraps a config file reader. The wrapper class CxxIniFile is provided
which wraps an IniFile for reading .ini files. Reading .json files
from C++ would be possible with a similar wrapper and a JSON parser.
After reading object descriptions, CxxConfigManager creates
SimObjectParam-derived objects from the classes in the (generated with this
patch) directory build/ARCH/cxx_config
CxxConfigManager can then build SimObjects from those SimObjectParams (in an
order dictated by the SimObject-value parameters on other objects) and bind
ports of the produced SimObjects.
A minimal set of instantiate-replacing member functions are provided by
CxxConfigManager and few of the member functions of SimObject (such as drain)
are extended onto CxxConfigManager.
Python configuration file reading (configs/example/read_config.py):
A Python version of the reader is also supplied with a similar interface to
CxxConfigFileBase (In Python: ConfigFile) to config file readers.
The Python config file reading will handle both .ini and .json files.
The object construction strategy is slightly different in Python from the C++
reader as you need to avoid objects prematurely becoming the children of other
objects when setting parameters.
Port binding also needs to be strictly in the same port-index order as the
original instantiation.
Andreas Hansson [Thu, 16 Oct 2014 09:49:36 +0000 (05:49 -0400)]
scons: Add Undefined Behavior Sanitizer (UBSan) option
This patch adds the Undefined Behavior Sanitizer (UBSan) for clang and
gcc >= 4.9. Due to the performance impact, the usage is guarded by a
command-line option.
Curtis Dunham [Mon, 22 Sep 2014 19:37:23 +0000 (14:37 -0500)]
scons: Add --without-tcmalloc build option
Disabling tcmalloc is required for valgrind's memcheck to work properly;
this option makes it easier to create such a build.
Curtis Dunham [Tue, 12 Aug 2014 22:35:28 +0000 (17:35 -0500)]
scons: Generate a single debug flag C++ file
Reduces target count/compiler invocations by ~180.
Curtis Dunham [Thu, 16 Oct 2014 09:49:33 +0000 (05:49 -0400)]
scons: create dummy target to have SWIG generate C++ classes
scons build/<arch>/swig
Andrew Bardsley [Thu, 16 Oct 2014 09:49:32 +0000 (05:49 -0400)]
config: Add a --without-python option to build process
Add the ability to build libgem5 without embedded Python or the
ability to configure with Python.
This is a prelude to a patch to allow config.ini files to be loaded
into libgem5 using only C++ which would make embedding gem5 within
other simulation systems easier.
This adds a few registration interfaces to things which cross
between Python and C++. Namely: stats dumping and SimObject resolving
Andreas Hansson [Thu, 16 Oct 2014 09:49:31 +0000 (05:49 -0400)]
stats: Small bump of trailing stats
Somehow these seem to have been missed.
Nilay Vaish [Sat, 11 Oct 2014 21:18:51 +0000 (16:18 -0500)]
stats: updates due to changes to x86, stale configs.
Andrew Lukefahr [Sat, 11 Oct 2014 21:16:02 +0000 (16:16 -0500)]
cpu: Fix o3 SMT IQCount bug
Commmitted by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sat, 11 Oct 2014 21:16:00 +0000 (16:16 -0500)]
util: adds a script for using DSENT
This patch adds a python script that processes the configuration and the
statistics file from a simulation run. Configuration and activity of network
routers and links obtained from this processing is fed to DSENT via its Python
interface. DSENT then computes the area and the power consumption of these
network components. The script outputs these quantities to the console.
Nilay Vaish [Sat, 11 Oct 2014 21:16:00 +0000 (16:16 -0500)]
ext: dsent: adds a Python interface, drops C++ one
This patch extensively modifies DSENT so that it can be accessed using Python.
To access the Python interface, DSENT needs to compiled as a shared library.
For this purpose a CMakeLists.txt file has been added. Some of the code that
is not required is being removed.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ext: add the source code for DSENT
This patch adds a tool called DSENT to the ext/ directory. DSENT
is a tool that models power and area for on-chip networks. The next
patch adds a script for using the tool.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: network: garnet: add statistics for different activities
This patch adds some statistics to garnet that record the activity
of certain structures in the on-chip network. These statistics, in a later
patch, will be used for computing the energy consumed by the on-chip network.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: network: garnet: remove functions for computing power
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: drop Orion network power model
Orion is being dropped from ruby. It would be replaced with DSENT
which has better models. Note that the power / energy numbers reported
after this patch has been applied are not for use.
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
ruby: mesi: slight renaming
Nilay Vaish [Sat, 11 Oct 2014 20:02:23 +0000 (15:02 -0500)]
config: separate function for instantiating a memory controller
This patch moves code for instantiating a single memory controller from
the function config_mem() to a separate function. This is being done
so that memory controllers can be instantiated without assuming that
they will be attached to the system in a particular fashion.
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
ruby: structures: coorect #ifndef macros in header files
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
ruby: moesi hammer: correct typo in master-slave assignment
Jiuyue Ma [Fri, 13 Jun 2014 08:48:47 +0000 (16:48 +0800)]
x86: add LongModeAddressSize function to cpuid
LongModeAddressSize was used by kernel 2.6.28.4 for physical address
validation, if not properly implemented, PCI resource allocation may
failed because of ioremap failed:
- linux-2.6.28.4/arch/x86/mm/ioremap.c:27-30
27 static inline int phys_addr_valid(unsigned long addr)
28 {
29 return addr < (1UL << boot_cpu_data.x86_phys_bits);
30 }
- linux-2.6.28.4/arch/x86/kernel/cpu/common.c:475-482
475 #ifdef CONFIG_X86_64
476 if (c->extended_cpuid_level >= 0x80000008) {
477 u32 eax = cpuid_eax(0x80000008);
478
479 c->x86_virt_bits = (eax >> 8) & 0xff;
480 c->x86_phys_bits = eax & 0xff;
481 }
482 #endif
- linux-2.6.28.4/arch/x86/mm/ioremap.c:209-214
209 if (!phys_addr_valid(phys_addr)) {
210 printk(KERN_WARNING "ioremap: invalid physical address %llx\n",
211 (unsigned long long)phys_addr);
212 WARN_ON_ONCE(1);
213 return NULL;
214 }
This patch return 0x0000ffff for LongModeAddressSize, which guarantee phys_addr_valid never failed.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Jiuyue Ma [Thu, 17 Jul 2014 04:05:41 +0000 (12:05 +0800)]
config, x86: Ensure that PCI devs get bridged to the memory bus
This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by
reserve anything between the end of memory and 3GB if memory is less
than 3GB. It also statically bridge these address range to the IO bus,
which guaranty access to pci address space will pass though bridge to
iobus.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Jiuyue Ma [Thu, 17 Jul 2014 03:00:12 +0000 (11:00 +0800)]
config, x86: swap bus_id of ISA/PCI in X86 IntelMPTable
This patch assign bus_id=0 to PCI bus and bus_id=1 to ISA bus for
X86 platform. Because PCI device get config space address using
Pc::calcPciConfigAddr() which requires "assert(bus==0)".
This fixes PCI interrupt routing and discovery on Linux.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andrew Lukefahr [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
sim: draining bug for fast-forwaring multiple cores
fix draining bug where multiple cores hit max_insts_any_thread simultaneously
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
base: addr range: slight change to validity check
The validity check is being changed from < to <= since the end of the range
is considered to be a part of it.
Nilay Vaish [Sat, 11 Oct 2014 20:02:22 +0000 (15:02 -0500)]
base: misc: Add missing header file.
Andreas Hansson [Thu, 9 Oct 2014 21:52:13 +0000 (17:52 -0400)]
stats: Add DRAM power statistics to reference output
Omar Naji [Tue, 29 Jul 2014 16:22:44 +0000 (17:22 +0100)]
mem: DRAMPower integration for on-line DRAM power stats
This patch takes the final step in integrating DRAMPower and adds the
appropriate calls in the DRAM controller to provide the command trace
and extract the power and energy stats. The debug printouts are still
left in place, but will eventually be removed.
At the moment the DRAM power calculation is always on when using the
DRAM controller model. The run-time impact of this addition is around
1.5% when looking at the total host seconds of the regressions. We
deem this a sensible trade-off to avoid the complication of adding an
enable/disable mechanism.
Omar Naji [Tue, 29 Jul 2014 16:29:36 +0000 (17:29 +0100)]
mem: Add DRAMPower wrapping class
This patch adds a class to wrap DRAMPower Library in gem5.
This class initiates an object of class MemorySpecification
of the DRAMPower Library, passes the parameters from DRAMCtrl.py
to this object and creates an object of drampower library using
the memory specification.
Omar Naji [Fri, 25 Jul 2014 09:05:59 +0000 (10:05 +0100)]
mem: Add missig timing and current parameters to DRAM configs
This patch adds missing timing and current parameters to the existing
DRAM configs. These missing timing and current parameters are required
by DRAMPower for the DRAM power calculations. The missing values are
datasheet values of the specified DRAMs, and the appropriate
references are added for the variuos configs.
Omar Naji [Thu, 9 Oct 2014 21:52:04 +0000 (17:52 -0400)]
mem: Remove DRAMSim2 DDR3 configuration
This patch prunes the DDR3 config that was initially created to match
the default config of DRAMSim2. The config is not complete as it is,
and to avoid having to maintain it, the easiest way forward is to
simply prune it. Going forward we are adding power number etc to the
other configurations.
Andreas Hansson [Thu, 9 Oct 2014 21:52:03 +0000 (17:52 -0400)]
ext: Add DRAMPower to enable on-line DRAM power modelling
This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit
8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the
simulator. We have chosen this specific version of DRAMPower as it
provides the necessary functionality, and future updates will be
coordinated with the DRAMPower development team. The files added only
include the bits needed to build the library, thus excluding all
memory specifications, traces, and the stand-alone DRAMPower
command-line tool.
A future patch includes the DRAMPower functionality in the DRAM
controller, to enable on-line DRAM power modelling, and avoid using
post-processing of traces.
Andreas Hansson [Thu, 9 Oct 2014 21:52:00 +0000 (17:52 -0400)]
config: Add Current as a parameter type
This patch adds the Python parameter type Current, which is used for
the DRAM power modelling (to start with). With this addition we avoid
implicit unit assumptions.
Mitch Hayenga [Thu, 9 Oct 2014 21:51:58 +0000 (17:51 -0400)]
cpu: Remove Ozone CPU from the source tree
The Ozone CPU is now very much out of date and completely
non-functional, with no one actively working on restoring it. It is a
source of confusion for new users who attempt to use it before
realizing its current state. RIP
Andreas Hansson [Thu, 9 Oct 2014 21:51:57 +0000 (17:51 -0400)]
scons: Warn for known gcc and swig incompatibilities
Andreas Hansson [Thu, 9 Oct 2014 21:51:56 +0000 (17:51 -0400)]
mem: Add packet sanity checks to cache and MSHRs
This patch adds a number of asserts to the cache, checking basic
assumptions about packets being requests or responses.
Andreas Hansson [Thu, 9 Oct 2014 21:51:52 +0000 (17:51 -0400)]
mem: Allow packet queue to move next send event forward
This patch changes the packet queue such that when scheduling a send,
the queue is allowed to move the event forward.
Andreas Hansson [Wed, 1 Oct 2014 12:05:54 +0000 (08:05 -0400)]
misc: Fix issues identified by static analysis
Another bunch of issues addressed.
Andreas Hansson [Wed, 1 Oct 2014 12:05:52 +0000 (08:05 -0400)]
arm: Use MiscRegIndex rather than int when flattening
Some additional type checking to avoid future issues.
Andreas Hansson [Wed, 1 Oct 2014 12:05:51 +0000 (08:05 -0400)]
arm: More UBSan cleanups after additional full-system runs
Some incorrect casting to IntRegIndex, and a few uninitialized members
in the i8254xGBe device.
Andreas Hansson [Sun, 28 Sep 2014 20:53:48 +0000 (16:53 -0400)]
stats: Update stats to reflect ARM fixes
As a result of the fixes, the full-system dual-core ARM regressions
are slightly changed. Hopefully this also means there will no longer
be any discrepancies between the results observed on different hosts.
Andreas Hansson [Sat, 27 Sep 2014 13:08:37 +0000 (09:08 -0400)]
arm: Fixed undefined behaviours identified by gcc
This patch fixes the runtime errors highlighted by the undefined
behaviour sanitizer. In the end there were two issues. First, when
rotating an immediate, we ended up shifting an uint32_t by 32 in some
cases. This case is fixed by checking for a rotation by 0
positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and
a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex
as an IntRegIndex. This issue is resolved by introducing a
MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types.
With these fixes there are no runtime errors identified for the full
ARM regressions.
Andreas Hansson [Sat, 27 Sep 2014 13:08:36 +0000 (09:08 -0400)]
arch: Use const StaticInstPtr references where possible
This patch optimises the passing of StaticInstPtr by avoiding copying
the reference-counting pointer. This avoids first incrementing and
then decrementing the reference-counting pointer.
Andreas Hansson [Sat, 27 Sep 2014 13:08:34 +0000 (09:08 -0400)]
scons: Address issues related to gcc 4.9.1
Fix a number few minor issues to please gcc 4.9.1. Removing the
'-fuse-linker-plugin' flag means no libraries are part of the LTO
process, but hopefully this is an acceptable loss, as the flag causes
issues on a lot of systems (only certain combinations of gcc, ld and
ar work).
Curtis Dunham [Sat, 27 Sep 2014 13:08:33 +0000 (09:08 -0400)]
dev: Output invalid access size in IsaFake panic
Curtis Dunham [Sat, 27 Sep 2014 13:08:32 +0000 (09:08 -0400)]
mem: Output precise range when XBar has conflicts
Curtis Dunham [Sat, 27 Sep 2014 13:08:30 +0000 (09:08 -0400)]
mem: Provide better diagnostic for unconnected port
When _masterPort is null, a message to that effect is
more helpful than a segfault.
Andreas Hansson [Sat, 27 Sep 2014 13:08:29 +0000 (09:08 -0400)]
misc: Fix a bunch of minor issues identified by static analysis
Add some missing initialisation, and fix a handful benign resource
leaks (including some false positives).
Steve Reinhardt [Mon, 22 Sep 2014 03:04:39 +0000 (23:04 -0400)]
stats: update t1000 stats for recent changes
Steve Reinhardt [Sun, 21 Sep 2014 20:15:14 +0000 (16:15 -0400)]
stats: update eio stats for recent changes
Andreas Hansson [Sat, 20 Sep 2014 21:18:53 +0000 (17:18 -0400)]
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Mitch Hayenga [Sat, 20 Sep 2014 21:18:36 +0000 (17:18 -0400)]
cpu: Remove unused deallocateContext calls
The call paths for de-scheduling a thread are halt() and suspend(), from
the thread context. There is no call to deallocateContext() in general,
though some CPUs chose to define it. This patch removes the function
from BaseCPU and the cores which do not require it.
Mitch Hayenga [Sat, 20 Sep 2014 21:18:35 +0000 (17:18 -0400)]
alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate
activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.
Andreas Hansson [Sat, 20 Sep 2014 21:18:33 +0000 (17:18 -0400)]
tests: Use more representative configs for ARM tests
This patch changes the CPU and cache configurations used in the ARM SE and FS
regressions to make them more representative, and also get better code
coverage by exercising different replacement policies and use an L2
prefetcher.
Andreas Hansson [Sat, 20 Sep 2014 21:18:32 +0000 (17:18 -0400)]
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.
As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.
--HG--
rename : src/mem/Bus.py => src/mem/XBar.py
rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc
rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh
rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc
rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh
rename : src/mem/bus.cc => src/mem/xbar.cc
rename : src/mem/bus.hh => src/mem/xbar.hh
Andreas Hansson [Sat, 20 Sep 2014 21:18:30 +0000 (17:18 -0400)]
tests: Add a memtest version using the ideal SnoopFilter
This patch adds a basic regression test for the snoop filter.
--HG--
rename : tests/configs/memtest.py => tests/configs/memtest-filter.py
Stephan Diestelhorst [Fri, 25 Apr 2014 11:36:16 +0000 (12:36 +0100)]
mem: Add access statistics for the snoop filter
Adds a simple access counter for requests and snoops for the snoop filter and
also classifies hits based on whether a single other holder existed or whether
multiple shares held the line.
Stephan Diestelhorst [Sat, 20 Sep 2014 21:18:29 +0000 (17:18 -0400)]
mem: Tie in the snoop filter in the coherent bus
Stephan Diestelhorst [Thu, 24 Apr 2014 12:28:47 +0000 (13:28 +0100)]
mem: Add a simple snoop counter per bus
This patch adds a simple counter for both total messages and a histogram for
the fan-out of snoop messages. The fan-out describes to how many ports snoops
had to be sent per incoming request / snoop-from-below. Without any
cleverness, this usually means to either all, or all but the requesting port.
Stephan Diestelhorst [Thu, 24 Apr 2014 16:41:26 +0000 (17:41 +0100)]
misc: Add functions for doing popcount and power-of-two checking
Adds two public domain algorithms for determining number of set bits and also
whether a value is a power of two, uses the builtin that is available in GCC
and clang for popcount.
Stephan Diestelhorst [Sat, 20 Sep 2014 21:18:26 +0000 (17:18 -0400)]
mem: Simple Snoop Filter
This is a first cut at a simple snoop filter that tracks presence of lines in
the caches "above" it. The snoop filter can be applied at any given cache
hierarchy and will then handle the caches above it appropriately; there is no
need to use this only in the last-level bus.
This design currently has some limitations: missing stats, no notion of clean
evictions (these will not update the underlying snoop filter, because they are
not sent from the evicting cache down), no notion of capacity for the snoop
filter and thus no need for invalidations caused by capacity pressure in the
snoop filter. These are planned to be added on top with future change sets.
Stephan Diestelhorst [Tue, 12 Aug 2014 18:00:44 +0000 (19:00 +0100)]
energy: Tighter checking of levels for DFS systems
There are cases where users might by accident / intention specify less voltage
operating points thatn frequency points. We consider one of these cases
special: giving only a single voltage to a voltage domain effectively renders
it as a static domain. This patch adds additional logic in the auxiliary parts
of the functionality to handle these cases properly (simple driver asking for
N>1 operating levels, we should return the same voltage for all of them) and
adds error checking code in the voltage domain.
Stephan Diestelhorst [Fri, 25 Jul 2014 12:36:23 +0000 (13:36 +0100)]
energy: Add the Energy Controller in the right configs
Tie in the newly created energy controller components in the default
configurations.
Akash Bagdia [Sat, 20 Sep 2014 21:18:23 +0000 (17:18 -0400)]
energy: Memory-mapped Energy Controller component
This patch provides an Energy Controller device that provides software
(driver) access to a DVFS handler. The device is currently residing in
the dev/arm tree, but there is nothing inherently ARM specific in the
behaviour. It is currently only tested and supported for ARM Linux,
hence the location.
Stephan Diestelhorst [Mon, 16 Jun 2014 13:59:44 +0000 (14:59 +0100)]
energy: Small extentions and fixes for DVFS handler
These additions allow easier interoperability with and querying from an
additional controller which will be in a separate patch. Also adding warnings
for changing the enabled state of the handler across checkpoint / resume and
deviating from the state in the configuration.
Contributed-by: Akash Bagdia <akash.bagdia@arm.com>
Wendy Elsasser [Sat, 20 Sep 2014 21:18:21 +0000 (17:18 -0400)]
mem: Add DDR4 bank group timing
Added the following parameter to the DRAMCtrl class:
- bank_groups_per_rank
This defaults to 1. For the DDR4 case, the default is overridden to indicate
bank group architecture, with multiple bank groups per rank.
Added the following delays to the DRAMCtrl class:
- tCCD_L : CAS-to-CAS, same bank group delay
- tRRD_L : RAS-to-RAS, same bank group delay
These parameters are only applied when bank group timing is enabled. Bank
group timing is currently enabled only for DDR4 memories.
For all other memories, these delays will default to '0 ns'
In the DRAM controller model, applied the bank group timing to the per bank
parameters actAllowedAt and colAllowedAt.
The actAllowedAt will be updated based on bank group when an ACT is issued.
The colAllowedAt will be updated based on bank group when a RD/WR burst is
issued.
At the moment no modifications are made to the scheduling.
Wendy Elsasser [Sat, 20 Sep 2014 21:17:57 +0000 (17:17 -0400)]
mem: Add memory rank-to-rank delay
Add the following delay to the DRAM controller:
- tCS : Different rank bus turnaround delay
This will be applied for
1) read-to-read,
2) write-to-write,
3) write-to-read, and
4) read-to-write
command sequences, where the new command accesses a different rank
than the previous burst.
The delay defaults to 2*tCK for each defined memory class. Note that
this does not correspond to one particular timing constraint, but is a
way of modelling all the associated constraints.
The DRAM controller has some minor changes to prioritize commands to
the same rank. This prioritization will only occur when the command
stream is not switching from a read to write or vice versa (in the
case of switching we have a gap in any case).
To prioritize commands to the same rank, the model will determine if there are
any commands queued (same type) to the same rank as the previous command.
This check will ensure that the 'same rank' command will be able to execute
without adding bubbles to the command flow, e.g. any ACT delay requirements
can be done under the hoods, allowing the burst to issue seamlessly.
Wendy Elsasser [Sat, 20 Sep 2014 21:17:55 +0000 (17:17 -0400)]
cpu: Update DRAM traffic gen
Add new DRAM_ROTATE mode to traffic generator.
This mode will generate DRAM traffic that rotates across
banks per rank, command types, and ranks per channel
The looping order is illustrated below:
for (ranks per channel)
for (command types)
for (banks per rank)
// Generate DRAM Command Series
This patch also adds the read percentage as an input argument to the
DRAM sweep script. If the simulated read percentage is 0 or 100, the
middle for loop does not generate additional commands. This loop is
used only when the read percentage is set to 50, in which case the
middle loop will toggle between read and write commands.
Modified sweep.py script, which generates DRAM traffic.
Added input arguments and support for new DRAM_ROTATE mode.
The script now has input arguments for:
1) Read percentage
2) Number of ranks
3) Address mapping
4) Traffic generator mode (DRAM or DRAM_ROTATE)
The default values are:
100% reads, 1 rank, RoRaBaCoCh address mapping, and DRAM traffic gen mode
For the DRAM traffic mode, added multi-rank support.
Andreas Sandberg [Sat, 20 Sep 2014 21:17:54 +0000 (17:17 -0400)]
dev: Add support for 9p proxying over VirtIO
This patch adds support for 9p filesystem proxying over VirtIO. It can
currently operate by connecting to a 9p server over a socket
(VirtIO9PSocket) or by starting the diod 9p server and connecting over
pipe (VirtIO9PDiod).
*WARNING*: Checkpoints are currently not supported for systems with 9p
proxies!
Andreas Sandberg [Sat, 20 Sep 2014 21:17:53 +0000 (17:17 -0400)]
dev: Add a VirtIO block device model
Andreas Sandberg [Sat, 20 Sep 2014 21:17:52 +0000 (17:17 -0400)]
dev: Add a VirtIO console device model
Andreas Sandberg [Sat, 20 Sep 2014 21:17:51 +0000 (17:17 -0400)]
dev, pci: Implement basic VirtIO support
This patch adds support for VirtIO over the PCI bus. It does so by
providing the following new SimObjects:
* VirtIODeviceBase - Abstract base class for VirtIO devices.
* PciVirtIO - VirtIO PCI transport interface.
A VirtIO device is hooked up to the guest system by adding a PciVirtIO
device to the PCI bus and connecting it to a VirtIO device using the
vio parameter.
New VirtIO devices should inherit from VirtIODevice base and
implementing one or more VirtQueues. The VirtQueues are usually
device-specific and all derive from the VirtQueue class. Queues must
be registered with the base class from the constructor since the
device assumes that the number of queues stay constant.
Andreas Sandberg [Sat, 20 Sep 2014 21:17:50 +0000 (17:17 -0400)]
dev: Refactor terminal<->UART interface to make it more generic
The terminal currently assumes that the transport to the guest always
inherits from the Uart class. This assumption breaks when
implementing, for example, a VirtIO consoles. This patch removes this
assumption by adding pointer to the from the terminal to the uart and
replacing it with a more general callback interface. The Uart, or any
other class using the terminal, class implements an instance of the
callbacks class and registers it with the terminal.
Andreas Hansson [Sat, 20 Sep 2014 21:17:49 +0000 (17:17 -0400)]
base: Clean up redundant string functions and use C++11
This patch does a bit of housekeeping on the string helper functions
and relies on the C++11 standard library where possible. It also does
away with our custom string hash as an implementation is already part
of the standard library.
Andrew Bardsley [Sat, 20 Sep 2014 21:17:47 +0000 (17:17 -0400)]
base: Add getSectionNames to IniFile
Add an accessor to IniFile to list all the sections in the file.
Curtis Dunham [Mon, 25 Aug 2014 19:32:00 +0000 (14:32 -0500)]
tests: automatically kill regressions that take too long
When GNU coreutils 'timeout' is available, limit each regression
simulation to 4 hours.
Mitch Hayenga [Sat, 20 Sep 2014 21:17:45 +0000 (17:17 -0400)]
cpu: Add ExecFlags debug flag
Adds a debug flag to print out the flags a instruction is tagged with.
Mitch Hayenga [Sat, 20 Sep 2014 21:17:44 +0000 (17:17 -0400)]
mem: Remove the GHB prefetcher from the source tree
There are two primary issues with this code which make it deserving of deletion.
1) GHB is a way to structure a prefetcher, not a definitive type of prefetcher
2) This prefetcher isn't even structured like a GHB prefetcher.
It's basically a worse version of the stride prefetcher.
It primarily serves to confuse new gem5 users and most functionality is already
present in the stride prefetcher.
Dam Sunwoo [Sat, 20 Sep 2014 21:17:43 +0000 (17:17 -0400)]
cpu: use probes infrastructure to do simpoint profiling
Instead of having code embedded in cpu model to do simpoint profiling use
the probes infrastructure to do it.
Andrew Bardsley [Sat, 20 Sep 2014 21:17:42 +0000 (17:17 -0400)]
config: Cleanup .json config file generation
This patch 'completes' .json config files generation by adding in the
SimObject references and String-valued parameters not currently
printed.
TickParamValues are also changed to print in the same tick-value
format as in .ini files.
This allows .json files to describe a system as fully as the .ini files
currently do.
This patch adds a new function config_value (which mirrors ini_str) to
each ParamValue and to SimObject. This function can then be explicitly
changed to give different .json and .ini printing behaviour rather than
being written in terms of ini_str.
Andreas Hansson [Fri, 19 Sep 2014 14:35:18 +0000 (10:35 -0400)]
arch: Pass faults by const reference where possible
This patch changes how faults are passed between methods in an attempt
to copy as few reference-counting pointer instances as possible. This
should avoid unecessary copies being created, contributing to the
increment/decrement of the reference counters.
Andreas Hansson [Fri, 19 Sep 2014 14:35:14 +0000 (10:35 -0400)]
cpu: Use a deque in o3 rename instruction queue
Switch from a list to a data structure with better data layout.
Andreas Hansson [Fri, 19 Sep 2014 14:35:12 +0000 (10:35 -0400)]
base: Ensure the CP annotation compiles again
A bit of revamping to get the CP annotate functionality to compile.
Andreas Hansson [Fri, 19 Sep 2014 14:35:11 +0000 (10:35 -0400)]
misc: Use safe_cast when assumptions are made about return value
This patch changes two dynamic_cast to safe_cast as we assume the
return value is not NULL (without checking).
Andreas Hansson [Fri, 19 Sep 2014 14:35:09 +0000 (10:35 -0400)]
misc: Restore ostream flags where needed
This patch ensures we adhere to the normal ostream usage rules, and
restore the flags after modifying them.
Andreas Hansson [Fri, 19 Sep 2014 14:35:08 +0000 (10:35 -0400)]
stats: Fix flow-control bug in Vector2D printing
Andreas Hansson [Fri, 19 Sep 2014 14:35:07 +0000 (10:35 -0400)]
misc: Remove assertions ensuring unsigned values >= 0
Andreas Hansson [Fri, 19 Sep 2014 14:35:06 +0000 (10:35 -0400)]
mem: Check return value of checkFunctional in SimpleMemory
Simple fix to ensure we only iterate until we are done.
Andreas Hansson [Fri, 19 Sep 2014 14:35:04 +0000 (10:35 -0400)]
mem: Add checks to sendTimingReq in cache
A small fix to ensure the return value is not ignored.
Nilay Vaish [Mon, 15 Sep 2014 21:19:38 +0000 (16:19 -0500)]
ruby: network: revert some of the changes from
ad9c042dce54
The changeset
ad9c042dce54 made changes to the structures under the network
directory to use a map of buffers instead of vector of buffers.
The reasoning was that not all vnets that are created are used and we
needlessly allocate more buffers than required and then iterate over them
while processing network messages. But the move to map resulted in a slow
down which was pointed out by Andreas Hansson. This patch moves things
back to using vector of message buffers.
Andreas Hansson [Fri, 12 Sep 2014 14:22:50 +0000 (10:22 -0400)]
stats: Minor update of Minor stats after uncacheable fix
Andrew Bardsley [Fri, 12 Sep 2014 14:22:49 +0000 (10:22 -0400)]
cpu: Fix memory access in Minor not setting parent Request flags
This patch fixes cases where uncacheable/memory type flags are not set
correctly on a memory op which is split in the LSQ. Without this
patch, request->request if freely used to check flags where the flags
should actually come from the accumulation of request fragment flags.
This patch also fixes a bug where an uncacheable access which passes
through tryToSendRequest more than once can increment
LSQ::numAccessesInMemorySystem more than once.
Andrew Bardsley [Fri, 12 Sep 2014 14:22:47 +0000 (10:22 -0400)]
style: Fix line continuation, especially in debug messages
This patch closes a number of space gaps in debug messages caused by
the incorrect use of line continuation within strings. (There's also
one consistency change to a similar, but correct, use of line
continuation)
Andreas Hansson [Fri, 12 Sep 2014 14:22:46 +0000 (10:22 -0400)]
minor: Fix typo in DPRINTF for Minor branch prediction
Andreas Sandberg [Tue, 9 Sep 2014 08:36:43 +0000 (04:36 -0400)]
sim: Automatically unregister probe listeners
The ProbeListener base class automatically registers itself with a
probe manager. Currently, the class does not unregister a itself when
it is destroyed, which makes removing probes listeners somewhat
cumbersome. This patch adds an automatic call to
manager->removeListener in the ProbeListener destructor, which solves
the problem.
Geoffrey Blake [Tue, 9 Sep 2014 08:36:34 +0000 (04:36 -0400)]
config: Fix vectorparam command line parsing
Parsing vectorparams from the command was slightly broken
in that it wouldn't accept the input that the help message
provided to the user and it didn't do the conversion
on the second code path used to convert the string input
to the actual internal representation. This patch fixes these bugs.
Mitch Hayenga [Tue, 9 Sep 2014 08:36:34 +0000 (04:36 -0400)]
cpu: Only iterate over possible threads on the o3 cpu
Some places in O3 always iterated over "Impl::MaxThreads" even if a CPU had
fewer threads. This removes a few of those instances.
Mitch Hayenga [Tue, 9 Sep 2014 08:36:33 +0000 (04:36 -0400)]
mem: Add accessor function for vaddr
Determine if a request has an associated virtual address.
Andreas Sandberg [Tue, 9 Sep 2014 08:36:32 +0000 (04:36 -0400)]
sim: Fix resource leak in BaseGlobalEvent
Static analysis revealed that BaseGlobalEvent::barrier was never
deallocated. This changeset solves this leak by making the barrier
allocation a part of the BaseGlobalEvent instead of storing a pointer
to a separate heap-allocated barrier.