Jakub Jelinek [Fri, 11 Jan 2019 16:01:23 +0000 (17:01 +0100)]
type_traits (__cpp_lib_is_constant_evaluated): Define.
* include/std/type_traits (__cpp_lib_is_constant_evaluated): Define.
* include/std/version (__cpp_lib_is_constant_evaluated): Define.
From-SVN: r267847
Steve Ellcey [Fri, 11 Jan 2019 15:53:02 +0000 (15:53 +0000)]
aarch64.c (aarch64_simd_call_p): New function.
2019-01-11 Steve Ellcey <sellcey@marvell.com>
* config/aarch64/aarch64.c (aarch64_simd_call_p): New function.
(aarch64_remove_extra_call_preserved_regs): New function.
(TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New macro.
* doc/tm.texi.in (TARGET_REMOVE_EXTRA_CALL_PRESERVED_REGS): New hook.
* doc/tm.texi: Regenerate.
* final.c (get_call_reg_set_usage): Call new hook.
* target.def (remove_extra_call_preserved_regs): New hook.
* targhooks.c (default_remove_extra_call_preserved_regs): New function.
* targhooks.h (default_remove_extra_call_preserved_regs): New function.
From-SVN: r267846
Jonathan Wakely [Fri, 11 Jan 2019 14:54:49 +0000 (14:54 +0000)]
PR libstdc++/88802 define std::hash<nullptr_t> for C++17
PR libstdc++/88802
* include/bits/functional_hash.h (hash<nullptr_t>): Define
specialization for C++17 (P0513R0, LWG 2817).
* testsuite/20_util/hash/nullptr.cc: New test.
From-SVN: r267845
Tamar Christina [Fri, 11 Jan 2019 14:20:58 +0000 (14:20 +0000)]
Fix arm testism regression.
gcc/testsuite/ChangeLog:
2019-01-11 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: Require neon
and add options.
From-SVN: r267843
Thomas Schwinge [Fri, 11 Jan 2019 13:55:01 +0000 (14:55 +0100)]
Better distinguish OpenACC and OpenMP sections in libgomp.texi
2019-01-11 Thomas Schwinge <thomas@codesourcery.com>
James Norris <jnorris@codesourcery.com>
* libgomp.texi: Better distinguish OpenACC and OpenMP "Runtime
Library Routines", and "Environment Variables".
Co-Authored-By: James Norris <jnorris@codesourcery.com>
From-SVN: r267841
Martin Liska [Fri, 11 Jan 2019 13:20:01 +0000 (14:20 +0100)]
Add a testcase (PR middle-end/88758).
2019-01-11 Martin Liska <mliska@suse.cz>
PR middle-end/88758
* g++.dg/lto/pr88758_0.C: New test.
* g++.dg/lto/pr88758_1.C: New test.
From-SVN: r267840
Jakub Jelinek [Fri, 11 Jan 2019 12:05:54 +0000 (13:05 +0100)]
re PR bootstrap/88714 (bootstrap comparison failure on armv7l since r265398)
PR bootstrap/88714
* passes.c (finish_optimization_passes): Call print_combine_total_stats
inside of pass_combine_1 dump rather than pass_profile_1.
From-SVN: r267839
Tom de Vries [Fri, 11 Jan 2019 11:46:43 +0000 (11:46 +0000)]
[nvptx] Don't allow vector_length 64 with num_workers 16
When using a compiler build with:
...
+#define PTX_DEFAULT_VECTOR_LENGTH PTX_CTA_SIZE
...
consider a test-case:
...
int
main (void)
{
#pragma acc parallel vector_length (64)
#pragma acc loop worker
for (unsigned int i = 0; i < 32; i++)
#pragma acc loop vector
for (unsigned int j = 0; j < 64; j++)
;
return 0;
}
...
If num_workers is 16, either because:
- we add a "num_workers (16)" clause on the parallel directive, or
- we set "GOMP_OPENACC_DIM=:16:", or
- the libgomp plugin chooses 16 num_workers
we run into an illegal instruction at runtime, because a bar.sync instruction
tries to use a barrier 16. The instruction is illegal, because ptx supports
only 16 barriers per CTA, and the valid range is 0..15.
The problem is that with a warp-multiple vector length, we use a code generation
scheme with a per-worker barrier. And because barrier zero is reserved for
per-cta barrier, only the remaining 15 barriers can be used as per-worker
barrier, and consequently we can't use num_workers larger than 15.
This problem occurs only for vector_length 64. For vector_length 32, we use a
different code generation scheme, and for vector_length >= 96, the maximum
num_workers is not big enough not to trigger this problem.
Also, this problem only occurs for num_workers 16. As explained above,
num_workers 15 is safe to use, and 16 is already the maximum num_workers for
vector_length 64.
This patch fixes the problem in both the compiler (handling "num_workers (16)")
and in the libgomp nvptx plugin (with and without "GOMP_OPENACC_DIM=:16:").
2019-01-11 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx.c (PTX_CTA_NUM_BARRIERS, PTX_PER_CTA_BARRIER)
(PTX_NUM_PER_CTA_BARRIER, PTX_FIRST_PER_WORKER_BARRIER)
(PTX_NUM_PER_WORKER_BARRIERS): Define.
(nvptx_apply_dim_limits): Prevent vector_length 64 and
num_workers 16.
* plugin/plugin-nvptx.c (nvptx_exec): Prevent vector_length 64 and
num_workers 16.
From-SVN: r267838
Tom de Vries [Fri, 11 Jan 2019 11:46:31 +0000 (11:46 +0000)]
[nvptx] Move PTX_CTA_SIZE up
Move the defition of PTX_CTA_SIZE up in nvptx.c.
2019-01-11 Tom de Vries <tdevries@suse.de>
* config/nvptx/nvptx.c (PTX_CTA_SIZE): Move up.
From-SVN: r267837
Tom de Vries [Fri, 11 Jan 2019 11:46:06 +0000 (11:46 +0000)]
[libgomp, testsuite, openacc] Remove -foffload=-w in reduction-[1-5].c
Before the commit "[libgomp, testsuite, openacc] Don't use const int for
dimensions", the "const int" construct was used to set launch dimensions in
reductions-[1-5].c. In the case of -xc -O0, the const int is implemented as a
variable by the C front-end. Consequently, the nvptx back-end generated
warnings that vector_length was overridden to be hard-coded, rather than left to
be set at runtime. The test-cases silenced these warnings by switching off all
warnings in the accelerator compiler using "-foffload=-w".
Given that no warnings occur anymore, remove the "-foffload=-w" setting.
2019-01-11 Tom de Vries <tdevries@suse.de>
* testsuite/libgomp.oacc-c-c++-common/reduction-1.c: Remove
-foffload=-w.
* testsuite/libgomp.oacc-c-c++-common/reduction-2.c: Same.
* testsuite/libgomp.oacc-c-c++-common/reduction-3.c: Same.
* testsuite/libgomp.oacc-c-c++-common/reduction-4.c: Same.
* testsuite/libgomp.oacc-c-c++-common/reduction-5.c: Same.
From-SVN: r267836
Tom de Vries [Fri, 11 Jan 2019 11:45:55 +0000 (11:45 +0000)]
[nvptx, testsuite, openacc, libgomp] Add insufficient-resources.c
Add a test-case that tests the "insufficient resources" fatal in the nvptx
libgomp plugin.
2019-01-11 Tom de Vries <tdevries@suse.de>
* testsuite/libgomp.oacc-c-c++-common/insufficient-resources.c: New
test.
From-SVN: r267835
Jonathan Wakely [Fri, 11 Jan 2019 11:39:45 +0000 (11:39 +0000)]
PR libstdc++/88125 remove duplicate entry in linker script
PR libstdc++/88125
* config/abi/pre/gnu.ver (GLIBCXX_3.4.6): Remove unused duplicate
pattern for std::basic_stringbuf::str().
From-SVN: r267834
Jan Beulich [Fri, 11 Jan 2019 11:20:40 +0000 (11:20 +0000)]
x86-64: {,V}CVT{,U}SI2Sx are ambiguous without suffix
For 64-bit these should not be emitted without suffix in AT&T mode (as
being ambiguous that way); the suffixes are benign for 32-bit. For
consistency also omit the suffix in Intel mode for {,V}CVTSI2SxQ.
The omission has originally (prior to rev 260691) lead to wrong code
being generated for the 64-bit unsigned-to-float/double conversions (as
gas guesses an L suffix instead of the required Q one when the operand
is in memory). In all remaining cases (being changed here) the omission
would "just" lead to warnings with future gas versions.
As a result, arrange to check for the L suffixes in 32-bit test cases.
In order for related test cases to actually test what they're supposed
to test, add (seemingly unrelated) a few empty "asm volatile()".
Presumably there are more where constant propagation voids the intended
effect of the tests, but these are ones helping make sure the assembler
actually still assembles correctly the output after the changes here.
From-SVN: r267833
Jonathan Wakely [Fri, 11 Jan 2019 10:25:46 +0000 (10:25 +0000)]
Fix incorrect linker script patterns
The recent changes to support operator<<(nullptr_t) changed the glob
patterns for existing operator<<(T) overloads, but did so incorrectly so
they still matched the new symbols. That broke Solaris bootstrap. This
patch replaces each of the existing globs by two more precise ones,
which match the old symbols but not the new ones.
* config/abi/pre/gnu.ver (GLIBCXX_3.4): Correct recent changes to
basic_ostream::operator<< patterns.
From-SVN: r267832
Jakub Jelinek [Fri, 11 Jan 2019 10:17:12 +0000 (11:17 +0100)]
re PR rtl-optimization/88296 (Infinite loop in lra_split_hard_reg_for)
PR rtl-optimization/88296
* gcc.target/i386/pr88296.c: New test.
From-SVN: r267831
Paolo Carlini [Fri, 11 Jan 2019 09:02:43 +0000 (09:02 +0000)]
decl.c (start_decl): Improve error location.
/cp
2019-01-11 Paolo Carlini <paolo.carlini@oracle.com>
* decl.c (start_decl): Improve error location.
(grokdeclarator): Likewise, improve two locations.
/testsuite
2019-01-11 Paolo Carlini <paolo.carlini@oracle.com>
* g++.dg/diagnostic/extern-initialized.C: New.
* g++.dg/ext/dllimport-initialized.C: Likewise.
From-SVN: r267830
Thomas Koenig [Fri, 11 Jan 2019 06:32:10 +0000 (06:32 +0000)]
re PR fortran/59345 (_gfortran_internal_pack on compiler generated temps)
2019-01-11 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/59345
* trans-array.c (gfc_conv_parameter_array): Temporary
arrays generated for expressions do not need to be repacked.
2019-01-11 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/59345
* gfortran.dg/internal_pack_16.f90: New test.
From-SVN: r267829
GCC Administrator [Fri, 11 Jan 2019 00:16:19 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r267828
Jakub Jelinek [Thu, 10 Jan 2019 23:20:19 +0000 (00:20 +0100)]
re PR target/88785 (ICE in as_a, at machmode.h:353)
PR target/88785
* config/i386/sse.md (float<floatunssuffix>v2div2sf2): Turn into
define_expand.
(*float<floatunssuffix>v2div2sf2): New define_insn.
(float<floatunssuffix>v2div2sf2_mask): Turn into define_expand.
(*float<floatunssuffix>v2div2sf2_mask): New define_insn.
(*float<floatunssuffix>v2div2sf2_mask_1): Replace
subrtxes (const_vector:V2SF [(const_int 0) (const_int 0)]) with
match_operands with "const0_operand" "C".
* g++.target/i386/pr88785.C: New test.
From-SVN: r267825
Tamar Christina [Thu, 10 Jan 2019 22:28:00 +0000 (22:28 +0000)]
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_init_builtins): Move aarch64_init_fcmla_laneq_builtins...
(aarch64_init_simd_builtins): ...Here.
From-SVN: r267824
Vladimir Makarov [Thu, 10 Jan 2019 21:02:50 +0000 (21:02 +0000)]
re PR rtl-optimization/87305 (Segfault in end_hard_regno in setup_live_pseudos_and_spill_after_risky_transforms on aarch64 big-endian)
2019-01-10 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/87305
* lra-assigns.c
(setup_live_pseudos_and_spill_after_risky_transforms): Check
allocation for big endian pseudos used as paradoxical subregs and
spill them if it is wrong.
* lra-constraints.c (lra_constraints): Add a comment.
2019-01-10 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/87305
* gcc.target/aarch64/pr87305.c: New.
From-SVN: r267823
Richard Biener [Thu, 10 Jan 2019 18:58:08 +0000 (18:58 +0000)]
re PR tree-optimization/88792 (wrong-code in RPO VN since r263875)
2019-01-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/88792
* tree-ssa-pre.c (get_representative_for): Do not return a
value-number here.
* gcc.dg/torture/pr88792.c: New testcase.
From-SVN: r267821
Steven G. Kargl [Thu, 10 Jan 2019 18:45:38 +0000 (18:45 +0000)]
re PR fortran/86322 (ICE in reference_record with data statement)
2019-01-10 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/86322
* decl.c (top_var_list): Set locus of expr.
(gfc_match_data): Detect pointer on non-rightmost part-refs.
2019-01-10 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/86322
* gfortran.dg/pr86322_1.f90: New test.
* gfortran.dg/pr86322_2.f90: Ditto.
* gfortran.dg/pr86322_3.f90: Ditto.
From-SVN: r267820
Sudakshina Das [Thu, 10 Jan 2019 17:29:54 +0000 (17:29 +0000)]
[Committed, AArch64] Disable tests for ilp32.
Currently Return Address Signing is only supported in lp64. Thus the
tests that I added recently (that enables return address signing by the
mbranch-protection=standard option), should also be exempted from testing in
ilp32. This patch adds the needed dg-require-effective-target directive in the
tests.
*** gcc/testsuite/ChangeLog ***
2019-01-10 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/bti-1.c: Exempt for ilp32.
* gcc.target/aarch64/bti-2.c: Likewise.
* gcc.target/aarch64/bti-3.c: Likewise.
Committed as obvious.
From-SVN: r267818
Jakub Jelinek [Thu, 10 Jan 2019 15:44:16 +0000 (16:44 +0100)]
re PR middle-end/84877 (Local stack copy of BLKmode parameter on the stack is not aligned when the requested alignment exceeds MAX_SUPPORTED_STACK_ALIGNMENT)
PR middle-end/84877
PR bootstrap/88450
* function.c (assign_stack_local_1): Revert the 2018-11-21 changes.
(assign_parm_setup_block): Do the argument slot realignment here
instead.
From-SVN: r267812
Jonathan Wakely [Thu, 10 Jan 2019 15:39:28 +0000 (15:39 +0000)]
Fix filesystem::last_write_time failure with 32-bit time_t
* testsuite/27_io/filesystem/operations/last_write_time.cc: Fix
test failures on targets with 32-bit time_t.
From-SVN: r267811
Jonathan Wakely [Thu, 10 Jan 2019 13:49:31 +0000 (13:49 +0000)]
Define __cpp_lib_erase_if feature test macro
The C++2a draft specifies the value 201811L for this, but as an
extension we return the number of elements erased. This is expected to
be standardised, so the macro has the value 201900L until a proper value
is specified in the draft.
* include/bits/erase_if.h: Define __cpp_lib_erase_if.
* include/std/deque: Likewise.
* include/std/forward_list: Likewise.
* include/std/list: Likewise.
* include/std/string: Likewise.
* include/std/vector: Likewise.
* include/std/version: Likewise.
* testsuite/21_strings/basic_string/erasure.cc: Test macro.
* testsuite/23_containers/deque/erasure.cc: Likewise.
* testsuite/23_containers/forward_list/erasure.cc: Likewise.
* testsuite/23_containers/list/erasure.cc: Likewise.
* testsuite/23_containers/map/erasure.cc: Likewise.
* testsuite/23_containers/set/erasure.cc: Likewise.
* testsuite/23_containers/unordered_map/erasure.cc: Likewise.
* testsuite/23_containers/unordered_set/erasure.cc: Likewise.
* testsuite/23_containers/vector/erasure.cc: Likewise.
From-SVN: r267810
Jonathan Wakely [Thu, 10 Jan 2019 13:21:54 +0000 (13:21 +0000)]
Check AI_NUMERICSERV is defined before using it
The AI_NUMERICSERV constant is missing from old Darwin systems, so only
use it if it's supported.
* include/experimental/internet [AI_NUMERICSERV]
(resolver_base::numeric_service): Define conditionally.
* testsuite/experimental/net/internet/resolver/base.cc: Test it
conditionally.
* testsuite/experimental/net/internet/resolver/ops/lookup.cc:
Likewise.
From-SVN: r267809
Ville Voutilainen [Thu, 10 Jan 2019 13:14:57 +0000 (15:14 +0200)]
Implement LWG 2221: formatted output operator for nullptr
2019-01-10 Ville Voutilainen <ville.voutilainen@gmail.com>
Jonathan Wakely <jwakely@redhat.com>
Implement LWG 2221
* config/abi/pre/gnu.ver (GLIBCXX_3.4): Tighten patterns.
(GLIBCXX_3.4.26): Add new exports.
* include/Makefile.am: Add ostream-inst.cc. Move string-inst.cc to
correct list of sources.
* include/Makefile.in: Regenerate.
* include/std/ostream (operator<<(nullptr_t)): New member function.
* src/c++17/ostream-inst.cc: New file.
* testsuite/27_io/basic_ostream/inserters_other/char/lwg2221.cc: New
test.
Co-Authored-By: Jonathan Wakely <jwakely@redhat.com>
From-SVN: r267808
Nathan Sidwell [Thu, 10 Jan 2019 12:32:03 +0000 (12:32 +0000)]
Add testcase from PR71959
libgomp/
PR lto/71959
* testsuite/libgomp.oacc-c++/pr71959-aux.cc: New.
* testsuite/libgomp.oacc-c++/pr71959.C: New.
Co-Authored-By: Julian Brown <julian@codesourcery.com>
From-SVN: r267806
Stefan Agner [Thu, 10 Jan 2019 11:36:42 +0000 (12:36 +0100)]
ARM: fix -masm-syntax-unified (PR88648)
This allows to use unified asm syntax when compiling for the
ARM instruction. This matches documentation and seems what the
initial patch was intended doing when the flag got added.
2019-01-10 Stefan Agner <stefan@agner.ch>
PR target/88648
* config/arm/arm.c (arm_option_override_internal): Force
opts->x_inline_asm_unified to true only if TARGET_THUMB2_P.
* gcc.target/arm/pr88648-asm-syntax-unified.c: Add test to
check if -masm-syntax-unified gets applied properly.
From-SVN: r267804
Jonathan Wakely [Thu, 10 Jan 2019 11:12:00 +0000 (11:12 +0000)]
Include name of test in filesystem-test.XXXXXX filenames
Also fix some tests that were not cleaning up after themselves, as
identified by the change to nonexistent_path.
* testsuite/util/testsuite_fs.h (nonexistent_path): Include name
of the source file containing the caller.
* testsuite/27_io/filesystem/iterators/directory_iterator.cc: Remove
directories created by test.
* testsuite/27_io/filesystem/iterators/recursive_directory_iterator.cc:
Likewise.
* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
Likewise.
* testsuite/experimental/filesystem/iterators/
recursive_directory_iterator.cc: Likewise.
From-SVN: r267801
Jakub Jelinek [Thu, 10 Jan 2019 10:56:56 +0000 (11:56 +0100)]
re PR tree-optimization/88775 (Optimize std::string assignment)
PR tree-optimization/88775
* include/bits/stl_function.h (greater<_Tp*>::operator(),
less<_Tp*>::operator(), greater_equal<_Tp*>::operator(),
less_equal<_Tp*>::operator()): Use __builtin_is_constant_evaluated
instead of __builtin_constant_p if available. Don't bother with
the pointer comparison in C++11 and earlier.
From-SVN: r267800
Jakub Jelinek [Thu, 10 Jan 2019 10:44:46 +0000 (11:44 +0100)]
re PR c/88568 ('dllimport' no longer implies 'extern' in C)
PR c/88568
* attribs.c (handle_dll_attribute): Clear TREE_STATIC after setting
DECL_EXTERNAL.
* gcc.dg/pr88568.c: New test.
From-SVN: r267799
Eric Botcazou [Thu, 10 Jan 2019 07:21:35 +0000 (07:21 +0000)]
Fix formatting
From-SVN: r267797
Tamar Christina [Thu, 10 Jan 2019 03:34:06 +0000 (03:34 +0000)]
arm-builtins.c (enum arm_type_qualifiers): Add qualifier_lane_pair_index.
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/arm/arm-builtins.c
(enum arm_type_qualifiers): Add qualifier_lane_pair_index.
(MAC_LANE_PAIR_QUALIFIERS): New.
(arm_expand_builtin_args): Use it.
(arm_expand_builtin_1): Likewise.
* config/arm/arm-protos.h (neon_vcmla_lane_prepare_operands): New.
* config/arm/arm.c (neon_vcmla_lane_prepare_operands): New.
* config/arm/arm-c.c (arm_cpu_builtins): Add __ARM_FEATURE_COMPLEX.
* config/arm/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/arm/arm_neon_builtins.def (vcadd90, vcadd270, vcmla0, vcmla90,
vcmla180, vcmla270, vcmla_lane0, vcmla_lane90, vcmla_lane180, vcmla_lane270,
vcmla_laneq0, vcmla_laneq90, vcmla_laneq180, vcmla_laneq270,
vcmlaq_lane0, vcmlaq_lane90, vcmlaq_lane180, vcmlaq_lane270): New.
* config/arm/neon.md (neon_vcmla_lane<rot><mode>,
neon_vcmla_laneq<rot><mode>, neon_vcmlaq_lane<rot><mode>): New.
* config/arm/arm.c (arm_arch8_3, arm_arch8_4): New.
* config/arm/arm.h (TARGET_COMPLEX, arm_arch8_3, arm_arch8_4): New.
(arm_option_reconfigure_globals): Use them.
* config/arm/iterators.md (VDF, VQ_HSF): New.
(VCADD, VCMLA): New.
(VF_constraint, rot, rotsplit1, rotsplit2): Add V4HF and V8HF.
* config/arm/neon.md (neon_vcadd<rot><mode>, neon_vcmla<rot><mode>): New.
* config/arm/unspecs.md (UNSPEC_VCADD90, UNSPEC_VCADD270,
UNSPEC_VCMLA, UNSPEC_VCMLA90, UNSPEC_VCMLA180, UNSPEC_VCMLA270): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: Add AArch32 regexpr.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: Likewise.
From-SVN: r267796
Tamar Christina [Thu, 10 Jan 2019 03:30:59 +0000 (03:30 +0000)]
aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
gcc/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers): Add qualifier_lane_pair_index.
(emit-rtl.h): Include.
(TYPES_QUADOP_LANE_PAIR): New.
(aarch64_simd_expand_args): Use it.
(aarch64_simd_expand_builtin): Likewise.
(AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_laneq_builtin_datum): New.
(FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin): New.
(aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
(aarch64_expand_buildin): Add AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF, AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
* config/aarch64/iterators.md (FCMLA_maybe_lane): New.
* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add __ARM_FEATURE_COMPLEX.
* config/aarch64/aarch64-simd-builtins.def (
fcadd90,
fcadd270, fcmla0, fcmla90,
fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180, fcmla_lane270,
fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
* config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
aarch64_fcmla_laneq<rot>v4hf, aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
aarch64_fcmla<rot><mode>): New.
* config/aarch64/arm_neon.h:
(vcadd_rot90_f16): New.
(vcaddq_rot90_f16): New.
(vcadd_rot270_f16): New.
(vcaddq_rot270_f16): New.
(vcmla_f16): New.
(vcmlaq_f16): New.
(vcmla_lane_f16): New.
(vcmla_laneq_f16): New.
(vcmlaq_lane_f16): New.
(vcmlaq_rot90_lane_f16): New.
(vcmla_rot90_laneq_f16): New.
(vcmla_rot90_lane_f16): New.
(vcmlaq_rot90_f16): New.
(vcmla_rot90_f16): New.
(vcmlaq_laneq_f16): New.
(vcmla_rot180_laneq_f16): New.
(vcmla_rot180_lane_f16): New.
(vcmlaq_rot180_f16): New.
(vcmla_rot180_f16): New.
(vcmlaq_rot90_laneq_f16): New.
(vcmlaq_rot270_laneq_f16): New.
(vcmlaq_rot270_lane_f16): New.
(vcmla_rot270_laneq_f16): New.
(vcmlaq_rot270_f16): New.
(vcmla_rot270_f16): New.
(vcmlaq_rot180_laneq_f16): New.
(vcmlaq_rot180_lane_f16): New.
(vcmla_rot270_lane_f16): New.
(vcadd_rot90_f32): New.
(vcaddq_rot90_f32): New.
(vcaddq_rot90_f64): New.
(vcadd_rot270_f32): New.
(vcaddq_rot270_f32): New.
(vcaddq_rot270_f64): New.
(vcmla_f32): New.
(vcmlaq_f32): New.
(vcmlaq_f64): New.
(vcmla_lane_f32): New.
(vcmla_laneq_f32): New.
(vcmlaq_lane_f32): New.
(vcmlaq_laneq_f32): New.
(vcmla_rot90_f32): New.
(vcmlaq_rot90_f32): New.
(vcmlaq_rot90_f64): New.
(vcmla_rot90_lane_f32): New.
(vcmla_rot90_laneq_f32): New.
(vcmlaq_rot90_lane_f32): New.
(vcmlaq_rot90_laneq_f32): New.
(vcmla_rot180_f32): New.
(vcmlaq_rot180_f32): New.
(vcmlaq_rot180_f64): New.
(vcmla_rot180_lane_f32): New.
(vcmla_rot180_laneq_f32): New.
(vcmlaq_rot180_lane_f32): New.
(vcmlaq_rot180_laneq_f32): New.
(vcmla_rot270_f32): New.
(vcmlaq_rot270_f32): New.
(vcmlaq_rot270_f64): New.
(vcmla_rot270_lane_f32): New.
(vcmla_rot270_laneq_f32): New.
(vcmlaq_rot270_lane_f32): New.
(vcmlaq_rot270_laneq_f32): New.
* config/aarch64/aarch64.h (TARGET_COMPLEX): New.
* config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270): New.
(FCADD, FCMLA): New.
(rot): New.
* config/arm/types.md (neon_fcadd, neon_fcmla): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
* gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New test.
From-SVN: r267795
Tamar Christina [Thu, 10 Jan 2019 03:27:13 +0000 (03:27 +0000)]
target-supports.exp (check_effective_target_arm_v8_3a_complex_neon_ok_nocache, [...]): New.
gcc/testsuite/ChangeLog:
2019-01-10 Tamar Christina <tamar.christina@arm.com>
* lib/target-supports.exp
(check_effective_target_arm_v8_3a_complex_neon_ok_nocache,
check_effective_target_arm_v8_3a_complex_neon_ok,
add_options_for_arm_v8_3a_complex_neon,
check_effective_target_arm_v8_3a_complex_neon_hw,
check_effective_target_vect_complex_rot_N): New.
From-SVN: r267794
Steven G. Kargl [Thu, 10 Jan 2019 01:11:51 +0000 (01:11 +0000)]
re PR fortran/88376 (ICE in is_illegal_recursion, at fortran/resolve.c:1689)
2019-01-09 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/88376
* resolve.c (is_illegal_recursion): Remove an assert().
2019-01-09 Steven G. Kargl <kargl@gcc.gnu.org>
PR fortran/88376
* gfortran.dg/pr88376.f90: New test.
From-SVN: r267793
GCC Administrator [Thu, 10 Jan 2019 00:16:43 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r267792
Ian Lance Taylor [Wed, 9 Jan 2019 23:38:55 +0000 (23:38 +0000)]
re PR go/86343 (types built by GO share TYPE_FIELDS in unsupported way)
PR go/86343
* go-gcc.cc (Gcc_backend::set_placeholder_struct_type): Go back to
build_distinct_type_copy, but copy the fields so that they have
the right DECL_CONTEXT.
From-SVN: r267789
Iain Buclaw [Wed, 9 Jan 2019 23:04:20 +0000 (23:04 +0000)]
libphobos: Merge phobos upstream
b022e552a
This removes updates the removal date of all deprecations in phobos.
Many of the marked functions have passed their end dates, and are now
absent in upstream.
Reviewed-on: https://github.com/dlang/phobos/pull/6828
From-SVN: r267788
Sandra Loosemore [Wed, 9 Jan 2019 21:46:45 +0000 (16:46 -0500)]
PR other/16615 [5/5]
2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
PR other/16615 [5/5]
gcc/po/
* gcc.pot: Regenerate.
From-SVN: r267787
Sandra Loosemore [Wed, 9 Jan 2019 21:44:56 +0000 (16:44 -0500)]
PR other/16615 [4/5]
2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
PR other/16615 [4/5]
gcc/
* config/pa/pa.c: Change "can not" to "cannot".
* gimple-ssa-evrp-analyze.c: Likewise.
* ipa-icf.c: Likewise.
* ipa-polymorphic-call.c: Likewise.
* ipa-pure-const.c: Likewise.
* lra-constraints.c: Likewise.
* lra-remat.c: Likewise.
* reload1.c: Likewise.
* reorg.c: Likewise.
* tree-ssa-uninit.c: Likewise.
gcc/ada/
* exp_ch11.adb: Change "can not" to "cannot".
* sem_ch4.adb: Likewise.
gcc/fortran/
* expr.c: Change "can not" to "cannot".
libobjc/
* objc/runtime.h: Change "can not" to "cannot".
From-SVN: r267786
Sandra Loosemore [Wed, 9 Jan 2019 21:41:36 +0000 (16:41 -0500)]
PR other/16615 [3/5]
2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
PR other/16615 [3/5]
gcc/testsuite/
* g++.dg/lto/odr-1_1.C: Update diagnostic message patterns to replace
"can not" with "cannot".
* gfortran.dg/common_15.f90: Likewise.
* gfortran.dg/derived_result_2.f90: Likewise.
* gfortran.dg/do_check_6.f90: Likewise.
* gfortran.dg/namelist_args.f90: Likewise.
* gfortran.dg/negative_unit_check.f90: Likewise.
* gfortran.dg/pure_formal_3.f90: Likewise.
* obj-c++.dg/attributes/method-attribute-2.mm: Likewise.
* obj-c++.dg/exceptions-3.mm: Likewise.
* obj-c++.dg/exceptions-4.mm: Likewise.
* obj-c++.dg/exceptions-5.mm: Likewise.
* obj-c++.dg/property/at-property-23.mm: Likewise.
* obj-c++.dg/property/dotsyntax-17.mm: Likewise.
* obj-c++.dg/property/property-neg-7.mm: Likewise.
* objc.dg/attributes/method-attribute-2.m: Likewise.
* objc.dg/exceptions-3.m: Likewise.
* objc.dg/exceptions-4.m: Likewise.
* objc.dg/exceptions-5.m: Likewise.
* objc.dg/param-1.m: Likewise.
* objc.dg/property/at-property-23.m: Likewise.
* objc.dg/property/dotsyntax-17.m: Likewise.
* objc.dg/property/property-neg-7.m: Likewise.
From-SVN: r267785
Sandra Loosemore [Wed, 9 Jan 2019 21:39:49 +0000 (16:39 -0500)]
PR other/16615 [2/5]
2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
PR other/16615 [2/5]
include/
* libiberty.h: Mechanically replace "can not" with "cannot".
* plugin-api.h: Likewise.
libiberty/
* cp-demangle.c: Mechanically replace "can not" with "cannot".
* floatformat.c: Likewise.
* strerror.c: Likewise.
From-SVN: r267784
Sandra Loosemore [Wed, 9 Jan 2019 21:37:45 +0000 (16:37 -0500)]
PR other/16615 [1/5]
2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
PR other/16615 [1/5]
contrib/
* mklog: Mechanically replace "can not" with "cannot".
gcc/
* Makefile.in: Mechanically replace "can not" with "cannot".
* alias.c: Likewise.
* builtins.c: Likewise.
* calls.c: Likewise.
* cgraph.c: Likewise.
* cgraph.h: Likewise.
* cgraphclones.c: Likewise.
* cgraphunit.c: Likewise.
* combine-stack-adj.c: Likewise.
* combine.c: Likewise.
* common/config/i386/i386-common.c: Likewise.
* config/aarch64/aarch64.c: Likewise.
* config/alpha/sync.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/predicates.md: Likewise.
* config/arm/arm-c.c: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/arm.h: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/cortex-r4f.md: Likewise.
* config/csky/csky.c: Likewise.
* config/csky/csky.h: Likewise.
* config/darwin-f.c: Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/sol2.h: Likewise.
* config/m68k/m68k.c: Likewise.
* config/mcore/mcore.h: Likewise.
* config/microblaze/microblaze.md: Likewise.
* config/mips/20kc.md: Likewise.
* config/mips/sb1.md: Likewise.
* config/nds32/nds32.c: Likewise.
* config/nds32/predicates.md: Likewise.
* config/pa/pa.c: Likewise.
* config/rs6000/
e300c2c3.md: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/s390/s390.h: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.md: Likewise.
* config/spu/vmx2spu.h: Likewise.
* cprop.c: Likewise.
* dbxout.c: Likewise.
* df-scan.c: Likewise.
* doc/cfg.texi: Likewise.
* doc/extend.texi: Likewise.
* doc/fragments.texi: Likewise.
* doc/gty.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/lto.texi: Likewise.
* doc/md.texi: Likewise.
* doc/objc.texi: Likewise.
* doc/rtl.texi: Likewise.
* doc/tm.texi: Likewise.
* dse.c: Likewise.
* emit-rtl.c: Likewise.
* emit-rtl.h: Likewise.
* except.c: Likewise.
* expmed.c: Likewise.
* expr.c: Likewise.
* fold-const.c: Likewise.
* genautomata.c: Likewise.
* gimple-fold.c: Likewise.
* hard-reg-set.h: Likewise.
* ifcvt.c: Likewise.
* ipa-comdats.c: Likewise.
* ipa-cp.c: Likewise.
* ipa-devirt.c: Likewise.
* ipa-fnsummary.c: Likewise.
* ipa-icf.c: Likewise.
* ipa-inline-transform.c: Likewise.
* ipa-inline.c: Likewise.
* ipa-polymorphic-call.c: Likewise.
* ipa-profile.c: Likewise.
* ipa-prop.c: Likewise.
* ipa-pure-const.c: Likewise.
* ipa-reference.c: Likewise.
* ipa-split.c: Likewise.
* ipa-visibility.c: Likewise.
* ipa.c: Likewise.
* ira-build.c: Likewise.
* ira-color.c: Likewise.
* ira-conflicts.c: Likewise.
* ira-costs.c: Likewise.
* ira-int.h: Likewise.
* ira-lives.c: Likewise.
* ira.c: Likewise.
* ira.h: Likewise.
* loop-invariant.c: Likewise.
* loop-unroll.c: Likewise.
* lower-subreg.c: Likewise.
* lra-assigns.c: Likewise.
* lra-constraints.c: Likewise.
* lra-eliminations.c: Likewise.
* lra-lives.c: Likewise.
* lra-remat.c: Likewise.
* lra-spills.c: Likewise.
* lra.c: Likewise.
* lto-cgraph.c: Likewise.
* lto-streamer-out.c: Likewise.
* postreload-gcse.c: Likewise.
* predict.c: Likewise.
* profile-count.h: Likewise.
* profile.c: Likewise.
* recog.c: Likewise.
* ree.c: Likewise.
* reload.c: Likewise.
* reload1.c: Likewise.
* reorg.c: Likewise.
* resource.c: Likewise.
* rtl.def: Likewise.
* rtl.h: Likewise.
* rtlanal.c: Likewise.
* sched-deps.c: Likewise.
* sched-ebb.c: Likewise.
* sched-rgn.c: Likewise.
* sel-sched-ir.c: Likewise.
* sel-sched.c: Likewise.
* shrink-wrap.c: Likewise.
* simplify-rtx.c: Likewise.
* symtab.c: Likewise.
* target.def: Likewise.
* toplev.c: Likewise.
* tree-call-cdce.c: Likewise.
* tree-cfg.c: Likewise.
* tree-complex.c: Likewise.
* tree-core.h: Likewise.
* tree-eh.c: Likewise.
* tree-inline.c: Likewise.
* tree-loop-distribution.c: Likewise.
* tree-nrv.c: Likewise.
* tree-profile.c: Likewise.
* tree-sra.c: Likewise.
* tree-ssa-alias.c: Likewise.
* tree-ssa-dce.c: Likewise.
* tree-ssa-dom.c: Likewise.
* tree-ssa-forwprop.c: Likewise.
* tree-ssa-loop-im.c: Likewise.
* tree-ssa-loop-ivcanon.c: Likewise.
* tree-ssa-loop-ivopts.c: Likewise.
* tree-ssa-loop-niter.c: Likewise.
* tree-ssa-phionlycprop.c: Likewise.
* tree-ssa-phiopt.c: Likewise.
* tree-ssa-propagate.c: Likewise.
* tree-ssa-threadedge.c: Likewise.
* tree-ssa-threadupdate.c: Likewise.
* tree-ssa-uninit.c: Likewise.
* tree-ssanames.c: Likewise.
* tree-streamer-out.c: Likewise.
* tree.c: Likewise.
* tree.h: Likewise.
* vr-values.c: Likewise.
gcc/ada/
* exp_ch9.adb: Mechanically replace "can not" with "cannot".
* libgnat/s-regpat.ads: Likewise.
* par-ch4.adb: Likewise.
* set_targ.adb: Likewise.
* types.ads: Likewise.
gcc/cp/
* cp-tree.h: Mechanically replace "can not" with "cannot".
* parser.c: Likewise.
* pt.c: Likewise.
gcc/fortran/
* class.c: Mechanically replace "can not" with "cannot".
* decl.c: Likewise.
* expr.c: Likewise.
* gfc-internals.texi: Likewise.
* intrinsic.texi: Likewise.
* invoke.texi: Likewise.
* io.c: Likewise.
* match.c: Likewise.
* parse.c: Likewise.
* primary.c: Likewise.
* resolve.c: Likewise.
* symbol.c: Likewise.
* trans-array.c: Likewise.
* trans-decl.c: Likewise.
* trans-intrinsic.c: Likewise.
* trans-stmt.c: Likewise.
gcc/go/
* go-backend.c: Mechanically replace "can not" with "cannot".
* go-gcc.cc: Likewise.
gcc/lto/
* lto-partition.c: Mechanically replace "can not" with "cannot".
* lto-symtab.c: Likewise.
* lto.c: Likewise.
gcc/objc/
* objc-act.c: Mechanically replace "can not" with "cannot".
libbacktrace/
* backtrace.h: Mechanically replace "can not" with "cannot".
libgcc/
* config/c6x/libunwind.S: Mechanically replace "can not" with
"cannot".
* config/tilepro/atomic.h: Likewise.
* config/vxlib-tls.c: Likewise.
* generic-morestack-thread.c: Likewise.
* generic-morestack.c: Likewise.
* mkmap-symver.awk: Likewise.
libgfortran/
* caf/single.c: Mechanically replace "can not" with "cannot".
* io/unit.c: Likewise.
libobjc/
* class.c: Mechanically replace "can not" with "cannot".
* objc/runtime.h: Likewise.
* sendmsg.c: Likewise.
liboffloadmic/
* include/coi/common/COIResult_common.h: Mechanically replace
"can not" with "cannot".
* include/coi/source/COIBuffer_source.h: Likewise.
libstdc++-v3/
* include/ext/bitmap_allocator.h: Mechanically replace "can not"
with "cannot".
From-SVN: r267783
Thomas Koenig [Wed, 9 Jan 2019 20:31:07 +0000 (20:31 +0000)]
re PR fortran/68426 (Simplification of SPREAD with a derived type element is unimplemented)
2019-01-09 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/68426
* simplify.c (gfc_simplify_spread): Also simplify if the
type of source is an EXPR_STRUCTURE.
2019-01-09 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/68426
* gfortran.dg/spread_simplify_1.f90: New test.
From-SVN: r267781
Uros Bizjak [Wed, 9 Jan 2019 19:16:02 +0000 (20:16 +0100)]
i386-protos.h (ix86_expand_xorsign): New prototype.
* config/i386/i386-protos.h (ix86_expand_xorsign): New prototype.
(ix86_split_xorsign): Ditto.
* config/i386/i386.c (ix86_expand_xorsign): New function.
(ix86_split_xorsign): Ditto.
* config/i386/i386.md (UNSPEC_XORSIGN): New unspec.
(xorsign<mode>3): New expander.
(xorsign<mode>3_1): New insn_and_split pattern.
* config/i386/sse.md (xorsign<mode>3): New expander.
testsuite/ChangeLog:
* lib/target-supports.exp
(check_effective_target_xorsign): Add i?86-*-* and x86_64-*-* targets.
* gcc.target/i386/xorsign.c: New test.
From-SVN: r267779
Iain Buclaw [Wed, 9 Jan 2019 17:59:55 +0000 (17:59 +0000)]
Merge dmd upstream
6d5b853d3
Updates the copyright years of all d/dmd sources.
Reviewed-on: https://github.com/dlang/dmd/pull/9181
From-SVN: r267778
Eric Botcazou [Wed, 9 Jan 2019 14:47:32 +0000 (14:47 +0000)]
sparc.md (*tablejump_sp32): Merge into...
* config/sparc/sparc.md (*tablejump_sp32): Merge into...
(*tablejump_sp64): Likewise.
(*tablejump<P:mode>): ...this.
(*call_address_sp32): Merge into...
(*call_address_sp64): Likewise.
(*call_address<P:mode>): ...this.
(*call_symbolic_sp32): Merge into...
(*call_symbolic_sp64): Likewise.
(*call_symbolic<P:mode>): ...this.
(call_value): Remove constraint and add predicate.
(*call_value_address_sp32): Merge into...
(*call_value_address_sp64): Likewise.
(*call_value_address<P:mode>): ...this.
(*call_value_symbolic_sp32): Merge into...
(*call_value_symbolic_sp64): Likewise.
(*call_value_symbolic<P:mode>): ...this.
(*sibcall_symbolic_sp32): Merge into...
(*sibcall_symbolic_sp64): Likewise.
(*sibcall_symbolic<P:mode>): ...this.
(sibcall_value): Remove constraint and add predicate.
(*sibcall_value_symbolic_sp32): Merge into...
(*sibcall_value_symbolic_sp64): Likewise.
(*sibcall_value_symbolic<P:mode>): ...this.
(window_save): Minor tweak.
(*branch_sp32): Merge into...
(*branch_sp64): Likewise.
(*branch<P:mode>): ...this.
From-SVN: r267774
Eric Botcazou [Wed, 9 Jan 2019 14:34:20 +0000 (14:34 +0000)]
re PR target/84010 (problematic TLS code generation on 64-bit SPARC)
PR target/84010
* config/sparc/sparc.c (sparc_legitimize_tls_address): Only use Pmode
consistently in TLS address generation and adjust code to the renaming
of patterns. Mark calls to __tls_get_addr as const.
* config/sparc/sparc.md (tgd_hi22): Turn into...
(tgd_hi22<P:mode>): ...this and use Pmode throughout.
(tgd_lo10): Turn into...
(tgd_lo10<P:mode>): ...this and use Pmode throughout.
(tgd_add32): Merge into...
(tgd_add64): Likewise.
(tgd_add<P:mode>): ...this and use Pmode throughout.
(tldm_hi22): Turn into...
(tldm_hi22<P:mode>): ...this and use Pmode throughout.
(tldm_lo10): Turn into...
(tldm_lo10<P:mode>): ...this and use Pmode throughout.
(tldm_add32): Merge into...
(tldm_add64): Likewise.
(tldm_add<P:mode>): ...this and use Pmode throughout.
(tldm_call32): Merge into...
(tldm_call64): Likewise.
(tldm_call<P:mode>): ...this and use Pmode throughout.
(tldo_hix22): Turn into...
(tldo_hix22<P:mode>): ...this and use Pmode throughout.
(tldo_lox10): Turn into...
(tldo_lox10<P:mode>): ...this and use Pmode throughout.
(tldo_add32): Merge into...
(tldo_add64): Likewise.
(tldo_add<P:mode>): ...this and use Pmode throughout.
(tie_hi22): Turn into...
(tie_hi22<P:mode>): ...this and use Pmode throughout.
(tie_lo10): Turn into...
(tie_lo10<P:mode>): ...this and use Pmode throughout.
(tie_ld64): Use DImode throughout.
(tie_add32): Merge into...
(tie_add64): Likewise.
(tie_add<P:mode>): ...this and use Pmode throughout.
(tle_hix22_sp32): Merge into...
(tle_hix22_sp64): Likewise.
(tle_hix22<P:mode>): ...this and use Pmode throughout.
(tle_lox22_sp32): Merge into...
(tle_lox22_sp64): Likewise.
(tle_lox22<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub_sp32): Merge into...
(*tldo_ldub_sp64): Likewise.
(*tldo_ldub<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub1_sp32): Merge into...
(*tldo_ldub1_sp64): Likewise.
(*tldo_ldub1<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub2_sp32): Merge into...
(*tldo_ldub2_sp64): Likewise.
(*tldo_ldub2<P:mode>): ...this and use Pmode throughout.
(*tldo_ldsb1_sp32): Merge into...
(*tldo_ldsb1_sp64): Likewise.
(*tldo_ldsb1<P:mode>): ...this and use Pmode throughout.
(*tldo_ldsb2_sp32): Merge into...
(*tldo_ldsb2_sp64): Likewise.
(*tldo_ldsb2<P:mode>): ...this and use Pmode throughout.
(*tldo_ldub3_sp64): Use DImode throughout.
(*tldo_ldsb3_sp64): Likewise.
(*tldo_lduh_sp32): Merge into...
(*tldo_lduh_sp64): Likewise.
(*tldo_lduh<P:mode>): ...this and use Pmode throughout.
(*tldo_lduh1_sp32): Merge into...
(*tldo_lduh1_sp64): Likewise.
(*tldo_lduh1<P:mode>): ...this and use Pmode throughout.
(*tldo_ldsh1_sp32): Merge into...
(*tldo_ldsh1_sp64): Likewise.
(*tldo_ldsh1<P:mode>): ...this and use Pmode throughout.
(*tldo_lduh2_sp64): Use DImode throughout.
(*tldo_ldsh2_sp64): Likewise.
(*tldo_lduw_sp32): Merge into...
(*tldo_lduw_sp64): Likewise.
(*tldo_lduw<P:mode>): ...this and use Pmode throughout.
(*tldo_lduw1_sp64): Use DImode throughout.
(*tldo_ldsw1_sp64): Likewise.
(*tldo_ldx_sp64): Likewise.
(*tldo_stb_sp32): Merge into...
(*tldo_stb_sp64): Likewise.
(*tldo_stb<P:mode>): ...this and use Pmode throughout.
(*tldo_sth_sp32): Merge into...
(*tldo_sth_sp64): Likewise.
(*tldo_sth<P:mode>): ...this and use Pmode throughout.
(*tldo_stw_sp32): Merge into...
(*tldo_stw_sp64): Likewise.
(*tldo_stw<P:mode>): ...this and use Pmode throughout.
(*tldo_stx_sp64): Use DImode throughout.
From-SVN: r267771
Sudakshina Das [Wed, 9 Jan 2019 14:32:06 +0000 (14:32 +0000)]
[AArch64, 6/6] Enable BTI: Add configure option.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch is adding a new configure option for enabling BTI and
Return Address Signing by default.
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.c (aarch64_override_options): Add case to
check configure option to set BTI and Return Address Signing.
* configure.ac: Add --enable-standard-branch-protection and
--disable-standard-branch-protection.
* configure: Regenerated.
* doc/install.texi: Document the same.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/bti-1.c: Update test to not add command line
option when configure with bti.
* gcc.target/aarch64/bti-2.c: Likewise.
* lib/target-supports.exp
(check_effective_target_default_branch_protection):
Add configure check for --enable-standard-branch-protection.
From-SVN: r267770
Sudakshina Das [Wed, 9 Jan 2019 14:21:22 +0000 (14:21 +0000)]
[AArch64, 5/6] Enable BTI : Add new pass for BTI.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch adds a new pass called "bti" which is triggered by the command
line argument -mbranch-protection whenever "bti" is turned on.
The pass iterates through the instructions and adds appropriated BTI
instructions based on the following:
* Add a new "BTI C" at the beginning of a function, unless its already
protected by a "PACIASP". We exempt the functions that are only called
directly.
* Add a new "BTI J" for every target of an indirect jump, jump table
targets, non-local goto targets or labels that might be referenced by
variables, constant pools, etc (NOTE_INSN_DELETED_LABEL).
Since we have already changed the use of indirect tail calls to only x16 and
x17, we do not have to use "BTI JC".
(check patch 3/6).
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config.gcc (aarch64*-*-*): Add aarch64-bti-insert.o.
* gcc/config/aarch64/aarch64.h: Update comment for TRAMPOLINE_SIZE.
* config/aarch64/aarch64.c (aarch64_asm_trampoline_template): Update
if bti is enabled.
* config/aarch64/aarch64-bti-insert.c: New file.
* config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert bti
pass.
* config/aarch64/aarch64-protos.h (make_pass_insert_bti): Declare the
new bti pass.
* config/aarch64/aarch64.md (unspecv): Add UNSPECV_BTI_NOARG,
UNSPECV_BTI_C, UNSPECV_BTI_J and UNSPECV_BTI_JC.
(bti_noarg, bti_j, bti_c, bti_jc): New define_insns.
* config/aarch64/t-aarch64: Add rule for aarch64-bti-insert.o.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/bti-1.c: New test.
* gcc.target/aarch64/bti-2.c: New test.
* gcc.target/aarch64/bti-3.c: New test.
* lib/target-supports.exp
(check_effective_target_aarch64_bti_hw): Add new check for BTI hw.
Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
From-SVN: r267769
Sudakshina Das [Wed, 9 Jan 2019 14:14:28 +0000 (14:14 +0000)]
[AArch64, 4/6] Enable BTI: Add new <type> to -mbranch-protection.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This pass updates the CLI of -mbranch-protection to add "bti" as a new
type of branch protection and also add it its definition of "none" and
"standard". The option does not really do anything functional.
The functional changes are in the next patch. I am initializing the target
variable aarch64_enable_bti to 2 since I am also adding a configure option
in a later patch and a value different from 0 and 1 would help identify if its
already been updated.
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_bti_enabled): Declare.
* config/aarch64/aarch64.c (aarch64_handle_no_branch_protection):
Disable bti for -mbranch-protection=none.
(aarch64_handle_standard_branch_protection): Enable bti for
-mbranch-protection=standard.
(aarch64_handle_bti_protection): Enable bti for "bti" in the string to
-mbranch-protection.
(aarch64_bti_enabled): Check if bti is enabled.
* config/aarch64/aarch64.opt: Declare target variable.
* doc/invoke.texi: Add bti to the -mbranch-protection documentation.
From-SVN: r267768
Sudakshina Das [Wed, 9 Jan 2019 14:10:58 +0000 (14:10 +0000)]
[AArch64, 3/6] Restrict indirect tail calls to x16 and x17
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch changes the registers that are allowed for indirect tail calls.
We are choosing to restrict these to only x16 or x17.
Indirect tail calls are special in a way that they convert a call statement
(BLR instruction) to a jump statement (BR instruction). For the best possible
use of Branch Target Identification Mechanism, we would like to place a
"BTI C" (call) at the beginning of the function which is only
compatible with BLRs and BR X16/X17. In order to make indirect tail calls
compatible with this scenario, we are restricting the TAILCALL_ADDR_REGS.
In order to use x16/x17 for this purpose, we also had to change the use
of these registers in the epilogue/prologue handling. For this purpose
we are now using x12 and x13 named as EP0_REGNUM and EP1_REGNUM as
scratch registers for epilogue and prologue.
*** gcc/ChangeLog***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_prologue): Use new
epilogue/prologue scratch registers EP0_REGNUM and EP1_REGNUM.
(aarch64_expand_epilogue): Likewise.
(aarch64_output_mi_thunk): Likewise
* config/aarch64/aarch64.h (REG_CLASS_CONTENTS): Change
TAILCALL_ADDR_REGS to x16 and x17.
* config/aarch64/aarch64.md: Define EP0_REGNUM and EP1_REGNUM.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/test_frame_17.c: Update to check for EP0_REGNUM
instead of IP0_REGNUM and add test case.
From-SVN: r267767
Sudakshina Das [Wed, 9 Jan 2019 14:08:01 +0000 (14:08 +0000)]
[AArch64, 2/6] Add new arch command line feaures from ARMv8.5-A
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch add all the command line feature that are added by ARMv8.5.
Optional extensions to armv8.5-a:
+rng : Random number Generation Instructions.
+memtag : Memory Tagging Extension.
ARMv8.5-A features that are optional to older arch:
+sb : Speculation barrier instruction.
+ssbs: Speculative Store Bypass Safe instruction.
+predres: Execution and Data Prediction Restriction instructions.
All of the above only effect the assembler and have already gone in the
trunk of binutils.
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-option-extensions.def: Define
AARCH64_OPT_EXTENSION for memtag, rng, sb, ssbs and predres.
* gcc/config/aarch64/aarch64.h (AARCH64_FL_RNG): New.
(AARCH64_FL_MEMTAG, ARCH64_FL_SB, AARCH64_FL_SSBS): New.
(AARCH64_FL_PREDRES): New.
(AARCH64_FL_FOR_ARCH8_5): Add AARCH64_FL_SB, AARCH64_FL_SSBS and
AARCH64_FL_PREDRES by default.
* gcc/doc/invoke.texi: Document rng, memtag, sb, ssbs and predres.
From-SVN: r267766
Sudakshina Das [Wed, 9 Jan 2019 14:05:55 +0000 (14:05 +0000)]
[AArch64, 1/6] Enable ARMv8.5-A in gcc
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* config/aarch64/aarch64-arches.def: Define AARCH64_ARCH for
ARMv8.5-A.
* gcc/config/aarch64/aarch64.h (AARCH64_FL_V8_5): New.
(AARCH64_FL_FOR_ARCH8_5, AARCH64_ISA_V8_5): New.
* gcc/doc/invoke.texi: Document ARMv8.5-A.
From-SVN: r267765
Alejandro Martinez [Wed, 9 Jan 2019 13:57:06 +0000 (13:57 +0000)]
[Aarch64][SVE] Add copysign and xorsign support
This patch adds support for copysign and xorsign builtins to SVE. With the new
expands, they can be vectorized using bitwise logical operations.
I tested this patch in an aarch64 machine bootstrapping the compiler and
running the checks.
2019-01-09 Alejandro Martinez <alejandro.martinezvicente@arm.com>
* config/aarch64/aarch64-sve.md (copysign<mode>3): New define_expand.
(xorsign<mode>3): Likewise.
2019-01-09 Alejandro Martinez <alejandro.martinezvicente@arm.com>
* gcc.target/aarch64/sve/copysign_1.c: New test for SVE vectorized
copysign.
* gcc.target/aarch64/sve/copysign_1_run.c: Likewise.
* gcc.target/aarch64/sve/xorsign_1.c: New test for SVE vectorized
xorsign.
* gcc.target/aarch64/sve/xorsign_1_run.c: Likewise.
From-SVN: r267764
Jonathan Wakely [Wed, 9 Jan 2019 10:46:52 +0000 (10:46 +0000)]
Fix failing prettyprinter test
The failure for "p2" went unnoticed due to the pre-existing failures for
variables with similar names, like "p" and "q". This fixes the failure,
and gives the filesystem::path variables better names.
* testsuite/libstdc++-prettyprinters/cxx17.cc: Fix expected output
for filesystem::path. Give variables more distinctive names.
From-SVN: r267762
Jonathan Wakely [Wed, 9 Jan 2019 10:40:49 +0000 (10:40 +0000)]
Remove some more code duplication in std::optional
Hoist the duplicated code from the _Optional_payload partial
specializations into the _Optional_payload_base base class.
* include/std/optional (_Optional_payload_base::_M_copy_assign): New
member function to perform non-trivial assignment.
(_Optional_payload_base::_M_move_assign): Likewise.
(_Optional_payload<T, true, false, true>::operator=)
(_Optional_payload<T, true, true, false>::operator=)
(_Optional_payload<T, true, false, false>::operator=): Call
_M_copy_assign and/or _M_move_assign to do non-trivial assignments.
From-SVN: r267761
Jakub Jelinek [Wed, 9 Jan 2019 10:24:43 +0000 (11:24 +0100)]
re PR middle-end/88758 (186.crafty in SPEC CPU 2000 failed to build)
PR middle-end/88758
* tree.c (initializer_each_zero_or_onep) <case VECTOR_CST>: Use
vector_cst_elt instead of VECTOR_CST_ENCODED_ELT.
From-SVN: r267760
Jakub Jelinek [Wed, 9 Jan 2019 10:16:10 +0000 (11:16 +0100)]
re PR rtl-optimization/88331 (ICE in rtl_verify_bb_layout, at cfgrtl.c:2987)
PR rtl-optimization/88331
* function.c (assign_stack_local_1): Don't set dynamic_align_addr if
not currently_expanding_to_rtl.
* gcc.target/i386/pr88331.c: New test.
From-SVN: r267758
Jonathan Wakely [Wed, 9 Jan 2019 09:37:34 +0000 (09:37 +0000)]
PR libstdc++/88204 disable std::complex<long double> tests
The IBM128 long double format isn't foldable in constant expressions, so
conditionally skip the std::complex<long double> cases when they'll
fail.
PR libstdc++/88204
* testsuite/26_numerics/complex/operators/more_constexpr.cc: Do not
test std::complex<long double> if long double format is IBM128.
* testsuite/26_numerics/complex/requirements/more_constexpr.cc:
Likewise.
From-SVN: r267757
Paolo Carlini [Wed, 9 Jan 2019 08:52:38 +0000 (08:52 +0000)]
decl.c (grok_reference_init): Improve error location.
/cp
2019-01-08 Paolo Carlini <paolo.carlini@oracle.com>
* decl.c (grok_reference_init): Improve error location.
(grokdeclarator): Likewise, improve two locations.
/testsuite
2019-01-08 Paolo Carlini <paolo.carlini@oracle.com>
* g++.dg/diagnostic/constexpr2.C: New.
* g++.dg/diagnostic/ref3.C: Likewise.
From-SVN: r267756
Eric Botcazou [Wed, 9 Jan 2019 08:25:14 +0000 (08:25 +0000)]
invoke.texi (-Os): Remove trailing spaces.
* doc/invoke.texi (-Os): Remove trailing spaces.
(-finline-functions): Remove reference to -O2.
From-SVN: r267753
Sebastian Huber [Wed, 9 Jan 2019 06:16:05 +0000 (06:16 +0000)]
libgomp: Reduce copy and paste for RTEMS
libgomp/
* config/rtems/bar.c: Include "../linux/bar.c" and delete copy
and paste code.
From-SVN: r267752
Sebastian Huber [Wed, 9 Jan 2019 06:14:15 +0000 (06:14 +0000)]
libgomp: Avoid complex dependencies for RTEMS
libgomp/
* config/rtems/affinity-fmt.c: New file. Include affinity-fmt.c,
undefining HAVE_GETPID and HAVE_GETHOSTNAME, and mapping fwrite to
write.
From-SVN: r267751
GCC Administrator [Wed, 9 Jan 2019 00:16:18 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r267750
Tom de Vries [Wed, 9 Jan 2019 00:07:55 +0000 (00:07 +0000)]
[libgomp, testsuite, openacc] Don't use const int for dimensions
Const int is handled differently at -O0 for -xc and -xc++, which can cause noise
in testsuite/libgomp.oacc-c-c++-common test-cases (which are both run for c and
c++) if const int is used for launch dimensions.
Fix this by using #defines instead.
2019-01-09 Tom de Vries <tdevries@suse.de>
PR target/88756
* testsuite/libgomp.oacc-c-c++-common/reduction-1.c (ng, nw, vl): Use
#define instead of "const int".
* testsuite/libgomp.oacc-c-c++-common/reduction-2.c (ng, nw, vl): Same.
* testsuite/libgomp.oacc-c-c++-common/reduction-3.c (ng, nw, vl): Same.
* testsuite/libgomp.oacc-c-c++-common/reduction-4.c (ng, nw, vl): Same.
* testsuite/libgomp.oacc-c-c++-common/reduction-5.c (ng, nw, vl): Same.
From-SVN: r267747
Tom de Vries [Wed, 9 Jan 2019 00:07:45 +0000 (00:07 +0000)]
[nvptx, libgomp] Don't launch with num_workers == 0
When using a compiler build with:
...
+#define PTX_DEFAULT_VECTOR_LENGTH PTX_CTA_SIZE
+#define PTX_MAX_VECTOR_LENGTH PTX_CTA_SIZE
...
and running the libgomp testsuite, we run into an execution failure in
parallel-loop-1.c, due to a cuda launch failure:
...
nvptx_exec: kernel f6_none_none$_omp_fn$0: launch gangs=480, workers=0, \
vectors=1024
libgomp: cuLaunchKernel error: invalid argument
...
because workers == 0.
The workers variable is set to 0 here in nvptx_exec:
...
workers = blocks / actual_vectors;
...
because actual_vectors is 1024, and blocks is 768:
...
cuOccupancyMaxPotentialBlockSize: grid = 10, block = 768
...
Fix this by ensuring that workers is at least one.
2019-01-09 Tom de Vries <tdevries@suse.de>
* plugin/plugin-nvptx.c (nvptx_exec): Make sure to launch with at least
one worker.
From-SVN: r267746
Ian Lance Taylor [Wed, 9 Jan 2019 00:05:12 +0000 (00:05 +0000)]
compiler: use int type for len & cap in slice value
Slice value expression has backend type a struct of a pointer and
two ints. Make sure the len and cap are converted to int when
creating slice value expression.
Reviewed-on: https://go-review.googlesource.com/c/156897
From-SVN: r267745
Marek Polacek [Tue, 8 Jan 2019 23:54:47 +0000 (23:54 +0000)]
re PR c++/88744 (class non-type template parameters doesn't work with default template parameters)
PR c++/88744
* g++.dg/cpp2a/nontype-class12.C: New test.
From-SVN: r267744
Jonathan Wakely [Tue, 8 Jan 2019 23:15:49 +0000 (23:15 +0000)]
Pretty printer test fixes and improvements
Test that StdUniquePtrPrinter correctly prints std::unique_ptr objects
using the old layout, prior to the PR libstdc++/77990 changes.
The printer test for a valueless std::variant started to fail because
the PR libstdc++/87431 fix meant it no longer became valueless. Change
the test to use a type that is not trivially copyable, so that the
exception causes it to become valueless.
* testsuite/libstdc++-prettyprinters/compat.cc: Test printer support
for old std::unique_ptr layout.
* testsuite/libstdc++-prettyprinters/cxx17.cc: Fix std::variant test
to become valueless. Add filesystem::path tests.
From-SVN: r267743
Jonathan Wakely [Tue, 8 Jan 2019 23:00:46 +0000 (23:00 +0000)]
PR libstdc++/87855 fix optional for types with non-trivial copy/move
When the contained value is not trivially copy (or move) constructible
the union's copy (or move) constructor will be deleted, and so the
_Optional_payload delegating constructors are invalid. G++ fails to
diagnose this because it incorrectly performs copy elision in the
delegating constructors. Clang does diagnose it (llvm.org/PR40245).
The solution is to avoid performing any copy (or move) when the
contained value's copy (or move) constructor isn't trivial. Instead the
contained value can be constructed by calling _M_construct. This is OK,
because the relevant constructor doesn't need to be constexpr when the
contained value isn't trivially copy (or move) constructible.
Additionally, this patch removes a lot of code duplication in the
_Optional_payload partial specializations and the _Optional_base partial
specialization, by hoisting it into common base classes.
The Python pretty printer for std::optional needs to be adjusted to
support the new layout. Retain support for the old layout, and add a
test to verify that the support still works.
PR libstdc++/87855
* include/std/optional (_Optional_payload_base): New class template
for common code hoisted from _Optional_payload specializations. Use
a template for the union, to allow a partial specialization for
types with non-trivial destructors. Add constructors for in-place
initialization to the union.
(_Optional_payload(bool, const _Optional_payload&)): Use _M_construct
to perform non-trivial copy construction, instead of relying on
non-standard copy elision in a delegating constructor.
(_Optional_payload(bool, _Optional_payload&&)): Likewise for
non-trivial move construction.
(_Optional_payload): Derive from _Optional_payload_base and use it
for everything except the non-trivial assignment operators, which are
defined as needed.
(_Optional_payload<false, C, M>): Derive from the specialization
_Optional_payload<true, false, false> and add a destructor.
(_Optional_base_impl::_M_destruct, _Optional_base_impl::_M_reset):
Forward to corresponding members of _Optional_payload.
(_Optional_base_impl::_M_is_engaged, _Optional_base_impl::_M_get):
Hoist common members from _Optional_base.
(_Optional_base): Make all members and base class public.
(_Optional_base::_M_get, _Optional_base::_M_is_engaged): Move to
_Optional_base_impl.
* python/libstdcxx/v6/printers.py (StdExpOptionalPrinter): Add
support for new std::optional layout.
* testsuite/libstdc++-prettyprinters/compat.cc: New test.
From-SVN: r267742
Marek Polacek [Tue, 8 Jan 2019 22:33:04 +0000 (22:33 +0000)]
PR c++/88538 - braced-init-list in template-argument-list.
* parser.c (cp_parser_template_argument): Handle braced-init-list when
in C++20.
* g++.dg/cpp2a/nontype-class11.C: New test.
From-SVN: r267741
Jakub Jelinek [Tue, 8 Jan 2019 22:29:56 +0000 (23:29 +0100)]
re PR rtl-optimization/79593 (Poor/Worse code generation for FPU on versions after 6)
PR rtl-optimization/79593
* config/i386/i386.md (reg = mem; mem = reg): New define_peephole2.
From-SVN: r267740
Jakub Jelinek [Tue, 8 Jan 2019 21:36:21 +0000 (22:36 +0100)]
re PR target/88457 (ICE: Max. number of generated reload insns per insn is achieved (90))
PR target/88457
* gcc.target/powerpc/pr88457.c: Remove -m32, -c and -mcpu=e300c3 from
dg-options. Require ppc_cpu_supports_hw effective target instead of
powerpc64*-*-*.
From-SVN: r267739
Jakub Jelinek [Tue, 8 Jan 2019 21:35:38 +0000 (22:35 +0100)]
rs6000.c (rs6000_delegitimize_address): Delegitimize UNSPEC_FUSION_GPR to its argument.
* config/rs6000/rs6000.c (rs6000_delegitimize_address): Delegitimize
UNSPEC_FUSION_GPR to its argument. Formatting fixes.
From-SVN: r267738
Janus Weil [Tue, 8 Jan 2019 19:29:01 +0000 (20:29 +0100)]
re PR fortran/88047 (ICE in gfc_find_vtab, at fortran/class.c:2843)
2019-01-08 Janus Weil <janus@gcc.gnu.org>
PR fortran/88047
* class.c (gfc_find_vtab): For polymorphic typespecs, the components of
the class container may not be available (in case of invalid code).
2019-01-08 Janus Weil <janus@gcc.gnu.org>
PR fortran/88047
* gfortran.dg/class_69.f90: New test case.
From-SVN: r267735
Eric Botcazou [Tue, 8 Jan 2019 19:09:52 +0000 (19:09 +0000)]
re PR bootstrap/88721 (-Wmaybe-uninitialized warnings in sparc.c)
PR bootstrap/88721
* config/sparc/sparc.c (function_arg_slotno): Set *PPREGNO & *PPADDING
to -1 on entry.
PR debug/88723
* config/sparc/sparc.c (sparc_delegitimize_address): Deal with naked
UNSPECs and UNSPEC_MOVE_GOTDATA specifically.
From-SVN: r267734
H.J. Lu [Tue, 8 Jan 2019 17:40:18 +0000 (17:40 +0000)]
x86: Don't generate vzeroupper if caller passes AVX/AVX512 registers
There is no need to generate vzeroupper if caller passes arguments in
AVX/AVX512 registers.
Tested on i686 and x86-64 with and without --with-arch=native.
gcc/
PR target/88717
* config/i386/i386.c (ix86_avx_u128_mode_exit): Call
ix86_avx_u128_mode_entry.
gcc/testsuite/
PR target/88717
* gcc.target/i386/pr88717.c: New test.
From-SVN: r267732
Marek Polacek [Tue, 8 Jan 2019 17:37:51 +0000 (17:37 +0000)]
PR c++/88548 - this accepted in static member functions.
* parser.c (cp_debug_parser): Adjust printing of
local_variables_forbidden_p.
(cp_parser_new): Set local_variables_forbidden_p to 0 rather than false.
(cp_parser_primary_expression): When checking
local_variables_forbidden_p, use THIS_FORBIDDEN or
LOCAL_VARS_FORBIDDEN.
(cp_parser_lambda_body): Update the type of
local_variables_forbidden_p. Set it to 0 rather than false.
(cp_parser_condition): Adjust call to cp_parser_declarator.
(cp_parser_explicit_instantiation): Likewise.
(cp_parser_init_declarator): Likewise.
(cp_parser_declarator): New parameter. Use it.
(cp_parser_direct_declarator): New parameter. Use it to set
local_variables_forbidden_p. Adjust call to cp_parser_declarator.
(cp_parser_type_id_1): Adjust call to cp_parser_declarator.
(cp_parser_parameter_declaration): Likewise.
(cp_parser_default_argument): Update the type of
local_variables_forbidden_p. Set it to LOCAL_VARS_AND_THIS_FORBIDDEN
rather than true.
(cp_parser_member_declaration): Tell cp_parser_declarator if we saw
'static' or 'friend'.
(cp_parser_exception_declaration): Adjust call to cp_parser_declarator.
(cp_parser_late_parsing_default_args): Update the type of
local_variables_forbidden_p. Set it to LOCAL_VARS_AND_THIS_FORBIDDEN
rather than true.
(cp_parser_cache_defarg): Adjust call to cp_parser_declarator.
(cp_parser_objc_class_ivars): Likewise.
(cp_parser_objc_struct_declaration): Likewise.
(cp_parser_omp_for_loop_init): Likewise.
* parser.h (cp_parser): Change the type of local_variables_forbidden_p
to unsigned char.
(LOCAL_VARS_FORBIDDEN, LOCAL_VARS_AND_THIS_FORBIDDEN, THIS_FORBIDDEN):
Define.
* g++.dg/cpp0x/this1.C: New test.
From-SVN: r267731
Martin Liska [Tue, 8 Jan 2019 14:45:28 +0000 (15:45 +0100)]
Use proper type in linear transformation in tree-switch-conversion (PR tree-optimization/88753).
2019-01-08 Martin Liska <mliska@suse.cz>
PR tree-optimization/88753
* tree-switch-conversion.c (switch_conversion::build_one_array):
Come up with local variable constructor. Convert first to
type of constructor values.
2019-01-08 Martin Liska <mliska@suse.cz>
PR tree-optimization/88753
* gcc.dg/tree-ssa/pr88753.c: New test.
From-SVN: r267728
Jonathan Wakely [Tue, 8 Jan 2019 13:25:19 +0000 (13:25 +0000)]
PR libstdc++/88066 use <> for includes not ""
Using #include "..." to include a header in the same directory fails if
the user compiles with -I-, so always use something like <bits/...> for
internal headers.
I haven't added tests for this, because dg-options adds options to the
end, and the position of -I- matters (if it's at the end then the tests
won't find any headers in the build tree, as they're specified by -I
options earlier in the flags). It's been manually tested though.
PR libstdc++/88066
* include/bits/locale_conv.h: Use <> for includes not "".
* include/ext/random: Likewise.
* include/ext/vstring.h: Likewise.
From-SVN: r267726
Richard Biener [Tue, 8 Jan 2019 13:05:47 +0000 (13:05 +0000)]
re PR middle-end/86554 (Incorrect code generation with signed/unsigned comparison)
2019-01-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/86554
* tree-ssa-sccvn.c (eliminate_dom_walker, rpo_elim,
rpo_avail): Move earlier.
(visit_nary_op): When value-numbering to expressions
with different overflow behavior make sure there's an
available expression on the path.
* gcc.dg/torture/pr86554-1.c: New testcase.
* gcc.dg/torture/pr86554-2.c: Likewise.
From-SVN: r267725
Rainer Orth [Tue, 8 Jan 2019 12:04:38 +0000 (12:04 +0000)]
Fix libstdc++.so link on Solaris with C++17 std::basic_string member functions
* config/abi/pre/gnu.ver (GLIBCXX_3.4): Tighten existing patterns.
(GLIBCXX_3.4.21): Likewise.
From-SVN: r267723
Paolo Carlini [Tue, 8 Jan 2019 11:52:46 +0000 (11:52 +0000)]
thread1.C: Tweak expected error #line 13 to cover target variance.
2019-01-08 Paolo Carlini <paolo.carlini@oracle.com>
* g++.dg/diagnostic/thread1.C: Tweak expected error #line 13 to
cover target variance.
From-SVN: r267722
Richard Biener [Tue, 8 Jan 2019 10:46:04 +0000 (10:46 +0000)]
re PR fortran/88611 (ICE in eliminate_stmt, at tree-ssa-sccvn.c:5011)
2019-01-08 Richard Biener <rguenther@suse.de>
PR fortran/88611
* trans-expr.c (gfc_conv_initializer): For ISOCBINDING_NULL_*
directly build the expected GENERIC tree.
* gfortran.dg/pr88611.f90: New testcase.
From-SVN: r267721
Sam Tebbs [Tue, 8 Jan 2019 10:31:11 +0000 (10:31 +0000)]
[PATCH 2/3][GCC][AARCH64] Add new -mbranch-protection option to combine pointer signing and BTI
gcc/ChangeLog:
2019-01-08 Sam Tebbs <sam.tebbs@arm.com>
* config/aarch64/aarch64.c (BRANCH_PROTECT_STR_MAX,
aarch64_parse_branch_protection,
struct aarch64_branch_protect_type,
aarch64_handle_no_branch_protection,
aarch64_handle_standard_branch_protection,
aarch64_validate_mbranch_protection,
aarch64_handle_pac_ret_protection,
aarch64_handle_attr_branch_protection,
accepted_branch_protection_string,
aarch64_pac_ret_subtypes,
aarch64_branch_protect_types,
aarch64_handle_pac_ret_leaf): Define.
(aarch64_override_options_after_change_1, aarch64_override_options):
Add check for accepted_branch_protection_string.
(aarch64_option_save): Save accepted_branch_protection_string.
(aarch64_option_restore): Save accepted_branch_protection_string.
* config/aarch64/aarch64.c (aarch64_attributes): Add branch-protection.
* config/aarch64/aarch64.opt: Add mbranch-protection. Deprecate
msign-return-address.
* doc/invoke.texi: Add mbranch-protection.
gcc/testsuite/Changelog:
2019-01-08 Sam Tebbs <sam.tebbs@arm.com>
* gcc.target/aarch64/(return_address_sign_1.c,
return_address_sign_2.c, return_address_sign_3.c (__attribute__)):
Change option to -mbranch-protection.
* gcc.target/aarch64/(branch-protection-option.c,
branch-protection-option-2.c, branch-protection-attr.c,
branch-protection-attr-2.c): New file.
From-SVN: r267717
Jonathan Wakely [Tue, 8 Jan 2019 10:18:54 +0000 (10:18 +0000)]
PR libstdc++/88749 fix build failure in src/filesystem/ops.cc
PR libstdc++/88749
* src/filesystem/ops.cc (last_write_time): Fix preprocessor condition
to match the one that controls whether utimbuf and utime are declared.
From-SVN: r267705
Pierre-Marie de Rodat [Tue, 8 Jan 2019 09:54:04 +0000 (09:54 +0000)]
[Ada] Bump copyright years to 2019
From-SVN: r267683
Justin Squirek [Tue, 8 Jan 2019 09:52:32 +0000 (09:52 +0000)]
[Ada] Revert recent changes in the generation of deps in ali files
Following the discovery of regressions in GPRbuild, this reverts both
r263100 and r264608:
2019-01-08 Justin Squirek <squirek@adacore.com>
Revert:
2018-07-31 Justin Squirek <squirek@adacore.com>
gcc/ada/
* lib-writ.adb (Write_With_Lines): Modfiy the generation
of dependencies within ali files so that source unit
bodies are properly listed even if said bodies are
missing. Perform legacy behavior in GNATprove mode.
* lib-writ.ads: Modify documentation to reflect current
behavior.
and:
2018-09-26 Justin Squirek <squirek@adacore.com>
gcc/ada/
* lib-writ.adb, lib-writ.ads (Write_With_Lines): Add
documentation and an extra conditional check for RCI
units so that generated ali files will list the spec
only instead of a body when a body is not found.
From-SVN: r267680
Paolo Carlini [Tue, 8 Jan 2019 09:41:36 +0000 (09:41 +0000)]
decl.c (start_decl): Improve permerror location.
/cp
2019-01-08 Paolo Carlini <paolo.carlini@oracle.com>
* decl.c (start_decl): Improve permerror location.
/testsuite
2019-01-08 Paolo Carlini <paolo.carlini@oracle.com>
* g++.dg/diagnostic/out-of-class-redeclaration.C: New.
From-SVN: r267675
Iain Sandoe [Tue, 8 Jan 2019 09:26:29 +0000 (09:26 +0000)]
teststuite - avoid parts of builtin-has-attribute tests requireing alias support.
2019-01-08 Iain Sandoe <iain@sandoe.co.uk>
gcc/testsuite/
* c-c++-common/builtin-has-attribute-3.c: Skip tests requiring symbol
alias support.
* c-c++-common/builtin-has-attribute-4.c: Likewise.
Append match for warning that ‘protected’ attribute is not supported.
From-SVN: r267674
Iain Sandoe [Tue, 8 Jan 2019 09:15:34 +0000 (09:15 +0000)]
testsuite - Require alias support for three tests.
2019-01-08 Iain Sandoe <iain@sandoe.co.uk>
gcc/testsuite/
* gcc.dg/Wmissing-attributes.c: Require alias support.
* gcc.dg/attr-copy-2.c: Likewise.
* gcc.dg/attr-copy-5.c: Likewise.
From-SVN: r267673
Jonathan Wakely [Tue, 8 Jan 2019 08:57:58 +0000 (08:57 +0000)]
re PR c++/88554 (Segfault ICE when falling off the end of a reference-returning friend operator)
PR c++/88554
* decl.c (finish_function): For -Wreturn-type don't add a return *this;
fixit hint if current_class_ref is NULL. Use a single if instead of
two nested ones.
* g++.dg/warn/Wreturn-type-11.C: New test.
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r267672
David Malcolm [Tue, 8 Jan 2019 01:39:09 +0000 (01:39 +0000)]
Fix jit test case (PR jit/88747)
Amongst other changes, r266077 updated value_range_base::dump so
that it additionally prints the type. This broke an assertion within
the jit testsuite, in jit.dg/test-sum-of-squares.c, which was checking
for:
": [-INF, n_"
but was now getting:
": signed int [-INF, n_"
The test is merely intended as a simple verification that we can read
dump files via gcc_jit_context_enable_dump.
This patch loosens the requirements on the dump so that it should work
with either version of value_range_base::dump.
gcc/testsuite/ChangeLog:
PR jit/88747
* jit.dg/test-sum-of-squares.c (verify_code): Update expected vrp
dump to reflect r266077.
From-SVN: r267671
GCC Administrator [Tue, 8 Jan 2019 00:16:40 +0000 (00:16 +0000)]
Daily bump.
From-SVN: r267670
Jakub Jelinek [Mon, 7 Jan 2019 22:55:48 +0000 (23:55 +0100)]
re PR c/88701 (Internal compiler error for valid program using compound literal with variably modified type.)
PR c/88701
* c-decl.c (build_compound_literal): If not TREE_STATIC, only pushdecl
if current_function_decl is non-NULL.
* gcc.dg/pr88701.c: New test.
From-SVN: r267667
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